[PATCH] D151397: [3/N][RISCV] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

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This commit consists of change in both clang front-end and RISC-
back-end.

In the front-end, this commit adds an additional operand to the C
intrinsics of `vaadd` that models the control of the rounding mode.

In the back-end, this commit replaces the existing `int.riscv.vaadd.*`
with `int.riscv.vaadd.rm.*` that was introduced in the previous patch
with the extra operand that models the control of the rounding mode
(`vxrm`) for RVV fixed-point intrinsics.

Note: The first 3 commit of the patch-set shows the intent to model the
rounding mode for fixed-point intrinsics by applying change to `vaadd`.
The proceeding patch will apply the change to the rest of the other
fixed-point instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151397

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaadd.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
  llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
  llvm/test/CodeGen/RISCV/rvv/vaadd.ll