[PATCH] D151337: ARM: default to arm_aapcscc (or VFP) for embedded MachO targets.

[Tim Northover via Phabricator via cfe-commits]

t.p.northover created this revision.
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These were always intended to be AAPCS targets and LLVM does treat the usual C calling convention that way, but some refactoring over time seems to have lost that so now they get lots of extra `arm_aapcscc` decoration that's not needed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151337

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/arm-macho-embedded.c
  clang/test/CodeGen/atomic-arm.c


Index: clang/test/CodeGen/atomic-arm.c
===================================================================
--- clang/test/CodeGen/atomic-arm.c
+++ clang/test/CodeGen/atomic-arm.c
@@ -22,7 +22,7 @@
 
 int lock_free_1() {
   // CHECK-LABEL: @lock_free_1
-  // CHECK-V6M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 1, ptr noundef null)
+  // CHECK-V6M:   [[RES:%.*]] = call zeroext i1 @__atomic_is_lock_free(i32 noundef 1, ptr noundef null)
   // CHECK-V6M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
   // CHECK-V6M:   ret i32 [[RES32]]
 
@@ -33,7 +33,7 @@
 
 int lock_free_4() {
   // CHECK-LABEL: @lock_free_4
-  // CHECK-V6M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 4, ptr noundef null)
+  // CHECK-V6M:   [[RES:%.*]] = call zeroext i1 @__atomic_is_lock_free(i32 noundef 4, ptr noundef null)
   // CHECK-V6M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
   // CHECK-V6M:   ret i32 [[RES32]]
 
@@ -44,11 +44,11 @@
 
 int lock_free_8() {
   // CHECK-LABEL: @lock_free_8
-  // CHECK-V6M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
+  // CHECK-V6M:   [[RES:%.*]] = call zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
   // CHECK-V6M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
   // CHECK-V6M:   ret i32 [[RES32]]
 
-  // CHECK-V7M:   [[RES:%.*]] = call arm_aapcscc zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
+  // CHECK-V7M:   [[RES:%.*]] = call zeroext i1 @__atomic_is_lock_free(i32 noundef 8, ptr noundef null)
   // CHECK-V7M:   [[RES32:%.*]] = zext i1 [[RES]] to i32
   // CHECK-V7M:   ret i32 [[RES32]]
 
Index: clang/test/CodeGen/arm-macho-embedded.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/arm-macho-embedded.c
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -triple thumbv7m-apple-unknown-macho %s -emit-llvm -o - | FileCheck %s
+
+// N.b. the default (C) calling convention for embedded MachO is AAPCS so we
+// don't want Clang generating arm_aapcscc or arm_aapcs_vfpcc for basic
+// functions.
+
+// CHECK: define void @func()
+void func() {
+}
Index: clang/lib/CodeGen/TargetInfo.cpp
===================================================================
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -6532,9 +6532,12 @@
 /// Return the default calling convention that LLVM will use.
 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
   // The default calling convention that LLVM will infer.
-  if (isEABIHF() || getTarget().getTriple().isWatchABI())
+  const llvm::Triple &TT = getTarget().getTriple();
+  if (isEABIHF() || TT.isWatchABI() ||
+      (TT.isOSBinFormatMachO() &&
+       TT.getSubArch() == llvm::Triple::ARMSubArch_v7em))
     return llvm::CallingConv::ARM_AAPCS_VFP;
-  else if (isEABI())
+  else if (isEABI() || (TT.isOSBinFormatMachO() && !TT.isOSDarwin()))
     return llvm::CallingConv::ARM_AAPCS;
   else
     return llvm::CallingConv::ARM_APCS;


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