[clang] deb63f4 - [5/11][POC][Clang][RISCV] Define tuple type variant of vlseg2e32ff
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Mon May 22 04:05:19 PDT 2023
Author: eopXD
Date: 2023-05-22T04:05:14-07:00
New Revision: deb63f4a54e66b44e81ccc249f5c9ae786b16d27
URL: https://github.com/llvm/llvm-project/commit/deb63f4a54e66b44e81ccc249f5c9ae786b16d27
DIFF: https://github.com/llvm/llvm-project/commit/deb63f4a54e66b44e81ccc249f5c9ae786b16d27.diff
LOG: [5/11][POC][Clang][RISCV] Define tuple type variant of vlseg2e32ff
For the cover letter of this patch-set, please checkout D146872.
Depends on D147774.
This is the 5th patch of the patch-set.
This patch is a proof-of-concept and will be extended to full coverage
in the future. Currently, the old non-tuple unit-stride fault-first
segment load is not removed, and only signed integer unit-stride
fault-first segment load of NF=2, EEW=32 is defined here.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D147911
Added:
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff_tuple.c
Modified:
clang/include/clang/Basic/riscv_vector.td
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 81f8da8b824d6..42375c265b088 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1591,11 +1591,73 @@ multiclass RVVUnitStridedSegStoreTuple<string op> {
}
}
}
+
+multiclass RVVUnitStridedSegLoadFFTuple<string op> {
+ foreach type = ["i"] in {
+ defvar eew = !cond(!eq(type, "i") : "32");
+ foreach nf = [2] in {
+ let Name = op # nf # "e" # eew # "ff_v_tuple",
+ OverloadedName = op # nf # "e" # eew # "ff_tuple",
+ IRName = op # nf # "ff",
+ MaskedIRName = op # nf # "ff_mask",
+ NF = nf,
+ ManualCodegen = [{
+ {
+ assert(((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
+ (!IsMasked && (PolicyAttrs & RVV_VTA))) &&
+ "FIXME: Only handling default policy (TAMA) for now");
+
+ llvm::Type *ElementVectorType = cast<StructType>(ResultType)->elements()[0];
+
+ IntrinsicTypes = {ElementVectorType, Ops.back()->getType()};
+ SmallVector<llvm::Value*, 12> Operands;
+
+ Operands.append(NF, llvm::PoisonValue::get(ElementVectorType));
+
+ unsigned Offset = IsMasked ? 1 : 0;
+ Operands.push_back(Ops[Offset]); // Ptr
+ if (IsMasked)
+ Operands.push_back(Ops[0]);
+ Operands.push_back(Ops[Offset + 2]); // vl
+ if (IsMasked)
+ Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
+
+ llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
+
+ llvm::Value *LoadValue = Builder.CreateCall(F, Operands, "");
+ // Get alignment from the new vl operand
+ clang::CharUnits Align =
+ CGM.getNaturalPointeeTypeAlignment(E->getArg(Offset + 1)->getType());
+
+ llvm::Value *ReturnTuple = llvm::PoisonValue::get(ResultType);
+ for (unsigned I = 0; I < NF; ++I) {
+ llvm::Value *V = Builder.CreateExtractValue(LoadValue, {I});
+ ReturnTuple = Builder.CreateInsertValue(ReturnTuple, V, {I});
+ }
+
+ // Store new_vl
+ llvm::Value *V = Builder.CreateExtractValue(LoadValue, {NF});
+ Builder.CreateStore(V, Address(Ops[Offset + 1], V->getType(), Align));
+
+ if (ReturnValue.isNull())
+ return ReturnTuple;
+ else
+ return Builder.CreateStore(ReturnTuple, ReturnValue.getValue());
+ }
+ }] in {
+ defvar T = "(Tuple:" # nf # ")";
+ def : RVVBuiltin<"v", T # "vPCePz", type>;
+ }
+ }
+ }
+}
+
// TODO: Extend for policy
let UnMaskedPolicyScheme = NonePolicy,
MaskedPolicyScheme = NonePolicy,
IsTuple = true in {
defm : RVVUnitStridedSegLoadTuple<"vlseg">;
+defm : RVVUnitStridedSegLoadFFTuple<"vlseg">;
}
let UnMaskedPolicyScheme = NonePolicy,
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff_tuple.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff_tuple.c
new file mode 100644
index 0000000000000..1003570a9bfd5
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlseg2e32ff_tuple.c
@@ -0,0 +1,39 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x i32>, <vscale x 2 x i32> } @test_vlseg2e32ff_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, i64 } @llvm.riscv.vlseg2ff.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, ptr [[BASE]], i64 [[VL]])
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, i64 } [[TMP0]], 0
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, i64 } [[TMP0]], 1
+// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, i64 } [[TMP0]], 2
+// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8
+// CHECK-RV64-NEXT: ret { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP4]]
+//
+vint32m1x2_t test_vlseg2e32ff_v_tuple_i32m1(const int32_t *base, size_t *new_vl, size_t vl) {
+ return __riscv_vlseg2e32ff_v_tuple_i32m1(base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x i32>, <vscale x 2 x i32> } @test_vlseg2e32ff_v_tuple_i32m1_m
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { <vscale x 2 x i32>, <vscale x 2 x i32>, i64 } @llvm.riscv.vlseg2ff.mask.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, i64 } [[TMP0]], 0
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, i64 } [[TMP0]], 1
+// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP2]], <vscale x 2 x i32> [[TMP3]], 1
+// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, i64 } [[TMP0]], 2
+// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8
+// CHECK-RV64-NEXT: ret { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP4]]
+//
+vint32m1x2_t test_vlseg2e32ff_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, size_t *new_vl, size_t vl) {
+ return __riscv_vlseg2e32ff_v_tuple_i32m1_m(mask, base, new_vl, vl);
+}
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