[PATCH] D150945: [RISCV] Add missing test for ctz_32 on RV64
Jim Lin via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Sun May 21 19:31:29 PDT 2023
This revision was automatically updated to reflect the committed changes.
Closed by commit rG33d3d51d77a7: [RISCV] Add missing test for ctz_32 on RV64 (authored by Jim).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D150945/new/
https://reviews.llvm.org/D150945
Files:
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===================================================================
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -50,6 +50,18 @@
return __builtin_riscv_clz_64(a);
}
+// RV64ZBB-LABEL: @ctz_32(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT: ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+ return __builtin_riscv_ctz_32(a);
+}
+
// RV64ZBB-LABEL: @ctz_64(
// RV64ZBB-NEXT: entry:
// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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