[PATCH] D144911: adding bf16 support to NVPTX

[Jacques Pienaar via Phabricator via cfe-commits]

jpienaar added inline comments.


================
Comment at: llvm/lib/Target/NVPTX/NVPTXInstrInfo.td:3352
 
-  // Coalesce two bf16 registers into bf16x2
-  def BuildBF16x2 : NVPTXInst<(outs BFloat16x2Regs:$dst),
-                             (ins BFloat16Regs:$a, BFloat16Regs:$b),
-                             "mov.b32 \t$dst, {{$a, $b}};",
-                             [(set (v2bf16 BFloat16x2Regs:$dst),
-                               (build_vector (bf16 BFloat16Regs:$a), (bf16 BFloat16Regs:$b)))]>;
-
-  // Directly initializing underlying the b32 register is one less SASS
-  // instruction than than vector-packing move.
-  def BuildBF16x2i : NVPTXInst<(outs BFloat16x2Regs:$dst), (ins i32imm:$src),
-                              "mov.b32 \t$dst, $src;",
-                              []>;
-
-  // Split f16x2 into two f16 registers.
-  def SplitBF16x2  : NVPTXInst<(outs BFloat16Regs:$lo, BFloat16Regs:$hi),
-                              (ins BFloat16x2Regs:$src),
-                              "mov.b32 \t{{$lo, $hi}}, $src;",
-                              []>;
-  // Split an i32 into two f16
-  def SplitI32toBF16x2  : NVPTXInst<(outs BFloat16Regs:$lo, BFloat16Regs:$hi),
-                                   (ins Int32Regs:$src),
-                                   "mov.b32 \t{{$lo, $hi}}, $src;",
-                                   []>;
+  // // Coalesce two bf16 registers into bf16x2
+  // def BuildBF16x2 : NVPTXInst<(outs BFloat16x2Regs:$dst),
----------------
Could these commented parts be dropped?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D144911/new/

https://reviews.llvm.org/D144911