[PATCH] D149986: AMDGPU: Force sc0 and sc1 on stores for gfx940 and gfx941

[Konstantin Zhuravlyov via Phabricator via cfe-commits]

kzhuravl added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp:524
+         SIAtomicAddrSpace::NONE)
+      return enableSC0Bit(MI) | enableSC1Bit(MI);
+    return false;
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Pierre-vh wrote:
> kzhuravl wrote:
> > jmmartinez wrote:
> > > NIT: Is the use of the bitwise or " | " intended? I'd use the logical or " || " instead.
> > It is intentional, we need both SC0 and SC1 bits set. If I switch this to || it will short circuit and not invoke enableSC1Bit.
> IMHO then it needs a comment to explain that it's intentional, otherwise some innocent maintainer in the future could think it's a typo and change it
Added comment.


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  https://reviews.llvm.org/D149986/new/

https://reviews.llvm.org/D149986