[PATCH] D149986: AMDGPU: Force sc0 and sc1 on stores for gfx940 and gfx941

[Juan Manuel Martinez Caamaño via Phabricator via cfe-commits]

jmmartinez added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp:524
+         SIAtomicAddrSpace::NONE)
+      return enableSC0Bit(MI) | enableSC1Bit(MI);
+    return false;
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NIT: Is the use of the bitwise or " | " intended? I'd use the logical or " || " instead.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D149986/new/

https://reviews.llvm.org/D149986