[clang] 728b8a1 - [RISCV] Make zve32f imply F and zve64d imply D.
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Sat May 6 23:17:25 PDT 2023
Author: Craig Topper
Date: 2023-05-06T23:17:16-07:00
New Revision: 728b8a139804db4fd9bce1ac7fa3dcbaf4dc316c
URL: https://github.com/llvm/llvm-project/commit/728b8a139804db4fd9bce1ac7fa3dcbaf4dc316c
DIFF: https://github.com/llvm/llvm-project/commit/728b8a139804db4fd9bce1ac7fa3dcbaf4dc316c.diff
LOG: [RISCV] Make zve32f imply F and zve64d imply D.
The 1.0 vector spec PDF has text that says that Zve32f is compatible
with F or Zfinx and that Zve64d is compatible with D and Zdinx.
The references to *inx were removed from the spec in the github repository in
October 2021. The 1.0 pdf was made in September 2021.
Relevant commit https://github.com/riscv/riscv-v-spec/commit/6fedb869e213da03f36092d661d14911a2f9d2c6
Reviewed By: jacquesguan
Differential Revision: https://reviews.llvm.org/D150021
Added:
Modified:
clang/test/Driver/riscv-arch.c
llvm/docs/ReleaseNotes.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
Removed:
################################################################################
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 5b9a45deb06a2..848fc14dc95e7 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -218,16 +218,6 @@
// RV32-ORDER: error: invalid arch name 'rv32imcq',
// RV32-ORDER: standard user-level extension not given in canonical order 'q'
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32f -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE32F-ER %s
-// RV32-ZVE32F-ER: error: invalid arch name 'rv32izve32f',
-// RV32-ZVE32F-ER: 'zve32f' requires 'f' or 'zfinx' extension to also be specified
-
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64d -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE64D-ER %s
-// RV32-ZVE64D-ER: error: invalid arch name 'rv32ifzve64d',
-// RV32-ZVE64D-ER: 'zve64d' requires 'd' or 'zdinx' extension to also be specified
-
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
// RV32-ZVL64B-ER: error: invalid arch name 'rv32izvl64b',
@@ -498,10 +488,6 @@
// RV32-ZVE32X-GOODVERS: "-target-feature" "+zve32x"
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32f -### %s -c 2>&1 | \
-// RUN: FileCheck -check-prefix=RV32-ZVE32F-REQUIRE-F %s
-// RV32-ZVE32F-REQUIRE-F: error: invalid arch name 'rv32izve32f', 'zve32f' requires 'f' or 'zfinx' extension to also be specified
-
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve32f -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-ZVE32F-GOOD %s
// RV32-ZVE32F-GOOD: "-target-feature" "+zve32f"
@@ -510,18 +496,10 @@
// RV32-ZVE64X: "-target-feature" "+zve64x"
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64f -### %s -c 2>&1 | \
-// RUN: FileCheck -check-prefix=RV32-ZVE64F-REQUIRE-F %s
-// RV32-ZVE64F-REQUIRE-F: error: invalid arch name 'rv32izve64f', 'zve32f' requires 'f' or 'zfinx' extension to also be specified
-
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64f -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-ZVE64F-GOOD %s
// RV32-ZVE64F-GOOD: "-target-feature" "+zve64f"
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64d -### %s -c 2>&1 | \
-// RUN: FileCheck -check-prefix=RV32-ZVE64D-REQUIRE-D %s
-// RV32-ZVE64D-REQUIRE-D: error: invalid arch name 'rv32ifzve64d', 'zve64d' requires 'd' or 'zdinx' extension to also be specified
-
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifdzve64d -### %s -c 2>&1 | \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64d -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-ZVE64D-GOOD %s
// RV32-ZVE64D-GOOD: "-target-feature" "+zve64d"
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 845cee9e75455..2be1febb44a7a 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -176,6 +176,8 @@ Changes to the RISC-V Backend
RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and
``checkTuneCPUKind``.
* Add sifive-x280 processor.
+* Zve32f is no longer allowed with Zfinx. Zve64d is no longer allowed with
+ Zdinx.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index d25dc2b0381d1..097dffd78205a 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -856,10 +856,7 @@ Error RISCVISAInfo::checkDependency() {
bool HasD = Exts.count("d") != 0;
bool HasF = Exts.count("f") != 0;
bool HasZfinx = Exts.count("zfinx") != 0;
- bool HasZdinx = Exts.count("zdinx") != 0;
bool HasVector = Exts.count("zve32x") != 0;
- bool HasZve32f = Exts.count("zve32f") != 0;
- bool HasZve64d = Exts.count("zve64d") != 0;
bool HasZvl = MinVLen != 0;
bool HasZcmt = Exts.count("zcmt") != 0;
bool HasZcd = Exts.count("zcd") != 0;
@@ -868,22 +865,10 @@ Error RISCVISAInfo::checkDependency() {
return createStringError(errc::invalid_argument,
"'f' and 'zfinx' extensions are incompatible");
- if (HasZve32f && !HasF && !HasZfinx)
+ if (Exts.count("zvfh") && !Exts.count("zfh") && !Exts.count("zfhmin"))
return createStringError(
errc::invalid_argument,
- "'zve32f' requires 'f' or 'zfinx' extension to also be specified");
-
- if (HasZve64d && !HasD && !HasZdinx)
- return createStringError(
- errc::invalid_argument,
- "'zve64d' requires 'd' or 'zdinx' extension to also be specified");
-
- if (Exts.count("zvfh") && !Exts.count("zfh") && !Exts.count("zfhmin") &&
- !Exts.count("zhinx") && !Exts.count("zhinxmin"))
- return createStringError(
- errc::invalid_argument,
- "'zvfh' requires 'zfh', 'zfhmin', 'zhinx' or 'zhinxmin' extension to "
- "also be specified");
+ "'zvfh' requires 'zfh' or 'zfhmin extension to also be specified");
if (HasZvl && !HasVector)
return createStringError(
@@ -949,9 +934,9 @@ static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
"zkne", "zknd", "zknh"};
static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
-static const char *ImpliedExtsZve32f[] = {"zve32x"};
+static const char *ImpliedExtsZve32f[] = {"zve32x", "f"};
static const char *ImpliedExtsZve32x[] = {"zvl32b", "zicsr"};
-static const char *ImpliedExtsZve64d[] = {"zve64f"};
+static const char *ImpliedExtsZve64d[] = {"zve64f", "d"};
static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
static const char *ImpliedExtsZvfh[] = {"zve32f"};
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index ca17c68075520..d4699ee64127e 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -397,7 +397,7 @@ def FeatureStdExtZve32f
: SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
- [FeatureStdExtZve32x]>;
+ [FeatureStdExtZve32x, FeatureStdExtF]>;
def FeatureStdExtZve64x
: SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
@@ -415,13 +415,12 @@ def FeatureStdExtZve64d
: SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
- [FeatureStdExtZve64f]>;
+ [FeatureStdExtZve64f, FeatureStdExtD]>;
def FeatureStdExtV
: SubtargetFeature<"v", "HasStdExtV", "true",
"'V' (Vector Extension for Application Processors)",
- [FeatureStdExtZvl128b, FeatureStdExtZve64d,
- FeatureStdExtF, FeatureStdExtD]>;
+ [FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">,
AssemblerPredicate<
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