[clang] df722b0 - [clang-format] Don't indent Verilog `begin` keyword on its own line
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Sat May 6 22:35:48 PDT 2023
Author: sstwcw
Date: 2023-05-07T05:13:04Z
New Revision: df722b01246de56a1d3c6f5b1e7aaa881c39f642
URL: https://github.com/llvm/llvm-project/commit/df722b01246de56a1d3c6f5b1e7aaa881c39f642
DIFF: https://github.com/llvm/llvm-project/commit/df722b01246de56a1d3c6f5b1e7aaa881c39f642.diff
LOG: [clang-format] Don't indent Verilog `begin` keyword on its own line
When the line is too long and the `begin` keyword wraps to the next
line, it shouldn't be indented.
Reviewed By: HazardyKnusperkeks
Differential Revision: https://reviews.llvm.org/D149657
Added:
Modified:
clang/lib/Format/ContinuationIndenter.cpp
clang/unittests/Format/FormatTestVerilog.cpp
Removed:
################################################################################
diff --git a/clang/lib/Format/ContinuationIndenter.cpp b/clang/lib/Format/ContinuationIndenter.cpp
index fbd11a4cb48c..3ae9d1997880 100644
--- a/clang/lib/Format/ContinuationIndenter.cpp
+++ b/clang/lib/Format/ContinuationIndenter.cpp
@@ -1125,7 +1125,8 @@ unsigned ContinuationIndenter::getNewLineColumn(const LineState &State) {
Style.IndentWidth;
}
- if (NextNonComment->is(tok::l_brace) && NextNonComment->is(BK_Block)) {
+ if ((NextNonComment->is(tok::l_brace) && NextNonComment->is(BK_Block)) ||
+ (Style.isVerilog() && Keywords.isVerilogBegin(*NextNonComment))) {
if (Current.NestingLevel == 0 ||
(Style.LambdaBodyIndentation == FormatStyle::LBI_OuterScope &&
State.NextToken->is(TT_LambdaLBrace))) {
diff --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp
index a95e572b62fd..e2c9faff1fd5 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -162,6 +162,39 @@ TEST_F(FormatTestVerilog, Block) {
"x = x;");
verifyFormat("rand join x x;\n"
"x = x;");
+ // The begin keyword should not be indented if it is too long to fit on the
+ // same line.
+ verifyFormat("while (true) //\n"
+ "begin\n"
+ " while (true) //\n"
+ " begin\n"
+ " end\n"
+ "end");
+ verifyFormat("while (true) //\n"
+ "begin : x\n"
+ " while (true) //\n"
+ " begin : x\n"
+ " end : x\n"
+ "end : x");
+ verifyFormat("while (true) //\n"
+ "fork\n"
+ " while (true) //\n"
+ " fork\n"
+ " join\n"
+ "join");
+ auto Style = getDefaultStyle();
+ Style.ColumnLimit = 17;
+ verifyFormat("while (true)\n"
+ "begin\n"
+ " while (true)\n"
+ " begin\n"
+ " end\n"
+ "end",
+ "while (true) begin\n"
+ " while (true) begin"
+ " end\n"
+ "end",
+ Style);
}
TEST_F(FormatTestVerilog, Case) {
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