[PATCH] D150021: [RISCV] Make zve32f imply F and zve64d imply D.

[Craig Topper via Phabricator via cfe-commits]

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The 1.0 vector spec PDF has text that says that Zve32f is compatible
with F or Zfinx and the Zve64d is compatible with D and Zdinx.
The references to *inx were removeB from the source in the github repository in
October 2021. The 1.0 pdf was made in September 2021.

Relevant commit https://github.com/riscv/riscv-v-spec/commit/6fedb869e213da03f36092d661d14911a2f9d2c6


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150021

Files:
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td

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