[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extension in SiFive7

[Michael Maitland via Phabricator via cfe-commits]

michaelmaitland updated this revision to Diff 518923.
michaelmaitland added a comment.

Split adding sifive-x280 and vector model between this patch and https://reviews.llvm.org/D149710


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149495/new/

https://reviews.llvm.org/D149495

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

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