[PATCH] D149657: [clang-format] Stop indent Verilog `begin` keyword on single line
sstwcw via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Tue May 2 08:33:45 PDT 2023
sstwcw created this revision.
Herald added projects: All, clang, clang-format.
Herald added a subscriber: cfe-commits.
Herald added reviewers: rymiel, HazardyKnusperkeks, owenpan, MyDeveloperDay.
sstwcw requested review of this revision.
When the line is too long and the `begin` keyword wraps to the next
line, it shouldn't be indented.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D149657
Files:
clang/lib/Format/ContinuationIndenter.cpp
clang/unittests/Format/FormatTestVerilog.cpp
Index: clang/unittests/Format/FormatTestVerilog.cpp
===================================================================
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -162,6 +162,39 @@
"x = x;");
verifyFormat("rand join x x;\n"
"x = x;");
+ // The begin keyword should not be indented if it is too long to fit on the
+ // same line.
+ verifyFormat("while (true) //\n"
+ "begin\n"
+ " while (true) //\n"
+ " begin\n"
+ " end\n"
+ "end");
+ verifyFormat("while (true) //\n"
+ "begin : x\n"
+ " while (true) //\n"
+ " begin : x\n"
+ " end : x\n"
+ "end : x");
+ verifyFormat("while (true) //\n"
+ "fork\n"
+ " while (true) //\n"
+ " fork\n"
+ " join\n"
+ "join");
+ auto Style = getDefaultStyle();
+ Style.ColumnLimit = 17;
+ verifyFormat("while (true)\n"
+ "begin\n"
+ " while (true)\n"
+ " begin\n"
+ " end\n"
+ "end",
+ "while (true) begin\n"
+ " while (true) begin"
+ " end\n"
+ "end",
+ Style);
}
TEST_F(FormatTestVerilog, Case) {
Index: clang/lib/Format/ContinuationIndenter.cpp
===================================================================
--- clang/lib/Format/ContinuationIndenter.cpp
+++ clang/lib/Format/ContinuationIndenter.cpp
@@ -1125,7 +1125,8 @@
Style.IndentWidth;
}
- if (NextNonComment->is(tok::l_brace) && NextNonComment->is(BK_Block)) {
+ if ((NextNonComment->is(tok::l_brace) && NextNonComment->is(BK_Block)) ||
+ (Style.isVerilog() && Keywords.isVerilogBegin(*NextNonComment))) {
if (Current.NestingLevel == 0 ||
(Style.LambdaBodyIndentation == FormatStyle::LBI_OuterScope &&
State.NextToken->is(TT_LambdaLBrace))) {
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