[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extension in SiFive7

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:169
 
+def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
+                                      [Feature64Bit,
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I would prefer that we add sifive-x280 in a single patch with all of its features. Currently zba/zbb are in a different patch. I don't think there's any restriction about adding a feature to a CPU without it being present in the scheduler model.


Repository:
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  https://reviews.llvm.org/D149495/new/

https://reviews.llvm.org/D149495