[PATCH] D149562: [clang-format] Stop comment disrupting indentation of Verilog ports

[MyDeveloperDay via Phabricator via cfe-commits]

MyDeveloperDay added inline comments.


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Comment at: clang/include/clang/Format/Format.h:4027
+  /// is probably for the port on the following line instead of the parenthesis
+  /// it follows.
   /// \code
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This seems an odd corner case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149562/new/

https://reviews.llvm.org/D149562