[PATCH] D149561: [clang-format] Recognize Verilog edge identifiers

[sstwcw via Phabricator via cfe-commits]

sstwcw created this revision.
Herald added projects: All, clang, clang-format.
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sstwcw requested review of this revision.

Previously the event expression would be misidentified as a port list.
A line break would be added after the comma.  The events can be
separated with either a comma or the `or` keyword, and a line break
would not be inserted if the `or` keyword was used.  We changed the
behavior of the comma to match the `or` keyword.

Before:

  always @(posedge x,
           posedge y)
    x <= x;
  always @(posedge x or posedge y)
    x <= x;

After:

  always @(posedge x, posedge y)
    x <= x;
  always @(posedge x or posedge y)
    x <= x;


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D149561

Files:
  clang/lib/Format/FormatToken.h
  clang/unittests/Format/FormatTestVerilog.cpp

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