[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

[Michael Maitland via Phabricator via cfe-commits]

michaelmaitland added inline comments.


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Comment at: clang/test/Driver/riscv-cpus.c:176
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
+// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
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craig.topper wrote:
> This means the patch is dependent on the patch that adds sifive-x280?
> This means the patch is dependent on the patch that adds sifive-x280?

Added parent revision.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149498/new/

https://reviews.llvm.org/D149498