[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:181
+                                       FeatureStdExtZvfh,
+                                       FeatureStdExtZba,
+                                       FeatureStdExtZbb],
----------------
This makes the patch dependent on adding sifive-x280


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149497/new/

https://reviews.llvm.org/D149497