[clang] dc72e8f - [RISCV][NFC] skip non-RISCV target test riscv32-zihintntl.c

Piyou Chen via cfe-commits cfe-commits at lists.llvm.org
Mon Apr 24 23:15:02 PDT 2023


Author: Piyou Chen
Date: 2023-04-24T23:14:56-07:00
New Revision: dc72e8fe675866b93748d54bc5e04b14c675f476

URL: https://github.com/llvm/llvm-project/commit/dc72e8fe675866b93748d54bc5e04b14c675f476
DIFF: https://github.com/llvm/llvm-project/commit/dc72e8fe675866b93748d54bc5e04b14c675f476.diff

LOG: [RISCV][NFC] skip non-RISCV target test riscv32-zihintntl.c

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D149126

Added: 
    

Modified: 
    clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c

Removed: 
    


################################################################################
diff  --git a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
index 9126e686c4202..5276e486604de 100644
--- a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -1,3 +1,4 @@
+// REQUIRES: riscv-registered-target
 // RUN: %clang_cc1  -triple riscv32 -target-feature +v -target-feature +experimental-zihintntl -emit-llvm %s -o - \
 // RUN:     | FileCheck %s
 


        


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