[clang] cb7dffd - [RISCV] Zvk (vector crypto) specification update to 0.5.1 (Zvbb/Zvbc/Zvkt/Zvkng/Zvksg)
Alex Bradbury via cfe-commits
cfe-commits at lists.llvm.org
Thu Apr 20 10:28:53 PDT 2023
Author: Eric Gouriou
Date: 2023-04-20T18:25:19+01:00
New Revision: cb7dffdc9a83f400410657431bda14e79f6e0176
URL: https://github.com/llvm/llvm-project/commit/cb7dffdc9a83f400410657431bda14e79f6e0176
DIFF: https://github.com/llvm/llvm-project/commit/cb7dffdc9a83f400410657431bda14e79f6e0176.diff
LOG: [RISCV] Zvk (vector crypto) specification update to 0.5.1 (Zvbb/Zvbc/Zvkt/Zvkng/Zvksg)
Update the Zvk support from 0.3.x to 0.5.1, tracking the extension as
documented in
<https://github.com/riscv/riscv-crypto/releases/download/v20230407/riscv-crypto-spec-vector.pdf>.
- Zvkb is split into Zvbb and Zvbc
- Zvbc (vector carryless multiply) requires 64 bit elements (Zve64x)
- Use the extension descriptions from the specification for Zvbb/Zvbc
- Zvkt is introduced (no instructions, but adds an attribute and macro)
- Zvkn and Zvks both imply Zvkt
- Zvkng and Zvksg are introduced, adding Zvkg (GMAC) to Zvkn and Zvks
- In Zvbb, add vrev.v, vclz.v, vctz.v, vcpop.v, vwsll.{vv,vx,vi}
Differential Revision: https://reviews.llvm.org/D148483
Added:
llvm/test/MC/RISCV/rvv/zvbb.s
llvm/test/MC/RISCV/rvv/zvbc.s
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rvv/zvkg.s
Removed:
llvm/test/MC/RISCV/rvv/zvkb.s
################################################################################
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 79b7af954898d..c4135e4d3ddfa 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -49,15 +49,19 @@
// CHECK-NOT: __riscv_zcd {{.*$}}
// CHECK-NOT: __riscv_zcf {{.*$}}
// CHECK-NOT: __riscv_h {{.*$}}
-// CHECK-NOT: __riscv_zvkb {{.*$}}
+// CHECK-NOT: __riscv_zvbb {{.*$}}
+// CHECK-NOT: __riscv_zvbc {{.*$}}
// CHECK-NOT: __riscv_zvkg {{.*$}}
// CHECK-NOT: __riscv_zvkn {{.*$}}
+// CHECK-NOT: __riscv_zvkned {{.*$}}
+// CHECK-NOT: __riscv_zvkng {{.*$}}
// CHECK-NOT: __riscv_zvknha {{.*$}}
// CHECK-NOT: __riscv_zvknhb {{.*$}}
-// CHECK-NOT: __riscv_zvkned {{.*$}}
// CHECK-NOT: __riscv_zvks {{.*$}}
// CHECK-NOT: __riscv_zvksed {{.*$}}
+// CHECK-NOT: __riscv_zvksg {{.*$}}
// CHECK-NOT: __riscv_zvksh {{.*$}}
+// CHECK-NOT: __riscv_zvkt {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
@@ -526,76 +530,108 @@
// CHECK-ZFA-EXT: __riscv_zfa 2000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvkb0p3 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s
+// RUN: -march=rv32i_zve64x_zvbb0p5 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvkb0p3 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s
-// CHECK-ZVKB-EXT: __riscv_zvkb 3000{{$}}
+// RUN: -march=rv64i_zve64x_zvbb0p5 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s
+// CHECK-ZVBB-EXT: __riscv_zvbb 5000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvkg0p3 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvbc0p5 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve64x_zvbc0p5 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC-EXT %s
+// CHECK-ZVBC-EXT: __riscv_zvbc 5000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvkg0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvkg0p3 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvkg0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
-// CHECK-ZVKG-EXT: __riscv_zvkg 3000{{$}}
+// CHECK-ZVKG-EXT: __riscv_zvkg 5000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvkn0p3 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvkn0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvkn0p3 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvkn0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s
-// CHECK-ZVKN-EXT: __riscv_zvkn 3000{{$}}
+// CHECK-ZVKN-EXT: __riscv_zvkn 5000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve64x_zvkng0p5 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNG-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve64x_zvkng0p5 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNG-EXT %s
+// CHECK-ZVKNG-EXT: __riscv_zvkng 5000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvknha0p3 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvknha0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvknha0p3 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvknha0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
-// CHECK-ZVKNHA-EXT: __riscv_zvknha 3000{{$}}
+// CHECK-ZVKNHA-EXT: __riscv_zvknha 5000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve64x_zvknhb0p3 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvknhb0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve64x_zvknhb0p3 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvknhb0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
-// CHECK-ZVKNHB-EXT: __riscv_zvknhb 3000{{$}}
+// CHECK-ZVKNHB-EXT: __riscv_zvknhb 5000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvkned0p3 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvkned0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvkned0p3 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvkned0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s
-// CHECK-ZVKNED-EXT: __riscv_zvkned 3000{{$}}
+// CHECK-ZVKNED-EXT: __riscv_zvkned 5000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvks0p3 -x c -E -dM %s \
+// RUN: -march=rv32i_zve64x_zvks0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvks0p3 -x c -E -dM %s \
+// RUN: -march=rv64i_zve64x_zvks0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s
-// CHECK-ZVKS-EXT: __riscv_zvks 3000{{$}}
+// CHECK-ZVKS-EXT: __riscv_zvks 5000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvksed0p3 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvksed0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvksed0p3 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvksed0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
-// CHECK-ZVKSED-EXT: __riscv_zvksed 3000{{$}}
+// CHECK-ZVKSED-EXT: __riscv_zvksed 5000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve64x_zvksg0p5 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSG-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve64x_zvksg0p5 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSG-EXT %s
+// CHECK-ZVKSG-EXT: __riscv_zvksg 5000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zve32x_zvksh0p3 -x c -E -dM %s \
+// RUN: -march=rv32i_zve32x_zvksh0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zve32x_zvksh0p3 -x c -E -dM %s \
+// RUN: -march=rv64i_zve32x_zvksh0p5 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
-// CHECK-ZVKSH-EXT: __riscv_zvksh 3000{{$}}
+// CHECK-ZVKSH-EXT: __riscv_zvksh 5000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32i_zve32x_zvkt0p5 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64i_zve32x_zvkt0p5 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
+// CHECK-ZVKT-EXT: __riscv_zvkt 5000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index d25da91b99611..352f6c5318bc5 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -202,8 +202,8 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zvfh``
LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`__.
-``experimental-zvkb``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvkns``, ``experimental-zvks``, ``experimental-zvksed``, ``experimental-zvksh``
- LLVM implements the `0.3 draft specification <https://github.com/riscv/riscv-crypto/releases/download/v20230206/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
+``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvkns``, ``experimental-zvks``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
+ LLVM implements the `0.5 draft specification <https://github.com/riscv/riscv-crypto/releases/download/v20230407/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 4cb70884ee28c..f62177cf78a8a 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -145,15 +145,19 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"ztso", RISCVExtensionVersion{0, 1}},
// vector crypto
- {"zvkb", RISCVExtensionVersion{0, 3}},
- {"zvkg", RISCVExtensionVersion{0, 3}},
- {"zvkn", RISCVExtensionVersion{0, 3}},
- {"zvknha", RISCVExtensionVersion{0, 3}},
- {"zvknhb", RISCVExtensionVersion{0, 3}},
- {"zvkned", RISCVExtensionVersion{0, 3}},
- {"zvks", RISCVExtensionVersion{0, 3}},
- {"zvksed", RISCVExtensionVersion{0, 3}},
- {"zvksh", RISCVExtensionVersion{0, 3}},
+ {"zvbb", RISCVExtensionVersion{0, 5}},
+ {"zvbc", RISCVExtensionVersion{0, 5}},
+ {"zvkg", RISCVExtensionVersion{0, 5}},
+ {"zvkn", RISCVExtensionVersion{0, 5}},
+ {"zvkned", RISCVExtensionVersion{0, 5}},
+ {"zvkng", RISCVExtensionVersion{0, 5}},
+ {"zvknha", RISCVExtensionVersion{0, 5}},
+ {"zvknhb", RISCVExtensionVersion{0, 5}},
+ {"zvks", RISCVExtensionVersion{0, 5}},
+ {"zvksed", RISCVExtensionVersion{0, 5}},
+ {"zvksg", RISCVExtensionVersion{0, 5}},
+ {"zvksh", RISCVExtensionVersion{0, 5}},
+ {"zvkt", RISCVExtensionVersion{0, 5}},
};
static bool stripExperimentalPrefix(StringRef &Ext) {
@@ -880,8 +884,17 @@ Error RISCVISAInfo::checkDependency() {
errc::invalid_argument,
"'zvl*b' requires 'v' or 'zve*' extension to also be specified");
- if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkn") ||
- Exts.count("zvknha") || Exts.count("zvkned") || Exts.count("zvks") ||
+ if (Exts.count("zvbb") && !HasVector)
+ return createStringError(
+ errc::invalid_argument,
+ "'zvbb' requires 'v' or 'zve*' extension to also be specified");
+
+ if (Exts.count("zvbc") && !Exts.count("zve64x"))
+ return createStringError(
+ errc::invalid_argument,
+ "'zvbc' requires 'v' or 'zve64*' extension to also be specified");
+
+ if ((Exts.count("zvkg") || Exts.count("zvkned") || Exts.count("zvknha") ||
Exts.count("zvksed") || Exts.count("zvksh")) &&
!HasVector)
return createStringError(
@@ -930,9 +943,13 @@ static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
"zkne", "zknd", "zknh"};
static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
static const char *ImpliedExtsZvfh[] = {"zve32f"};
-static const char *ImpliedExtsZvkn[] = {"zvkned", "zvknhb", "zvkb"};
+static const char *ImpliedExtsZvkn[] = {"zvbb", "zvbc", "zvkned", "zvknhb",
+ "zvkt"};
+static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
static const char *ImpliedExtsZvknhb[] = {"zvknha"};
-static const char *ImpliedExtsZvks[] = {"zvksed", "zvksh", "zvkb"};
+static const char *ImpliedExtsZvks[] = {"zvbb", "zvbc", "zvksed", "zvksh",
+ "zvkt"};
+static const char *ImpliedExtsZvksg[] = {"zvks", "zvkg"};
static const char *ImpliedExtsXsfvcp[] = {"zve32x"};
static const char *ImpliedExtsXTHeadVdot[] = {"v"};
static const char *ImpliedExtsZcb[] = {"zca"};
@@ -974,8 +991,10 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"zve64x"}, {ImpliedExtsZve64x}},
{{"zvfh"}, {ImpliedExtsZvfh}},
{{"zvkn"}, {ImpliedExtsZvkn}},
+ {{"zvkng"}, {ImpliedExtsZvkng}},
{{"zvknhb"}, {ImpliedExtsZvknhb}},
{{"zvks"}, {ImpliedExtsZvks}},
+ {{"zvksg"}, {ImpliedExtsZvksg}},
{{"zvl1024b"}, {ImpliedExtsZvl1024b}},
{{"zvl128b"}, {ImpliedExtsZvl128b}},
{{"zvl16384b"}, {ImpliedExtsZvl16384b}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index b761c99faa93f..cec2f19dafcbf 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -481,12 +481,19 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
AssemblerPredicate<(all_of FeatureStdExtZawrs),
"'Zawrs' (Wait on Reservation Set)">;
-def FeatureStdExtZvkb
- : SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true",
- "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">;
-def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
- AssemblerPredicate<(all_of FeatureStdExtZvkb),
- "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">;
+def FeatureStdExtZvbb
+ : SubtargetFeature<"experimental-zvbb", "HasStdExtZvbb", "true",
+ "'Zvbb' (Vector Bit-manipulation used in Cryptography)">;
+def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvbb),
+ "'Zvbb' (Vector Bit-manipulation used in Cryptography)">;
+
+def FeatureStdExtZvbc
+ : SubtargetFeature<"experimental-zvbc", "HasStdExtZvbc", "true",
+ "'Zvbc' (Vector Carryless Multiplication)">;
+def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvbc),
+ "'Zvbc' (Vector Carryless Multiplication)">;
def FeatureStdExtZvkg
: SubtargetFeature<"experimental-zvkg", "HasStdExtZvkg", "true",
@@ -498,7 +505,19 @@ def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
def FeatureStdExtZvkn
: SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true",
"This extension is shorthand for the following set of "
- "other extensions: Zvkned, Zvknhb and Zvkb.">;
+ "other extensions: Zvkned, Zvknhb, Zvbb, Zvbc, and Zvkt.">;
+
+def FeatureStdExtZvkned
+ : SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true",
+ "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
+def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
+ AssemblerPredicate<(all_of FeatureStdExtZvkned),
+ "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
+
+def FeatureStdExtZvkng
+ : SubtargetFeature<"experimental-zvkng", "HasStdExtZvkng", "true",
+ "This extension is shorthand for the following set of "
+ "other extensions: Zvkn and Zvkg.">;
def FeatureStdExtZvknha
: SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true",
@@ -512,17 +531,10 @@ def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
AssemblerPredicate<(all_of FeatureStdExtZvknha),
"'Zvknha' (Vector SHA-2. (SHA-256 only))">;
-def FeatureStdExtZvkned
- : SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true",
- "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
-def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
- AssemblerPredicate<(all_of FeatureStdExtZvkned),
- "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
-
def FeatureStdExtZvks
: SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true",
"This extension is shorthand for the following set of "
- "other extensions: Zvksed, Zvksh and Zvkb.">;
+ "other extensions: Zvksed, Zvksh, Zvbb, Zvbc, and Zvkt.">;
def FeatureStdExtZvksed
: SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true",
@@ -531,6 +543,11 @@ def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
AssemblerPredicate<(all_of FeatureStdExtZvksed),
"'Zvksed' (SM4 Block Cipher Instructions.)">;
+def FeatureStdExtZvksg
+ : SubtargetFeature<"experimental-zvksg", "HasStdExtZvksg", "true",
+ "This extension is shorthand for the following set of "
+ "other extensions: Zvks and Zvkg.">;
+
def FeatureStdExtZvksh
: SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true",
"'Zvksh' (SM3 Hash Function Instructions.)">;
@@ -538,6 +555,10 @@ def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions.)">;
+def FeatureStdExtZvkt
+ : SubtargetFeature<"experimental-zvkt", "HasStdExtZvkt", "true",
+ "'Zvkt' (Vector Data-Independent Execution Latency )">;
+
def FeatureStdExtZicond
: SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true",
"'Zicond' (Integer Conditional Operations)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 26a48cea34b2b..1e27e4306b840 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -128,15 +128,23 @@ def rnum_2_14 : Operand<XLenVT>, ImmLeaf<XLenVT,
let OperandNamespace = "RISCVOp";
}
-let Predicates = [HasStdExtZvkb] in {
- defm VANDN_V : VALU_IV_V_X<"vandn", 0b000001>;
- def VBREV8_V : VALUVs2<0b010010, 0b01000, OPMVV, "vbrev8.v">;
- defm VCLMUL_V : VCLMUL_MV_V_X<"vclmul", 0b001100>;
+let Predicates = [HasStdExtZvbb] in {
+ defm VANDN_V : VALU_IV_V_X<"vandn", 0b000001>;
+ def VBREV8_V : VALUVs2<0b010010, 0b01000, OPMVV, "vbrev8.v">;
+ def VBREV_V : VALUVs2<0b010010, 0b01010, OPMVV, "vbrev.v">;
+ def VCLZ_V : VALUVs2<0b010010, 0b01100, OPMVV, "vclz.v">;
+ def VCPOP_V : VALUVs2<0b010010, 0b01110, OPMVV, "vcpop.v">;
+ def VCTZ_V : VALUVs2<0b010010, 0b01101, OPMVV, "vctz.v">;
+ def VREV8_V : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">;
+ defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>;
+ defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>;
+ defm VWSLL_V : VALU_IV_V_X_I<"vwsll", 0b110101, uimm5>;
+} // Predicates = [HasStdExtZvbb]
+
+let Predicates = [HasStdExtZvbc] in {
+ defm VCLMUL_V : VCLMUL_MV_V_X<"vclmul", 0b001100>;
defm VCLMULH_V : VCLMUL_MV_V_X<"vclmulh", 0b001101>;
- def VREV8_V : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">;
- defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>;
- defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>;
-} // Predicates = [HasStdExtZvkb]
+} // Predicates = [HasStdExtZvbc]
let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
def VGHSH_VV : PALUVVNoVm<0b101100, OPMVV, "vghsh.vv">;
@@ -150,21 +158,21 @@ let Predicates = [HasStdExtZvknha], RVVConstraint = NoConstraint in {
} // Predicates = [HasStdExtZvknha]
let Predicates = [HasStdExtZvkned], RVVConstraint = NoConstraint in {
- defm VAESDF : VAES_MV_V_S<0b101000, 0b101001, 0b00001, OPMVV, "vaesdf">;
- defm VAESDM : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
- defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
- defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
- def VAESKF1_VI : VAESKF_MV_I<0b100010, "vaeskf1.vi", rnum_1_10>;
- def VAESKF2_VI : VAESKF_MV_I<0b101010, "vaeskf2.vi", rnum_2_14>;
- def VAESZ_VS : PALUVs2NoVm<0b101001, 0b00111, OPMVV, "vaesz.vs">;
+ defm VAESDF : VAES_MV_V_S<0b101000, 0b101001, 0b00001, OPMVV, "vaesdf">;
+ defm VAESDM : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
+ defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
+ defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
+ def VAESKF1_VI : VAESKF_MV_I<0b100010, "vaeskf1.vi", rnum_1_10>;
+ def VAESKF2_VI : VAESKF_MV_I<0b101010, "vaeskf2.vi", rnum_2_14>;
+ def VAESZ_VS : PALUVs2NoVm<0b101001, 0b00111, OPMVV, "vaesz.vs">;
} // Predicates = [HasStdExtZvkned]
let Predicates = [HasStdExtZvksed], RVVConstraint = NoConstraint in {
- def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", rnum_0_7>;
- defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
+ def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", rnum_0_7>;
+ defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
} // Predicates = [HasStdExtZvksed]
let Predicates = [HasStdExtZvksh], RVVConstraint = NoConstraint in {
- def VSM3C_VI : PALUVINoVm<0b101011, "vsm3c.vi", uimm5>;
+ def VSM3C_VI : PALUVINoVm<0b101011, "vsm3c.vi", uimm5>;
def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">;
} // Predicates = [HasStdExtZvksh]
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 83ee6cae07b2a..5ddfad5eddb9b 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -55,15 +55,19 @@
; RUN: llc -mtriple=riscv32 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICSR %s
; RUN: llc -mtriple=riscv32 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV32ZIFENCEI %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFA %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV32ZVKB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV32ZVBB %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV32ZVBC %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV32ZVKN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV32ZVKNED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkng %s -o - | FileCheck --check-prefix=RV32ZVKNG %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV32ZVKNED %s
-; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvksg %s -o - | FileCheck --check-prefix=RV32ZVKSG %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
@@ -127,15 +131,19 @@
; RUN: llc -mtriple=riscv64 -mattr=+zicsr %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICSR %s
; RUN: llc -mtriple=riscv64 -mattr=+zifencei %s -o - | FileCheck --check-prefixes=CHECK,RV64ZIFENCEI %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFA %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkb %s -o - | FileCheck --check-prefix=RV64ZVKB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbb %s -o - | FileCheck --check-prefix=RV64ZVBB %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV64ZVBC %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV64ZVKN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV64ZVKNED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkng %s -o - | FileCheck --check-prefix=RV64ZVKNG %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV64ZVKNED %s
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvksg %s -o - | FileCheck --check-prefix=RV64ZVKSG %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
; CHECK: .attribute 4, 16
@@ -194,15 +202,19 @@
; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0"
; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2"
-; RV32ZVKB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
-; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
-; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
-; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
-; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
-; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
-; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
-; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
+; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zve32x1p0_zvl32b1p0"
+; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p5_zvl32b1p0"
+; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkn0p5_zvkned0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p5_zvl32b1p0"
+; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvkn0p5_zvkned0p5_zvkng0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
+; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p5_zvl32b1p0"
+; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p5_zvknhb0p5_zvl32b1p0_zvl64b1p0"
+; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvks0p5_zvksed0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p5_zvl32b1p0"
+; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvks0p5_zvksed0p5_zvksg0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
+; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p5_zvl32b1p0"
+; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt0p5_zvl32b1p0"
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
; RV64M: .attribute 5, "rv64i2p1_m2p0"
@@ -265,15 +277,19 @@
; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"
; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2"
-; RV64ZVKB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
-; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
-; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
-; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
-; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
-; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
-; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
-; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
+; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zve32x1p0_zvl32b1p0"
+; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg0p5_zvl32b1p0"
+; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkn0p5_zvkned0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned0p5_zvl32b1p0"
+; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvkn0p5_zvkned0p5_zvkng0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
+; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha0p5_zvl32b1p0"
+; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p5_zvknhb0p5_zvl32b1p0_zvl64b1p0"
+; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvks0p5_zvksed0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
+; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed0p5_zvl32b1p0"
+; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvks0p5_zvksed0p5_zvksg0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
+; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh0p5_zvl32b1p0"
+; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt0p5_zvl32b1p0"
; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
define i32 @addi(i32 %a) {
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index dfc00074fceaf..ef5a95c715fb8 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -111,32 +111,44 @@
.attribute arch, "rv32izbc1p0"
# CHECK: attribute 5, "rv32i2p1_zbc1p0"
-.attribute arch, "rv32i_zve64x_zvkb0p3"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvbb0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve32x_zvkg0p3"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
+.attribute arch, "rv32i_zve64x_zvbc0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve64x_zvkn0p3"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve32x_zvkg0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p5_zvl32b1p0"
-.attribute arch, "rv32i_zve32x_zvknha0p3"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
+.attribute arch, "rv32i_zve64x_zvkn0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkn0p5_zvkned0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve64x_zvknhb0p3"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvkng0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvkn0p5_zvkned0p5_zvkng0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve32x_zvkned0p3"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvknha0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p5_zvl32b1p0"
-.attribute arch, "rv32i_zve32x_zvks0p3"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
+.attribute arch, "rv32i_zve64x_zvknhb0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p5_zvknhb0p5_zvl32b1p0_zvl64b1p0"
-.attribute arch, "rv32i_zve32x_zvksed0p3"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvkned0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p5_zvl32b1p0"
-.attribute arch, "rv32i_zve32x_zvksh0p3"
-# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
+.attribute arch, "rv32i_zve64x_zvks0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvks0p5_zvksed0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32i_zve64x_zvksg0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvks0p5_zvksed0p5_zvksg0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
+
+.attribute arch, "rv32i_zve32x_zvksed0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p5_zvl32b1p0"
+
+.attribute arch, "rv32i_zve32x_zvksh0p5"
+# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p5_zvl32b1p0"
+
+.attribute arch, "rv32i_zvkt0p5"
+# CHECK: attribute 5, "rv32i2p1_zvkt0p5"
.attribute arch, "rv32izbs1p0"
# CHECK: attribute 5, "rv32i2p1_zbs1p0"
diff --git a/llvm/test/MC/RISCV/rvv/zvbb.s b/llvm/test/MC/RISCV/rvv/zvbb.s
new file mode 100644
index 0000000000000..e32b6e46f9b54
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvbb.s
@@ -0,0 +1,105 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvbb %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvbb %s \
+# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvbb - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvbb %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vandn.vv v10, v9, v8, v0.t
+# CHECK-INST: vandn.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 05 94 04 <unknown>
+
+vandn.vx v10, v9, a0, v0.t
+# CHECK-INST: vandn.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 45 95 04 <unknown>
+
+vbrev8.v v10, v9, v0.t
+# CHECK-INST: vbrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0x25,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 25 94 48 <unknown>
+
+vbrev.v v10, v9, v0.t
+# CHECK-INST: vbrev.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0x25,0x95,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 25 95 48 <unknown>
+
+vclz.v v10, v9, v0.t
+# CHECK-INST: vclz.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0x25,0x96,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 25 96 48 <unknown>
+
+vcpop.v v10, v9, v0.t
+# CHECK-INST: vcpop.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0x25,0x97,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 25 97 48 <unknown>
+
+vctz.v v10, v9, v0.t
+# CHECK-INST: vctz.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0xa5,0x96,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 a5 96 48 <unknown>
+
+vrev8.v v10, v9, v0.t
+# CHECK-INST: vrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0xa5,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 a5 94 48 <unknown>
+
+vrol.vv v10, v9, v8, v0.t
+# CHECK-INST: vrol.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 05 94 54 <unknown>
+
+vrol.vx v10, v9, a0, v0.t
+# CHECK-INST: vrol.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 45 95 54 <unknown>
+
+vror.vv v10, v9, v8, v0.t
+# CHECK-INST: vror.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 05 94 50 <unknown>
+
+vror.vx v10, v9, a0, v0.t
+# CHECK-INST: vror.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x50]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 45 95 50 <unknown>
+
+vror.vi v10, v9, 33, v0.t
+# CHECK-INST: vror.vi v10, v9, 33, v0.t
+# CHECK-ENCODING: [0x57,0xb5,0x90,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 b5 90 54 <unknown>
+
+vwsll.vv v10, v9, v8, v0.t
+# CHECK-INST: vwsll.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0xd4]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 05 94 d4 <unknown>
+
+vwsll.vx v10, v9, a0, v0.t
+# CHECK-INST: vwsll.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0xd4]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 45 95 d4 <unknown>
+
+vwsll.vi v10, v9, 29, v0.t
+# CHECK-INST: vwsll.vi v10, v9, 29, v0.t
+# CHECK-ENCODING: [0x57,0xb5,0x9e,0xd4]
+# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 b5 9e d4 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/zvbc.s b/llvm/test/MC/RISCV/rvv/zvbc.s
new file mode 100644
index 0000000000000..9c1f7873248d9
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/zvbc.s
@@ -0,0 +1,33 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve64x --mattr=+experimental-zvbc %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvbc %s \
+# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+experimental-zvbc - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvbc %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vclmul.vv v10, v9, v8
+# CHECK-INST: vclmul.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x25,0x94,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}}
+# CHECK-UNKNOWN: 57 25 94 32 <unknown>
+
+vclmul.vx v10, v9, a0
+# CHECK-INST: vclmul.vx v10, v9, a0
+# CHECK-ENCODING: [0x57,0x65,0x95,0x32]
+# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}}
+# CHECK-UNKNOWN: 57 65 95 32 <unknown>
+
+vclmulh.vv v10, v9, v8
+# CHECK-INST: vclmulh.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x25,0x94,0x36]
+# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}}
+# CHECK-UNKNOWN: 57 25 94 36 <unknown>
+
+vclmulh.vx v10, v9, a0
+# CHECK-INST: vclmulh.vx v10, v9, a0
+# CHECK-ENCODING: [0x57,0x65,0x95,0x36]
+# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}}
+# CHECK-UNKNOWN: 57 65 95 36 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/zvkb.s b/llvm/test/MC/RISCV/rvv/zvkb.s
deleted file mode 100644
index a237b7d2eecdc..0000000000000
--- a/llvm/test/MC/RISCV/rvv/zvkb.s
+++ /dev/null
@@ -1,87 +0,0 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkb %s \
-# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
-# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
-# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkb - \
-# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
-# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-
-vandn.vv v10, v9, v8, v0.t
-# CHECK-INST: vandn.vv v10, v9, v8, v0.t
-# CHECK-ENCODING: [0x57,0x05,0x94,0x04]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 05 94 04 <unknown>
-
-vandn.vx v10, v9, a0, v0.t
-# CHECK-INST: vandn.vx v10, v9, a0, v0.t
-# CHECK-ENCODING: [0x57,0x45,0x95,0x04]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 45 95 04 <unknown>
-
-vbrev8.v v10, v9, v0.t
-# CHECK-INST: vbrev8.v v10, v9, v0.t
-# CHECK-ENCODING: [0x57,0x25,0x94,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 25 94 48 <unknown>
-
-vclmul.vv v10, v9, v8
-# CHECK-INST: vclmul.vv v10, v9, v8
-# CHECK-ENCODING: [0x57,0x25,0x94,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 25 94 32 <unknown>
-
-vclmul.vx v10, v9, a0
-# CHECK-INST: vclmul.vx v10, v9, a0
-# CHECK-ENCODING: [0x57,0x65,0x95,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 65 95 32 <unknown>
-
-vclmulh.vv v10, v9, v8
-# CHECK-INST: vclmulh.vv v10, v9, v8
-# CHECK-ENCODING: [0x57,0x25,0x94,0x36]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 25 94 36 <unknown>
-
-vclmulh.vx v10, v9, a0
-# CHECK-INST: vclmulh.vx v10, v9, a0
-# CHECK-ENCODING: [0x57,0x65,0x95,0x36]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 65 95 36 <unknown>
-
-vrev8.v v10, v9, v0.t
-# CHECK-INST: vrev8.v v10, v9, v0.t
-# CHECK-ENCODING: [0x57,0xa5,0x94,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 a5 94 48 <unknown>
-
-vrol.vv v10, v9, v8, v0.t
-# CHECK-INST: vrol.vv v10, v9, v8, v0.t
-# CHECK-ENCODING: [0x57,0x05,0x94,0x54]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 05 94 54 <unknown>
-
-vrol.vx v10, v9, a0, v0.t
-# CHECK-INST: vrol.vx v10, v9, a0, v0.t
-# CHECK-ENCODING: [0x57,0x45,0x95,0x54]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 45 95 54 <unknown>
-
-vror.vv v10, v9, v8, v0.t
-# CHECK-INST: vror.vv v10, v9, v8, v0.t
-# CHECK-ENCODING: [0x57,0x05,0x94,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 05 94 50 <unknown>
-
-vror.vx v10, v9, a0, v0.t
-# CHECK-INST: vror.vx v10, v9, a0, v0.t
-# CHECK-ENCODING: [0x57,0x45,0x95,0x50]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 45 95 50 <unknown>
-
-vror.vi v10, v9, 33, v0.t
-# CHECK-INST: vror.vi v10, v9, 33, v0.t
-# CHECK-ENCODING: [0x57,0xb5,0x90,0x54]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 b5 90 54 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/zvkg.s b/llvm/test/MC/RISCV/rvv/zvkg.s
index 1533ac2ddbde7..a649bb177c4ea 100644
--- a/llvm/test/MC/RISCV/rvv/zvkg.s
+++ b/llvm/test/MC/RISCV/rvv/zvkg.s
@@ -13,3 +13,9 @@ vghsh.vv v10, v9, v8
# CHECK-ENCODING: [0x77,0x25,0x94,0xb2]
# CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography.){{$}}
# CHECK-UNKNOWN: 77 25 94 b2 <unknown>
+
+vgmul.vv v10, v9
+# CHECK-INST: vgmul.vv v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 77 a5 98 a2 <unknown>
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