[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

Craig Topper via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Wed Apr 19 10:34:10 PDT 2023


craig.topper updated this revision to Diff 515015.
craig.topper added a comment.

Renamed preprocessor define to __riscv_v_fixed_vlen. This makes it similar to the existing __riscv_v_min_vlen.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145088/new/

https://reviews.llvm.org/D145088

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/RISCVVTypes.def
  clang/include/clang/Driver/Options.td
  clang/include/clang/Sema/Overload.h
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/JSONNodeDumper.cpp
  clang/lib/AST/TextNodeDumper.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaExprCXX.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-bitcast.c
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-globals.c
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-types.c
  clang/test/CodeGen/riscv-rvv-vls-arith-ops.c
  clang/test/CodeGen/riscv-rvv-vls-bitwise-ops.c
  clang/test/CodeGen/riscv-rvv-vls-compare-ops.c
  clang/test/CodeGen/riscv-rvv-vls-shift-ops.c
  clang/test/CodeGen/riscv-rvv-vls-subscript-ops.c
  clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
  clang/test/CodeGenCXX/riscv-rvv-fixedtypeinfo.cpp
  clang/test/Driver/riscv-rvv-vector-bits.c
  clang/test/Sema/attr-riscv-rvv-vector-bits.c
  clang/test/Sema/riscv-rvv-explicit-casts-fixed-size.c
  clang/test/Sema/riscv-rvv-lax-vector-conversions.c
  clang/test/Sema/riscv-vector-types-support.c
  clang/test/SemaCXX/attr-riscv-rvv-vector-bits.cpp
  clang/test/SemaCXX/riscv-rvv-explicit-casts-fixed-size.cpp
  clang/test/SemaCXX/riscv-rvv-lax-vector-conversions.cpp

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