[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

In D145088#4276099 <https://reviews.llvm.org/D145088#4276099>, @rjmccall wrote:

> The CodeGen change looks fine.  I'm surprised you didn't need any code in argument/parameter/call/return emission to do the actual fixed<->scalable coercion; do we already have that for other reasons?

You mean RISC-V specific code or generic code? If generic, I assume we got it from SVE's earlier implementation.


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  https://reviews.llvm.org/D145088/new/

https://reviews.llvm.org/D145088