[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

Tue Apr 11 13:32:13 PDT 2023

jrtc27 added inline comments.

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Comment at: clang/lib/CodeGen/TargetInfo.cpp:11390
+    ResType = llvm::ScalableVectorType::get(
+        llvm::Type::getIntNTy(getVMContext(), XLen), 64 / XLen);
+    break;
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erichkeane wrote:
> craig.topper wrote:
> > erichkeane wrote:
> > > Where is 'XLen' from here?  
> > It's a member of RISCVABIInfo. It's 64 for riscv64 triple and 32 for riscv32 triple.
> Well, the name is awful :)  I'd probably suggest a re-name and hiding it behind a function call (since that way it can be done on the triple, rather than an initialized variable perhaps?), but I'm not really in charge of this target info.
It's not for anyone in the RISC-V space, since it is defined by the architecture and used pervasively (and means the X register LENgth, i.e. how many bits in the x0-x31 GPRs). Using anything else in a RISC-V ABI context would be worse from a RISC-V perspective. In a random LLVM checkout I have I see 1118 instances of `/xlen/i` in llvm/lib/Target/RISCV alone.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145088/new/

https://reviews.llvm.org/D145088