[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

[Erich Keane via Phabricator via cfe-commits]

erichkeane added a comment.

So I don't see any handling of the dependent version of this, we probably need tests for those at minimum.



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Comment at: clang/docs/ReleaseNotes.rst:355
+- Added ``attribute(riscv_rvv_vector_bits(__RISCV_RVV_VLEN_BITS))`` to allow
+  the size of a RVV scalable type to be specified. This allows scalable vector
+  types to be used in structs or in global variables.
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Would love it if we defined "RVV" here.


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Comment at: clang/include/clang/AST/ASTContext.h:2262
+  /// Return true if the given vector types are lax-compatible RVV vector types,
+  /// false otherwise.
+  bool areLaxCompatibleRVVTypes(QualType FirstType, QualType SecondType);
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Same here, what is 'lax compatible' mean here? And RVV?


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Comment at: clang/lib/CodeGen/TargetInfo.cpp:11369
+  llvm::ScalableVectorType *ResType = nullptr;
+  switch (BT->getKind()) {
+  default:
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I wonder if at least the inner type can be picked up ConvertType instead.  There doesn't seem to be obvious rhyme/reason to the last argument to ScalableVectorType, so it might not solve that.

However, it'll solve the long problem.


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Comment at: clang/lib/CodeGen/TargetInfo.cpp:11390
+    ResType = llvm::ScalableVectorType::get(
+        llvm::Type::getIntNTy(getVMContext(), XLen), 64 / XLen);
+    break;
----------------
Where is 'XLen' from here?  


Repository:
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https://reviews.llvm.org/D145088