[clang] 5e2d8a3 - [RISCV] Remove getCPUFeaturesExceptStdExt.
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Tue Apr 11 10:42:15 PDT 2023
Author: Craig Topper
Date: 2023-04-11T10:41:46-07:00
New Revision: 5e2d8a35288802f94df8c60513e7a835b27e621d
URL: https://github.com/llvm/llvm-project/commit/5e2d8a35288802f94df8c60513e7a835b27e621d
DIFF: https://github.com/llvm/llvm-project/commit/5e2d8a35288802f94df8c60513e7a835b27e621d.diff
LOG: [RISCV] Remove getCPUFeaturesExceptStdExt.
This function was used to force +64bit or -64bit into the feature
string basd on -mcpu.
It's not entirely clear to me why this was needed. This informationo
is redundant with the triple. RISCVTargetInfo::initFeatureMap
independently recomputes it from the triple for the feature map.
It is ultimately needed in the backend, but that should be handled
by RISCVSubtarget processing the CPU name.
Differential Revision: https://reviews.llvm.org/D147978
Added:
Modified:
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Driver/riscv-cpus.c
llvm/include/llvm/TargetParser/RISCVTargetParser.h
llvm/lib/TargetParser/RISCVTargetParser.cpp
Removed:
################################################################################
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index da120d95b42f..887442222210 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -53,8 +53,7 @@ static bool getRISCFeaturesFromMcpu(const llvm::Triple &Triple, StringRef Mcpu,
std::vector<StringRef> &Features) {
bool Is64Bit = Triple.isRISCV64();
llvm::RISCV::CPUKind CPUKind = llvm::RISCV::parseCPUKind(Mcpu);
- return llvm::RISCV::checkCPUKind(CPUKind, Is64Bit) &&
- llvm::RISCV::getCPUFeaturesExceptStdExt(CPUKind, Features);
+ return llvm::RISCV::checkCPUKind(CPUKind, Is64Bit);
}
void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 7a08b8c10956..a57cbf1e0e25 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -7,20 +7,17 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=rocket-rv64 | FileCheck -check-prefix=MCPU-ROCKET64 %s
// MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
// MCPU-ROCKET64: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-ROCKET64: "-target-feature" "+64bit"
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-base | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-BASE %s
// MCPU-SYNTACORE-SCR1-BASE: "-target-cpu" "syntacore-scr1-base"
// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c"
// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "-64bit"
// MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32"
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-max | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-MAX %s
// MCPU-SYNTACORE-SCR1-MAX: "-target-cpu" "syntacore-scr1-max"
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c"
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "-64bit"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
// We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
@@ -92,7 +89,6 @@
// MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a"
// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c"
// MCPU-ABI-SIFIVE-S21: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-ABI-SIFIVE-S21: "-target-feature" "+64bit"
// MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64"
// mcpu with mabi option
@@ -101,7 +97,6 @@
// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c"
// MCPU-ABI-SIFIVE-S51: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-ABI-SIFIVE-S51: "-target-feature" "+64bit"
// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
// mcpu with default march
@@ -110,7 +105,6 @@
// MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
// MCPU-SIFIVE-S54: "-target-feature" "+c"
// MCPU-SIFIVE-S54: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-SIFIVE-S54: "-target-feature" "+64bit"
// MCPU-SIFIVE-S54: "-target-abi" "lp64d"
// mcpu with mabi option
@@ -119,7 +113,6 @@
// MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
// MCPU-SIFIVE-S76: "-target-feature" "+c"
// MCPU-SIFIVE-S76: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-SIFIVE-S76: "-target-feature" "+64bit"
// MCPU-SIFIVE-S76: "-target-abi" "lp64d"
// mcpu with default march
@@ -128,7 +121,6 @@
// MCPU-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
// MCPU-SIFIVE-U54: "-target-feature" "+c"
// MCPU-SIFIVE-U54: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-SIFIVE-U54: "-target-feature" "+64bit"
// MCPU-SIFIVE-U54: "-target-abi" "lp64d"
// mcpu with mabi option
@@ -137,7 +129,6 @@
// MCPU-ABI-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
// MCPU-ABI-SIFIVE-U54: "-target-feature" "+c"
// MCPU-ABI-SIFIVE-U54: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-ABI-SIFIVE-U54: "-target-feature" "+64bit"
// MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64"
// mcpu with default march
@@ -154,7 +145,6 @@
// MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c"
// MCPU-ABI-SIFIVE-U74: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-ABI-SIFIVE-U74: "-target-feature" "+64bit"
// MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64"
// march overwrite mcpu's default march
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index fe40eb3737b5..6f6c89e80e4e 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -39,7 +39,6 @@ CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64);
StringRef getMArchFromMcpu(StringRef CPU);
void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
-bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector<StringRef> &Features);
bool isX18ReservedByDefault(const Triple &TT);
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 379855a42020..e3543b90e4d2 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -85,22 +85,6 @@ void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
}
-// Get all features except standard extension feature
-bool getCPUFeaturesExceptStdExt(CPUKind Kind,
- std::vector<StringRef> &Features) {
- const CPUInfo &Info = RISCVCPUInfo[static_cast<unsigned>(Kind)];
-
- if (Info.isInvalid())
- return false;
-
- if (Info.is64Bit())
- Features.push_back("+64bit");
- else
- Features.push_back("-64bit");
-
- return true;
-}
-
bool isX18ReservedByDefault(const Triple &TT) {
// X18 is reserved for the ShadowCallStack ABI (even when not enabled).
return TT.isOSFuchsia() || TT.isAndroid();
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