[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

[Paul Kirth via Phabricator via cfe-commits]

paulkirth added a comment.

whe



================
Comment at: clang/lib/Driver/SanitizerArgs.cpp:546
 
-  if ((Kinds & SanitizerKind::ShadowCallStack) &&
-      ((TC.getTriple().isAArch64() &&
-        !llvm::AArch64::isX18ReservedByDefault(TC.getTriple())) ||
-       (TC.getTriple().isRISCV() &&
-        !llvm::RISCV::isX18ReservedByDefault(TC.getTriple()))) &&
+  if ((Kinds & SanitizerKind::ShadowCallStack) && TC.getTriple().isAArch64() &&
+      !llvm::AArch64::isX18ReservedByDefault(TC.getTriple()) &&
----------------
mcgrathr wrote:
> For RISC-V this needs a similar check that the equivalent of `-msmall-data-limit=0` is in force (that's the default under `-fPIC` but not other modes).
> 
I'll look into adding support for that.


================
Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:86
       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
-  if (RISCV::isX18ReservedByDefault(TT))
-    UserReservedRegister.set(RISCV::X18);
----------------
craig.topper wrote:
> Drop the blank line here.
@mcgrathr This stops Fuchsia and Android from reserving X18. I'll look at doing something similar for `-msmall-data-limit=0`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146463/new/

https://reviews.llvm.org/D146463