[PATCH] D147328: [clang-format] Handle enum in Verilog

[Owen Pan via Phabricator via cfe-commits]

owenpan accepted this revision.
owenpan added inline comments.


================
Comment at: clang/lib/Format/UnwrappedLineParser.cpp:1712
         break;
-      // This only applies for C++.
-      if (!Style.isCpp()) {
+      // This only applies for C++ and Verilog.
+      if (!Style.isCpp() && !Style.isVerilog()) {
----------------



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147328/new/

https://reviews.llvm.org/D147328