[PATCH] D147261: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

[Craig Topper via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG96a7e057567d: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td. (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147261/new/

https://reviews.llvm.org/D147261

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/lib/Target/RISCV/RISCVProcessors.td

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D147261.509848.patch
Type: text/x-patch
Size: 14396 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/cfe-commits/attachments/20230330/51b57a8e/attachment-0001.bin>