[PATCH] D147261: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

[Craig Topper via Phabricator via cfe-commits]

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I only added Zicsr to CPUs that didn't already have an implication
through the F extension.

As far as I could tell from searching Rocket and Syntacore repositories,
all the CPUs support these instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147261

Files:
  clang/test/Driver/riscv-cpus.c
  llvm/lib/Target/RISCV/RISCVProcessors.td

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