[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

[Craig Topper via Phabricator via cfe-commits]

craig.topper updated this revision to Diff 509481.
craig.topper added a comment.

Zve32x needs to imply Zicsr too


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147179/new/

https://reviews.llvm.org/D147179

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  lld/test/ELF/lto/riscv-attributes.ll
  lld/test/ELF/riscv-attributes.s
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/attribute-with-insts.s
  llvm/test/MC/RISCV/attribute-with-option.s
  llvm/test/MC/RISCV/attribute.s
  llvm/test/MC/RISCV/invalid-attribute.s
  llvm/test/tools/llvm-readobj/ELF/RISCV/attribute.s
  llvm/unittests/Support/RISCVISAInfoTest.cpp

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