[clang] 0f4c9c0 - [RISCV] Replace RISCV->RISC-V in strings.
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Mon Mar 27 09:51:18 PDT 2023
Author: Craig Topper
Date: 2023-03-27T09:50:17-07:00
New Revision: 0f4c9c016caf52dc45934e0cbf82b1daabcf1d96
URL: https://github.com/llvm/llvm-project/commit/0f4c9c016caf52dc45934e0cbf82b1daabcf1d96
DIFF: https://github.com/llvm/llvm-project/commit/0f4c9c016caf52dc45934e0cbf82b1daabcf1d96.diff
LOG: [RISCV] Replace RISCV->RISC-V in strings.
To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.
D146449 already updated comments. Strings may have more user impact.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D146451
Added:
Modified:
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Driver/Options.td
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/O0-pipeline.ll
llvm/test/CodeGen/RISCV/O3-pipeline.ll
llvm/utils/TableGen/CompressInstEmitter.cpp
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td
index 1bb9e691725d3..02f0b6e622771 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -2293,7 +2293,7 @@ as ``-mlong-calls`` and ``-mno-long-calls``.
def RISCVInterruptDocs : Documentation {
let Category = DocCatFunction;
- let Heading = "interrupt (RISCV)";
+ let Heading = "interrupt (RISC-V)";
let Content = [{
Clang supports the GNU style ``__attribute__((interrupt))`` attribute on RISCV
targets. This attribute may be attached to a function definition and instructs
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 5d2089e6b3edc..c01859bc18a9a 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -185,7 +185,7 @@ def m_wasm_Features_Driver_Group : OptionGroup<"<wasm driver features group>">,
def m_x86_Features_Group : OptionGroup<"<x86 features group>">,
Group<m_Group>, Flags<[CoreOption]>, DocName<"X86">;
def m_riscv_Features_Group : OptionGroup<"<riscv features group>">,
- Group<m_Group>, DocName<"RISCV">;
+ Group<m_Group>, DocName<"RISC-V">;
def m_libc_Group : OptionGroup<"<m libc group>">, Group<m_mips_Features_Group>,
Flags<[HelpHidden]>;
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 7789ef7da0540..659f8e84f215e 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -53,7 +53,7 @@ class RISCVAsmPrinter : public AsmPrinter {
std::unique_ptr<MCStreamer> Streamer)
: AsmPrinter(TM, std::move(Streamer)) {}
- StringRef getPassName() const override { return "RISCV Assembly Printer"; }
+ StringRef getPassName() const override { return "RISC-V Assembly Printer"; }
bool runOnMachineFunction(MachineFunction &MF) override;
diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
index c972859f2f566..2fcd9a40588a7 100644
--- a/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
@@ -26,7 +26,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-codegenprepare"
-#define PASS_NAME "RISCV CodeGenPrepare"
+#define PASS_NAME "RISC-V CodeGenPrepare"
STATISTIC(NumZExtToSExt, "Number of SExt instructions converted to ZExt");
diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
index 6a9b959fe4cda..9cca52617ab51 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
@@ -24,7 +24,7 @@
using namespace llvm;
#define RISCV_EXPAND_ATOMIC_PSEUDO_NAME \
- "RISCV atomic pseudo instruction expansion pass"
+ "RISC-V atomic pseudo instruction expansion pass"
namespace {
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index b8e4665bea918..d86ba822f0308 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -23,8 +23,8 @@
using namespace llvm;
-#define RISCV_EXPAND_PSEUDO_NAME "RISCV pseudo instruction expansion pass"
-#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISCV Pre-RA pseudo instruction expansion pass"
+#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
+#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
namespace {
diff --git a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
index 995647b7c6a20..8a440ed29ac35 100644
--- a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
@@ -59,7 +59,7 @@ class RISCVGatherScatterLowering : public FunctionPass {
}
StringRef getPassName() const override {
- return "RISCV gather/scatter lowering";
+ return "RISC-V gather/scatter lowering";
}
private:
@@ -81,7 +81,7 @@ class RISCVGatherScatterLowering : public FunctionPass {
char RISCVGatherScatterLowering::ID = 0;
INITIALIZE_PASS(RISCVGatherScatterLowering, DEBUG_TYPE,
- "RISCV gather/scatter lowering pass", false, false)
+ "RISC-V gather/scatter lowering pass", false, false)
FunctionPass *llvm::createRISCVGatherScatterLoweringPass() {
return new RISCVGatherScatterLowering();
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index e44cf385dad30..99f664b6bc56a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -26,7 +26,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-isel"
-#define PASS_NAME "RISCV DAG->DAG Pattern Instruction Selection"
+#define PASS_NAME "RISC-V DAG->DAG Pattern Instruction Selection"
namespace llvm::RISCV {
#define GET_RISCVVSSEGTable_IMPL
@@ -134,7 +134,7 @@ void RISCVDAGToDAGISel::PreprocessISelDAG() {
}
if (Result) {
- LLVM_DEBUG(dbgs() << "RISCV DAG preprocessing replacing:\nOld: ");
+ LLVM_DEBUG(dbgs() << "RISC-V DAG preprocessing replacing:\nOld: ");
LLVM_DEBUG(N->dump(CurDAG));
LLVM_DEBUG(dbgs() << "\nNew: ");
LLVM_DEBUG(Result->dump(CurDAG));
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 3fa9fd663845d..b66ecc8084097 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -32,7 +32,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-insert-vsetvli"
-#define RISCV_INSERT_VSETVLI_NAME "RISCV Insert VSETVLI pass"
+#define RISCV_INSERT_VSETVLI_NAME "RISC-V Insert VSETVLI pass"
static cl::opt<bool> DisableInsertVSETVLPHIOpt(
"riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index faf47ed8592d6..77f63ee29b7de 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -951,7 +951,7 @@ unsigned RISCVInstrInfo::insertBranch(
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 3 || Cond.size() == 0) &&
- "RISCV branch conditions have two components!");
+ "RISC-V branch conditions have two components!");
// Unconditional branch.
if (Cond.empty()) {
diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
index 39d0a201c666b..e6ae40970d511 100644
--- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -75,7 +75,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-make-compressible"
-#define RISCV_COMPRESS_INSTRS_NAME "RISCV Make Compressible"
+#define RISCV_COMPRESS_INSTRS_NAME "RISC-V Make Compressible"
namespace {
diff --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
index 55ded2c2c6628..a2b3065fdefbe 100644
--- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
@@ -23,7 +23,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-merge-base-offset"
-#define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset"
+#define RISCV_MERGE_BASE_OFFSET_NAME "RISC-V Merge Base Offset"
namespace {
class RISCVMergeBaseOffsetOpt : public MachineFunctionPass {
diff --git a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
index a1de27f0f9916..fed3fa2987e52 100644
--- a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
@@ -39,7 +39,7 @@
using namespace llvm;
#define DEBUG_TYPE "riscv-init-undef"
-#define RISCV_INIT_UNDEF_NAME "RISCV init undef pass"
+#define RISCV_INIT_UNDEF_NAME "RISC-V init undef pass"
namespace {
diff --git a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
index 92fba63a080bb..61d605fda3f53 100644
--- a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
@@ -56,7 +56,7 @@ class RISCVRedundantCopyElimination : public MachineFunctionPass {
}
StringRef getPassName() const override {
- return "RISCV Redundant Copy Elimination";
+ return "RISC-V Redundant Copy Elimination";
}
private:
@@ -68,7 +68,7 @@ class RISCVRedundantCopyElimination : public MachineFunctionPass {
char RISCVRedundantCopyElimination::ID = 0;
INITIALIZE_PASS(RISCVRedundantCopyElimination, "riscv-copyelim",
- "RISCV redundant copy elimination pass", false, false)
+ "RISC-V Redundant Copy Elimination", false, false)
static bool
guaranteesZeroRegInBlock(MachineBasicBlock &MBB,
diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index a26a3f2411f8a..173482e7aea87 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -47,13 +47,13 @@ class RISCVSExtWRemoval : public MachineFunctionPass {
MachineFunctionPass::getAnalysisUsage(AU);
}
- StringRef getPassName() const override { return "RISCV sext.w Removal"; }
+ StringRef getPassName() const override { return "RISC-V sext.w Removal"; }
};
} // end anonymous namespace
char RISCVSExtWRemoval::ID = 0;
-INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISCV sext.w Removal", false,
+INITIALIZE_PASS(RISCVSExtWRemoval, DEBUG_TYPE, "RISC-V sext.w Removal", false,
false)
FunctionPass *llvm::createRISCVSExtWRemovalPass() {
diff --git a/llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp b/llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp
index 8324f16497413..edf41b7ed07e9 100644
--- a/llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp
+++ b/llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp
@@ -40,14 +40,14 @@ class RISCVStripWSuffix : public MachineFunctionPass {
MachineFunctionPass::getAnalysisUsage(AU);
}
- StringRef getPassName() const override { return "RISCV Strip W Suffix"; }
+ StringRef getPassName() const override { return "RISC-V Strip W Suffix"; }
};
} // end anonymous namespace
char RISCVStripWSuffix::ID = 0;
INITIALIZE_PASS(RISCVStripWSuffix, "riscv-strip-w-suffix",
- "RISCV Strip W Suffix", false, false)
+ "RISC-V Strip W Suffix", false, false)
FunctionPass *llvm::createRISCVStripWSuffixPass() {
return new RISCVStripWSuffix();
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 4b676f297623f..19b6b3612441d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -68,7 +68,7 @@ static cl::opt<int> RVVVectorBitsMinOpt(
static cl::opt<bool> EnableRISCVCopyPropagation(
"riscv-enable-copy-propagation",
- cl::desc("Enable the copy propagation with RISCV copy instr"),
+ cl::desc("Enable the copy propagation with RISC-V copy instr"),
cl::init(true), cl::Hidden);
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
index c87a0e3ae244c..f18e6a34ecdd1 100644
--- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
@@ -36,11 +36,11 @@
; CHECK-NEXT: Insert stack protectors
; CHECK-NEXT: Module Verifier
; CHECK-NEXT: Assignment Tracking Analysis
-; CHECK-NEXT: RISCV DAG->DAG Pattern Instruction Selection
+; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Local Stack Slot Allocation
-; CHECK-NEXT: RISCV Pre-RA pseudo instruction expansion pass
-; CHECK-NEXT: RISCV Insert VSETVLI pass
+; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V Insert VSETVLI pass
; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Fast Register Allocator
@@ -55,7 +55,7 @@
; CHECK-NEXT: Insert XRay ops
; CHECK-NEXT: Implement the 'patchable-function' attribute
; CHECK-NEXT: Branch relaxation pass
-; CHECK-NEXT: RISCV Make Compressible
+; CHECK-NEXT: RISC-V Make Compressible
; CHECK-NEXT: Contiguously Lay Out Funclets
; CHECK-NEXT: StackMap Liveness Analysis
; CHECK-NEXT: Live DEBUG_VALUE analysis
@@ -63,9 +63,9 @@
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Stack Frame Layout Analysis
-; CHECK-NEXT: RISCV pseudo instruction expansion pass
-; CHECK-NEXT: RISCV atomic pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
-; CHECK-NEXT: RISCV Assembly Printer
+; CHECK-NEXT: RISC-V Assembly Printer
; CHECK-NEXT: Free MachineFunction
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index 0ad08074c104e..a010df10adb3c 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -28,8 +28,8 @@
; CHECK-NEXT: Expand Atomic instructions
; CHECK-NEXT: Dominator Tree Construction
; CHECK-NEXT: Natural Loop Information
-; CHECK-NEXT: RISCV gather/scatter lowering
-; CHECK-NEXT: RISCV CodeGenPrepare
+; CHECK-NEXT: RISC-V gather/scatter lowering
+; CHECK-NEXT: RISC-V CodeGenPrepare
; CHECK-NEXT: Module Verifier
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Canonicalize natural loops
@@ -79,7 +79,7 @@
; CHECK-NEXT: Assignment Tracking Analysis
; CHECK-NEXT: Lazy Branch Probability Analysis
; CHECK-NEXT: Lazy Block Frequency Analysis
-; CHECK-NEXT: RISCV DAG->DAG Pattern Instruction Selection
+; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Early Tail Duplication
@@ -103,13 +103,13 @@
; CHECK-NEXT: Machine Trace Metrics
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine InstCombiner
-; RV64-NEXT: RISCV sext.w Removal
-; RV64-NEXT: RISCV Strip W Suffix
-; CHECK-NEXT: RISCV Pre-RA pseudo instruction expansion pass
-; CHECK-NEXT: RISCV Merge Base Offset
-; CHECK-NEXT: RISCV Insert VSETVLI pass
+; RV64-NEXT: RISC-V sext.w Removal
+; RV64-NEXT: RISC-V Strip W Suffix
+; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V Merge Base Offset
+; CHECK-NEXT: RISC-V Insert VSETVLI pass
; CHECK-NEXT: Detect Dead Lanes
-; CHECK-NEXT: RISCV init undef pass
+; CHECK-NEXT: RISC-V init undef pass
; CHECK-NEXT: Process Implicit Definitions
; CHECK-NEXT: Remove unreachable machine basic blocks
; CHECK-NEXT: Live Variable Analysis
@@ -136,7 +136,7 @@
; CHECK-NEXT: Stack Slot Coloring
; CHECK-NEXT: Machine Copy Propagation Pass
; CHECK-NEXT: Machine Loop Invariant Code Motion
-; CHECK-NEXT: RISCV Redundant Copy Elimination
+; CHECK-NEXT: RISC-V Redundant Copy Elimination
; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
; CHECK-NEXT: Fixup Statepoint Caller Saved
; CHECK-NEXT: PostRA Machine Sink
@@ -165,7 +165,7 @@
; CHECK-NEXT: Insert XRay ops
; CHECK-NEXT: Implement the 'patchable-function' attribute
; CHECK-NEXT: Branch relaxation pass
-; CHECK-NEXT: RISCV Make Compressible
+; CHECK-NEXT: RISC-V Make Compressible
; CHECK-NEXT: Machine Copy Propagation Pass
; CHECK-NEXT: Contiguously Lay Out Funclets
; CHECK-NEXT: StackMap Liveness Analysis
@@ -176,9 +176,9 @@
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Stack Frame Layout Analysis
-; CHECK-NEXT: RISCV pseudo instruction expansion pass
-; CHECK-NEXT: RISCV atomic pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
-; CHECK-NEXT: RISCV Assembly Printer
+; CHECK-NEXT: RISC-V Assembly Printer
; CHECK-NEXT: Free MachineFunction
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index a7816c24f8717..9d9b69f4cfbda 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -904,4 +904,4 @@ void CompressInstEmitter::run(raw_ostream &o) {
}
static TableGen::Emitter::OptClass<CompressInstEmitter>
- X("gen-compress-inst-emitter", "Generate RISCV compressed instructions.");
+ X("gen-compress-inst-emitter", "Generate compressed instructions.");
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