[clang] f90668c - [clang-format] Handle Verilog assign statements
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Sat Mar 25 14:18:40 PDT 2023
Author: sstwcw
Date: 2023-03-25T21:13:15Z
New Revision: f90668c8ccc5cd3d8c6521cfc872f3c51f2a02db
URL: https://github.com/llvm/llvm-project/commit/f90668c8ccc5cd3d8c6521cfc872f3c51f2a02db
DIFF: https://github.com/llvm/llvm-project/commit/f90668c8ccc5cd3d8c6521cfc872f3c51f2a02db.diff
LOG: [clang-format] Handle Verilog assign statements
Reviewed By: MyDeveloperDay
Differential Revision: https://reviews.llvm.org/D146402
Added:
Modified:
clang/lib/Format/FormatToken.h
clang/lib/Format/TokenAnnotator.cpp
clang/unittests/Format/FormatTestVerilog.cpp
Removed:
################################################################################
diff --git a/clang/lib/Format/FormatToken.h b/clang/lib/Format/FormatToken.h
index 5cac5776a652..5cd3422aed5b 100644
--- a/clang/lib/Format/FormatToken.h
+++ b/clang/lib/Format/FormatToken.h
@@ -144,6 +144,8 @@ namespace format {
TYPE(UnaryOperator) \
TYPE(UnionLBrace) \
TYPE(UntouchableMacroFunc) \
+ /* Like in 'assign x = 0, y = 1;' . */ \
+ TYPE(VerilogAssignComma) \
/* like in begin : block */ \
TYPE(VerilogBlockLabelColon) \
/* The square bracket for the dimension part of the type name. \
diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp
index a9f3bd0bb06b..d7758e7d068d 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -1286,8 +1286,11 @@ class AnnotatingParser {
Tok->setType(TT_InheritanceComma);
break;
default:
- if (Contexts.back().FirstStartOfName &&
- (Contexts.size() == 1 || startsWithInitStatement(Line))) {
+ if (Style.isVerilog() && Contexts.size() == 1 &&
+ Line.startsWith(Keywords.kw_assign)) {
+ Tok->setFinalizedType(TT_VerilogAssignComma);
+ } else if (Contexts.back().FirstStartOfName &&
+ (Contexts.size() == 1 || startsWithInitStatement(Line))) {
Contexts.back().FirstStartOfName->PartOfMultiVariableDeclStmt = true;
Line.IsMultiVariableDeclStmt = true;
}
@@ -4720,6 +4723,9 @@ bool TokenAnnotator::mustBreakBefore(const AnnotatedLine &Line,
return true;
}
} else if (Style.isVerilog()) {
+ // Break between assignments.
+ if (Left.is(TT_VerilogAssignComma))
+ return true;
// Break between ports of
diff erent types.
if (Left.is(TT_VerilogTypeComma))
return true;
diff --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp
index 6192deb3267d..3a03525c2db7 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -97,6 +97,23 @@ TEST_F(FormatTestVerilog, Align) {
Style);
}
+TEST_F(FormatTestVerilog, Assign) {
+ verifyFormat("assign mynet = enable;");
+ verifyFormat("assign (strong1, pull0) #1 mynet = enable;");
+ verifyFormat("assign #1 mynet = enable;");
+ verifyFormat("assign mynet = enable;");
+ // Test that assignments are on separate lines.
+ verifyFormat("assign mynet = enable,\n"
+ " mynet1 = enable1;");
+ // Test that `<=` and `,` don't confuse it.
+ verifyFormat("assign mynet = enable1 <= enable2;");
+ verifyFormat("assign mynet = enable1 <= enable2,\n"
+ " mynet1 = enable3;");
+ verifyFormat("assign mynet = enable,\n"
+ " mynet1 = enable2 <= enable3;");
+ verifyFormat("assign mynet = enable(enable1, enable2);");
+}
+
TEST_F(FormatTestVerilog, BasedLiteral) {
verifyFormat("x = '0;");
verifyFormat("x = '1;");
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