[clang] 65a0d66 - Fix accessing of aligned arrays in offloaded target regions
Doru Bercea via cfe-commits
cfe-commits at lists.llvm.org
Wed Mar 22 08:12:18 PDT 2023
Author: Doru Bercea
Date: 2023-03-22T11:11:23-04:00
New Revision: 65a0d669b4625c34775436a6d3643d15bbc2465a
URL: https://github.com/llvm/llvm-project/commit/65a0d669b4625c34775436a6d3643d15bbc2465a
DIFF: https://github.com/llvm/llvm-project/commit/65a0d669b4625c34775436a6d3643d15bbc2465a.diff
LOG: Fix accessing of aligned arrays in offloaded target regions
Added:
clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c
Modified:
clang/lib/Sema/SemaOpenMP.cpp
clang/test/OpenMP/parallel_firstprivate_codegen.cpp
clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp
clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp
clang/test/OpenMP/target_firstprivate_codegen.cpp
clang/test/OpenMP/target_is_device_ptr_codegen.cpp
clang/test/OpenMP/teams_firstprivate_codegen.cpp
Removed:
################################################################################
diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp
index e193fa3d19d5c..1cd263b8a5b1c 100644
--- a/clang/lib/Sema/SemaOpenMP.cpp
+++ b/clang/lib/Sema/SemaOpenMP.cpp
@@ -2273,10 +2273,10 @@ bool Sema::isOpenMPCapturedByRef(const ValueDecl *D, unsigned Level,
// and alignment, because the runtime library only deals with uintptr types.
// If it does not fit the uintptr size, we need to pass the data by reference
// instead.
- if (!IsByRef &&
- (Ctx.getTypeSizeInChars(Ty) >
- Ctx.getTypeSizeInChars(Ctx.getUIntPtrType()) ||
- Ctx.getDeclAlign(D) > Ctx.getTypeAlignInChars(Ctx.getUIntPtrType()))) {
+ if (!IsByRef && (Ctx.getTypeSizeInChars(Ty) >
+ Ctx.getTypeSizeInChars(Ctx.getUIntPtrType()) ||
+ Ctx.getAlignOfGlobalVarInChars(Ty) >
+ Ctx.getTypeAlignInChars(Ctx.getUIntPtrType()))) {
IsByRef = true;
}
diff --git a/clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c b/clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c
new file mode 100644
index 0000000000000..e33ad0b353f51
--- /dev/null
+++ b/clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c
@@ -0,0 +1,305 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
+// REQUIRES: amdgpu-registered-target
+
+// expected-no-diagnostics
+#ifndef HEADER
+#define HEADER
+
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple powerpc64le-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host-amd.bc
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host-amd.bc -o - | FileCheck %s --check-prefix=CHECK-AMD
+
+
+void write_to_aligned_array(int *a, int N) {
+ int *aptr __attribute__ ((aligned(64))) = a;
+ #pragma omp target teams distribute parallel for map(tofrom: aptr[0:N])
+ for(int i = 0; i < N; i++) {
+ aptr[i] = i;
+ }
+}
+
+#endif
+// CHECK-AMD-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14
+// CHECK-AMD-SAME: (i64 noundef [[N:%.*]], ptr noundef [[APTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-AMD-NEXT: entry:
+// CHECK-AMD-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[APTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr
+// CHECK-AMD-NEXT: [[APTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[APTR_ADDR]] to ptr
+// CHECK-AMD-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr
+// CHECK-AMD-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr
+// CHECK-AMD-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
+// CHECK-AMD-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: store ptr [[APTR]], ptr [[APTR_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr), i8 2, i1 false)
+// CHECK-AMD-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-AMD-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-AMD: user_code.entry:
+// CHECK-AMD-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr))
+// CHECK-AMD-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[TMP2]], ptr [[N_CASTED_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP3:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP4:%.*]] = load ptr, ptr [[APTR_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4
+// CHECK-AMD-NEXT: call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP3]], ptr [[TMP4]]) #[[ATTR2:[0-9]+]]
+// CHECK-AMD-NEXT: call void @__kmpc_target_deinit(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i8 2)
+// CHECK-AMD-NEXT: ret void
+// CHECK-AMD: worker.exit:
+// CHECK-AMD-NEXT: ret void
+//
+//
+// CHECK-AMD-LABEL: define {{[^@]+}}@__omp_outlined__
+// CHECK-AMD-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef [[APTR:%.*]]) #[[ATTR1:[0-9]+]] {
+// CHECK-AMD-NEXT: entry:
+// CHECK-AMD-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[APTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[I3:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr
+// CHECK-AMD-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr
+// CHECK-AMD-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr
+// CHECK-AMD-NEXT: [[APTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[APTR_ADDR]] to ptr
+// CHECK-AMD-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr
+// CHECK-AMD-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr
+// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr
+// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_1]] to ptr
+// CHECK-AMD-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
+// CHECK-AMD-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr
+// CHECK-AMD-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr
+// CHECK-AMD-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr
+// CHECK-AMD-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr
+// CHECK-AMD-NEXT: [[I3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I3]] to ptr
+// CHECK-AMD-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr
+// CHECK-AMD-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr
+// CHECK-AMD-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: store ptr [[APTR]], ptr [[APTR_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
+// CHECK-AMD-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK-AMD-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK-AMD-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK-AMD-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 0, ptr [[I_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
+// CHECK-AMD-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]]
+// CHECK-AMD-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK-AMD: omp.precond.then:
+// CHECK-AMD-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-AMD-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK-AMD-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-AMD-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]]
+// CHECK-AMD-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK-AMD: cond.true:
+// CHECK-AMD-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
+// CHECK-AMD-NEXT: br label [[COND_END:%.*]]
+// CHECK-AMD: cond.false:
+// CHECK-AMD-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: br label [[COND_END]]
+// CHECK-AMD: cond.end:
+// CHECK-AMD-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
+// CHECK-AMD-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK-AMD: omp.inner.for.cond:
+// CHECK-AMD-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 1
+// CHECK-AMD-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[ADD]]
+// CHECK-AMD-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-AMD: omp.inner.for.body:
+// CHECK-AMD-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
+// CHECK-AMD-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
+// CHECK-AMD-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[TMP17]], ptr [[N_CASTED_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP18:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP19:%.*]] = load ptr, ptr [[APTR_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0
+// CHECK-AMD-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP14]] to ptr
+// CHECK-AMD-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8
+// CHECK-AMD-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
+// CHECK-AMD-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP16]] to ptr
+// CHECK-AMD-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8
+// CHECK-AMD-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2
+// CHECK-AMD-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP18]] to ptr
+// CHECK-AMD-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8
+// CHECK-AMD-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3
+// CHECK-AMD-NEXT: store ptr [[TMP19]], ptr [[TMP26]], align 8
+// CHECK-AMD-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
+// CHECK-AMD-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__.1, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 4)
+// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK-AMD: omp.inner.for.inc:
+// CHECK-AMD-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
+// CHECK-AMD-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
+// CHECK-AMD-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
+// CHECK-AMD-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
+// CHECK-AMD-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
+// CHECK-AMD: cond.true10:
+// CHECK-AMD-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
+// CHECK-AMD-NEXT: br label [[COND_END12:%.*]]
+// CHECK-AMD: cond.false11:
+// CHECK-AMD-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: br label [[COND_END12]]
+// CHECK-AMD: cond.end12:
+// CHECK-AMD-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
+// CHECK-AMD-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-AMD: omp.inner.for.end:
+// CHECK-AMD-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-AMD: omp.loop.exit:
+// CHECK-AMD-NEXT: [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
+// CHECK-AMD-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP41]])
+// CHECK-AMD-NEXT: br label [[OMP_PRECOND_END]]
+// CHECK-AMD: omp.precond.end:
+// CHECK-AMD-NEXT: ret void
+//
+//
+// CHECK-AMD-LABEL: define {{[^@]+}}@__omp_outlined__.1
+// CHECK-AMD-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef [[APTR:%.*]]) #[[ATTR1]] {
+// CHECK-AMD-NEXT: entry:
+// CHECK-AMD-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[APTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[I4:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-AMD-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr
+// CHECK-AMD-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr
+// CHECK-AMD-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr
+// CHECK-AMD-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr
+// CHECK-AMD-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr
+// CHECK-AMD-NEXT: [[APTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[APTR_ADDR]] to ptr
+// CHECK-AMD-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr
+// CHECK-AMD-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr
+// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr
+// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_1]] to ptr
+// CHECK-AMD-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
+// CHECK-AMD-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr
+// CHECK-AMD-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr
+// CHECK-AMD-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr
+// CHECK-AMD-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr
+// CHECK-AMD-NEXT: [[I4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I4]] to ptr
+// CHECK-AMD-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: store ptr [[APTR]], ptr [[APTR_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
+// CHECK-AMD-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
+// CHECK-AMD-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
+// CHECK-AMD-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
+// CHECK-AMD-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 0, ptr [[I_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
+// CHECK-AMD-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]]
+// CHECK-AMD-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
+// CHECK-AMD: omp.precond.then:
+// CHECK-AMD-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32
+// CHECK-AMD-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32
+// CHECK-AMD-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-AMD-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP7]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
+// CHECK-AMD-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// CHECK-AMD: omp.inner.for.cond:
+// CHECK-AMD-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[CONV5:%.*]] = sext i32 [[TMP9]] to i64
+// CHECK-AMD-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP10]]
+// CHECK-AMD-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-AMD: omp.inner.for.body:
+// CHECK-AMD-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
+// CHECK-AMD-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-AMD-NEXT: store i32 [[ADD]], ptr [[I4_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP12:%.*]] = load i32, ptr [[I4_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP13:%.*]] = load ptr, ptr [[APTR_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP14:%.*]] = load i32, ptr [[I4_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
+// CHECK-AMD-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[IDXPROM]]
+// CHECK-AMD-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4
+// CHECK-AMD-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-AMD: omp.body.continue:
+// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK-AMD: omp.inner.for.inc:
+// CHECK-AMD-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
+// CHECK-AMD-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-AMD: omp.inner.for.end:
+// CHECK-AMD-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-AMD: omp.loop.exit:
+// CHECK-AMD-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
+// CHECK-AMD-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP18]])
+// CHECK-AMD-NEXT: br label [[OMP_PRECOND_END]]
+// CHECK-AMD: omp.precond.end:
+// CHECK-AMD-NEXT: ret void
+//
diff --git a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp
index 2c70e05feafd0..845888dd32d19 100644
--- a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp
@@ -467,6 +467,8 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128
// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128
// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128
+// CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4
// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])
// CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[SST]])
// CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 128
@@ -476,23 +478,29 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
// CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3)
-// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @.omp_outlined..3, ptr [[VEC]], ptr [[T_VAR]], ptr [[S_ARR]], ptr [[VAR]])
-// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..4, ptr [[T_VAR]])
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
+// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @.omp_outlined..3, ptr [[VEC]], i32 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]])
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR]], align 128
+// CHECK1-NEXT: store i32 [[TMP2]], ptr [[T_VAR_CASTED1]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4
+// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..4, i32 [[TMP3]])
// CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
+// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1: arraydestroy.body:
-// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
-// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
-// CHECK1: arraydestroy.done1:
+// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK1: arraydestroy.done2:
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
-// CHECK1-NEXT: ret i32 [[TMP1]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK1-NEXT: ret i32 [[TMP5]]
//
//
// CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
@@ -713,67 +721,63 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
-// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
+// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
-// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4
+// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
// CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
-// CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
-// CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128
-// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128
+// CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128
+// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128
// CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
-// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
-// CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
+// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
+// CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
-// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
// CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
// CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
-// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 128
-// CHECK1-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 128
-// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC2]], ptr align 128 [[TMP0]], i32 8, i1 false)
-// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
-// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
-// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
+// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i32 8, i1 false)
+// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
+// CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
+// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK1: omp.arraycpy.body:
-// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])
// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])
// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
// CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
-// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
-// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
-// CHECK1: omp.arraycpy.done4:
-// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
-// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR5]], ptr nonnull align 4 dereferenceable(4) [[TMP3]], ptr [[AGG_TMP6]])
-// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR1]], align 128
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 0
-// CHECK1-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 128
-// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
-// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX7]], ptr align 128 [[VAR5]], i32 4, i1 false)
-// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
-// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
-// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i32 2
+// CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
+// CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK1: omp.arraycpy.done3:
+// CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
+// CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])
+// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0
+// CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128
+// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
+// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i32 4, i1 false)
+// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]
+// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i32 2
// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK1: arraydestroy.body:
-// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
-// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
-// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
-// CHECK1: arraydestroy.done9:
+// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
+// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK1: arraydestroy.done8:
// CHECK1-NEXT: ret void
//
//
@@ -803,18 +807,14 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
-// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] {
+// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4
-// CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
+// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR1]], align 128
+// CHECK1-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
// CHECK1-NEXT: ret void
//
//
@@ -1123,27 +1123,23 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
-// CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] {
+// CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] {
// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
+// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128
// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 4
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[G]], ptr [[G_ADDR]], align 4
// CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
-// CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr [[TMP0]], align 128
-// CHECK3-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128
-// CHECK3-NEXT: store i32 1, ptr [[G1]], align 128
+// CHECK3-NEXT: store i32 1, ptr [[G_ADDR]], align 4
// CHECK3-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0
-// CHECK3-NEXT: store ptr [[G1]], ptr [[TMP2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1
-// CHECK3-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP3]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0
+// CHECK3-NEXT: store ptr [[G_ADDR]], ptr [[TMP0]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1
+// CHECK3-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP1]], align 4
// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr nonnull align 4 dereferenceable(8) [[REF_TMP]])
// CHECK3-NEXT: ret void
//
@@ -1193,33 +1189,33 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 4
// CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 4
+// CHECK4-NEXT: [[G_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4
// CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 4
-// CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
-// CHECK4-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4
-// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
-// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.omp_outlined., ptr @g, i32 [[TMP1]])
+// CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128
+// CHECK4-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4
+// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[G_CASTED]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
+// CHECK4-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
+// CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
+// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.omp_outlined., i32 [[TMP1]], i32 [[TMP3]])
// CHECK4-NEXT: ret void
//
//
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
-// CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK4-NEXT: entry:
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK4-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
+// CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32, align 4
// CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
-// CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 128
// CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, align 128
// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK4-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
+// CHECK4-NEXT: store i32 [[G]], ptr [[G_ADDR]], align 4
// CHECK4-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
-// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
-// CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, ptr [[TMP0]], align 128
-// CHECK4-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128
-// CHECK4-NEXT: store i32 1, ptr [[G1]], align 128
+// CHECK4-NEXT: store i32 1, ptr [[G_ADDR]], align 4
// CHECK4-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4
// CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 0
// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 128
@@ -1232,14 +1228,14 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 4
// CHECK4-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 16
// CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 7
-// CHECK4-NEXT: [[TMP2:%.*]] = load volatile i32, ptr [[G1]], align 128
-// CHECK4-NEXT: store volatile i32 [[TMP2]], ptr [[BLOCK_CAPTURED]], align 128
-// CHECK4-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 5
-// CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
-// CHECK4-NEXT: store i32 [[TMP3]], ptr [[BLOCK_CAPTURED2]], align 4
-// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
-// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
-// CHECK4-NEXT: call void [[TMP5]](ptr [[BLOCK]])
+// CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr [[G_ADDR]], align 4
+// CHECK4-NEXT: store volatile i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 128
+// CHECK4-NEXT: [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [104 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 5
+// CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
+// CHECK4-NEXT: store i32 [[TMP1]], ptr [[BLOCK_CAPTURED1]], align 4
+// CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
+// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CHECK4-NEXT: call void [[TMP3]](ptr [[BLOCK]])
// CHECK4-NEXT: ret void
//
//
@@ -1675,6 +1671,8 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128
// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128
// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128
+// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
+// CHECK9-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i64, align 8
// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])
// CHECK9-NEXT: call void @_ZN3SSTIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[SST]])
// CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 128
@@ -1684,23 +1682,29 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3)
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @.omp_outlined..3, ptr [[VEC]], ptr [[T_VAR]], ptr [[S_ARR]], ptr [[VAR]])
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..4, ptr [[T_VAR]])
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128
+// CHECK9-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
+// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @.omp_outlined..3, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]])
+// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR]], align 128
+// CHECK9-NEXT: store i32 [[TMP2]], ptr [[T_VAR_CASTED1]], align 4
+// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..4, i64 [[TMP3]])
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK9: arraydestroy.body:
-// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
-// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
-// CHECK9: arraydestroy.done1:
+// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK9: arraydestroy.done2:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4
-// CHECK9-NEXT: ret i32 [[TMP1]]
+// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK9-NEXT: ret i32 [[TMP5]]
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi
@@ -1921,67 +1925,63 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
-// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
+// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
-// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
-// CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128
-// CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128
+// CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128
+// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128
// CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
-// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
-// CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
+// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
+// CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
-// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
+// CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 128
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 128
-// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC2]], ptr align 128 [[TMP0]], i64 8, i1 false)
-// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
-// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
-// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
+// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i64 8, i1 false)
+// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
+// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
+// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK9: omp.arraycpy.body:
-// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])
// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])
// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
-// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
-// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
-// CHECK9: omp.arraycpy.done4:
-// CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
-// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR5]], ptr nonnull align 4 dereferenceable(4) [[TMP3]], ptr [[AGG_TMP6]])
-// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR1]], align 128
-// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 128
-// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0
-// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX7]], ptr align 128 [[VAR5]], i64 4, i1 false)
-// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
-// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2
+// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
+// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK9: omp.arraycpy.done3:
+// CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
+// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])
+// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
+// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128
+// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i64 0, i64 0
+// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i64 4, i1 false)
+// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]
+// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK9: arraydestroy.body:
-// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
-// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
-// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
-// CHECK9: arraydestroy.done9:
+// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
+// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK9: arraydestroy.done8:
// CHECK9-NEXT: ret void
//
//
@@ -2011,18 +2011,14 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
-// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] {
+// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
+// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR1]], align 128
+// CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
// CHECK9-NEXT: ret void
//
//
@@ -2331,27 +2327,23 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
-// CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] {
+// CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] {
// CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8
+// CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
// CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
-// CHECK11-NEXT: [[G1:%.*]] = alloca i32, align 128
// CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK11-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8
+// CHECK11-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
// CHECK11-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
-// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8
-// CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr [[TMP0]], align 128
-// CHECK11-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128
-// CHECK11-NEXT: store i32 1, ptr [[G1]], align 128
+// CHECK11-NEXT: store i32 1, ptr [[G_ADDR]], align 4
// CHECK11-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0
-// CHECK11-NEXT: store ptr [[G1]], ptr [[TMP2]], align 8
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1
-// CHECK11-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP3]], align 8
+// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0
+// CHECK11-NEXT: store ptr [[G_ADDR]], ptr [[TMP0]], align 8
+// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1
+// CHECK11-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP1]], align 8
// CHECK11-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr nonnull align 8 dereferenceable(16) [[REF_TMP]])
// CHECK11-NEXT: ret void
//
@@ -2401,33 +2393,33 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
+// CHECK12-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
// CHECK12-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
// CHECK12-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
-// CHECK12-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
-// CHECK12-NEXT: store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4
-// CHECK12-NEXT: [[TMP1:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
-// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.omp_outlined., ptr @g, i64 [[TMP1]])
+// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128
+// CHECK12-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4
+// CHECK12-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8
+// CHECK12-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
+// CHECK12-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
+// CHECK12-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
+// CHECK12-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.omp_outlined., i64 [[TMP1]], i64 [[TMP3]])
// CHECK12-NEXT: ret void
//
//
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
-// CHECK12-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK12-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK12-NEXT: entry:
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8
+// CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
// CHECK12-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
-// CHECK12-NEXT: [[G1:%.*]] = alloca i32, align 128
// CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, align 128
// CHECK12-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK12-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK12-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8
+// CHECK12-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
// CHECK12-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
-// CHECK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8
-// CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, ptr [[TMP0]], align 128
-// CHECK12-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128
-// CHECK12-NEXT: store i32 1, ptr [[G1]], align 128
+// CHECK12-NEXT: store i32 1, ptr [[G_ADDR]], align 4
// CHECK12-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4
// CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 0
// CHECK12-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 128
@@ -2440,14 +2432,14 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 4
// CHECK12-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 8
// CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 7
-// CHECK12-NEXT: [[TMP2:%.*]] = load volatile i32, ptr [[G1]], align 128
-// CHECK12-NEXT: store volatile i32 [[TMP2]], ptr [[BLOCK_CAPTURED]], align 128
-// CHECK12-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 5
-// CHECK12-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
-// CHECK12-NEXT: store i32 [[TMP3]], ptr [[BLOCK_CAPTURED2]], align 32
-// CHECK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
-// CHECK12-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
-// CHECK12-NEXT: call void [[TMP5]](ptr [[BLOCK]])
+// CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, ptr [[G_ADDR]], align 4
+// CHECK12-NEXT: store volatile i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 128
+// CHECK12-NEXT: [[BLOCK_CAPTURED1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, [92 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 5
+// CHECK12-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
+// CHECK12-NEXT: store i32 [[TMP1]], ptr [[BLOCK_CAPTURED1]], align 32
+// CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3
+// CHECK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CHECK12-NEXT: call void [[TMP3]](ptr [[BLOCK]])
// CHECK12-NEXT: ret void
//
//
diff --git a/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp
index a120b8bfb1904..d316ee8b3e411 100644
--- a/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp
@@ -1,3 +1,4 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
@@ -7,11 +8,10 @@
// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
-// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}
+// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY4 %s
// expected-no-diagnostics
#ifndef ARRAY
@@ -30,15 +30,6 @@ struct S {
volatile double g;
-// CHECK-DAG: [[KMP_TASK_T_TY:%.+]] = type { i8*, i32 (i32, i8*)*, i32, %union{{.+}}, %union{{.+}}, i64, i64, i64, i32, i8* }
-// CHECK-DAG: [[S_DOUBLE_TY:%.+]] = type { double }
-// CHECK-DAG: [[PRIVATES_MAIN_TY:%.+]] = type {{.?}}{ [2 x [[S_DOUBLE_TY]]], [[S_DOUBLE_TY]], i32, [2 x i32]
-// CHECK-DAG: [[CAP_MAIN_TY:%.+]] = type { [2 x [[S_DOUBLE_TY]]]*, [[S_DOUBLE_TY]]* }
-// CHECK-DAG: [[KMP_TASK_MAIN_TY:%.+]] = type { [[KMP_TASK_T_TY]], [[PRIVATES_MAIN_TY]] }
-// CHECK-DAG: [[S_INT_TY:%.+]] = type { i32 }
-// CHECK-DAG: [[CAP_TMAIN_TY:%.+]] = type { [2 x [[S_INT_TY]]]*, [[S_INT_TY]]* }
-// CHECK-DAG: [[PRIVATES_TMAIN_TY:%.+]] = type { i32, [2 x i32], [2 x [[S_INT_TY]]], [[S_INT_TY]], [104 x i8] }
-// CHECK-DAG: [[KMP_TASK_TMAIN_TY:%.+]] = type { [[KMP_TASK_T_TY]], [{{[0-9]+}} x i8], [[PRIVATES_TMAIN_TY]] }
template <typename T>
T tmain() {
S<T> ttt;
@@ -58,48 +49,14 @@ T tmain() {
int main() {
static int sivar;
#ifdef LAMBDA
- // LAMBDA: [[G:@.+]] ={{.*}} global double
- // LAMBDA: [[SIVAR:@.+]] = internal global i{{[0-9]+}} 0,
- // LAMBDA-LABEL: @main
- // LAMBDA: call{{( x86_thiscallcc)?}} void [[OUTER_LAMBDA:@.+]](
[&]() {
- // LAMBDA: define{{.*}} internal{{.*}} void [[OUTER_LAMBDA]](
-// LAMBDA: [[RES:%.+]] = call {{.*}}i32 @__kmpc_master(
-// LAMBDA-NEXT: [[IS_MASTER:%.+]] = icmp ne i32 [[RES]], 0
-// LAMBDA-NEXT: br i1 [[IS_MASTER]], label {{%?}}[[THEN:.+]], label {{%?}}[[EXIT:.+]]
-// LAMBDA: [[THEN]]
-// LAMBDA: [[RES:%.+]] = call i8* @__kmpc_omp_task_alloc(%{{[^ ]+}} @{{[^,]+}}, i32 %{{[^,]+}}, i32 1, i64 96, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %{{[^*]+}}*)* [[TASK_ENTRY:@[^ ]+]] to i32 (i32, i8*)*))
-// LAMBDA: [[PRIVATES:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i{{.+}} 0, i{{.+}} 1
-// LAMBDA: [[G_PRIVATE_ADDR:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0
-// LAMBDA: [[G_VAL:%.+]] = load volatile double, double* @{{.+}},
-// LAMBDA: store volatile double [[G_VAL]], double* [[G_PRIVATE_ADDR]]
-
-// LAMBDA: [[SIVAR_PRIVATE_ADDR:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1
-// LAMBDA: [[SIVAR_VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* @{{.+}},
-// LAMBDA: store i{{[0-9]+}} [[SIVAR_VAL]], i{{[0-9]+}}* [[SIVAR_PRIVATE_ADDR]]
-
-// LAMBDA: call void @__kmpc_taskloop(%{{.+}}* @{{.+}}, i32 %{{.+}}, i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* null)
-// LAMBDA: call {{.*}}void @__kmpc_end_master(
-// LAMBDA-NEXT: br label {{%?}}[[EXIT]]
-// LAMBDA: [[EXIT]]
-// LAMBDA: ret
+
+
#pragma omp parallel master taskloop firstprivate(g, sivar)
for (int i = 0; i < 10; ++i) {
- // LAMBDA: define {{.+}} void [[INNER_LAMBDA:@.+]](%{{.+}}* {{[^,]*}} [[ARG_PTR:%.+]])
- // LAMBDA: store %{{.+}}* [[ARG_PTR]], %{{.+}}** [[ARG_PTR_REF:%.+]],
- // LAMBDA: [[ARG_PTR:%.+]] = load %{{.+}}*, %{{.+}}** [[ARG_PTR_REF]]
- // LAMBDA: [[G_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // LAMBDA: [[G_REF:%.+]] = load double*, double** [[G_PTR_REF]]
- // LAMBDA: store double 2.0{{.+}}, double* [[G_REF]]
-
- // LAMBDA: store double* %{{.+}}, double** %{{.+}},
- // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1)
+
g = 1;
sivar = 11;
- // LAMBDA: store double 1.0{{.+}}, double* %{{.+}},
- // LAMBDA: store i{{[0-9]+}} 11, i{{[0-9]+}}* %{{.+}},
- // LAMBDA: call void [[INNER_LAMBDA]](%
- // LAMBDA: ret
[&]() {
g = 2;
sivar = 22;
@@ -108,51 +65,13 @@ int main() {
}();
return 0;
#elif defined(BLOCKS)
- // BLOCKS: [[G:@.+]] ={{.*}} global double
- // BLOCKS: [[SIVAR:@.+]] = internal global i{{[0-9]+}} 0,
- // BLOCKS-LABEL: @main
- // BLOCKS: call void {{%.+}}(i8
^{
- // BLOCKS: define{{.*}} internal{{.*}} void {{.+}}(i8*
- // BLOCKS: [[RES:%.+]] = call {{.*}}i32 @__kmpc_master(
- // BLOCKS-NEXT: [[IS_MASTER:%.+]] = icmp ne i32 [[RES]], 0
- // BLOCKS-NEXT: br i1 [[IS_MASTER]], label {{%?}}[[THEN:.+]], label {{%?}}[[EXIT:.+]]
- // BLOCKS: [[THEN]]
- // BLOCKS: [[RES:%.+]] = call i8* @__kmpc_omp_task_alloc(%{{[^ ]+}} @{{[^,]+}}, i32 %{{[^,]+}}, i32 1, i64 96, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %{{[^*]+}}*)* [[TASK_ENTRY:@[^ ]+]] to i32 (i32, i8*)*))
- // BLOCKS: [[PRIVATES:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i{{.+}} 0, i{{.+}} 1
- // BLOCKS: [[G_PRIVATE_ADDR:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0
- // BLOCKS: [[G_VAL:%.+]] = load volatile double, double* @{{.+}},
- // BLOCKS: store volatile double [[G_VAL]], double* [[G_PRIVATE_ADDR]]
-
- // BLOCKS: [[SIVAR_PRIVATE_ADDR:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1
- // BLOCKS: [[SIVAR_VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* @{{.+}},
- // BLOCKS: store i{{[0-9]+}} [[SIVAR_VAL]], i{{[0-9]+}}* [[SIVAR_PRIVATE_ADDR]]
- // BLOCKS: call void @__kmpc_taskloop(%{{.+}}* @{{.+}}, i32 %{{.+}}, i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* null)
- // BLOCKS: call {{.*}}void @__kmpc_end_master(
- // BLOCKS-NEXT: br label {{%?}}[[EXIT]]
- // BLOCKS: [[EXIT]]
- // BLOCKS: ret
+
#pragma omp parallel master taskloop firstprivate(g, sivar)
for (int i = 0; i < 10; ++i) {
- // BLOCKS: define {{.+}} void {{@.+}}(i8*
- // BLOCKS-NOT: [[G]]{{[[^:word:]]}}
- // BLOCKS: store double 2.0{{.+}}, double*
- // BLOCKS-NOT: [[G]]{{[[^:word:]]}}
- // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}}
- // BLOCKS: store i{{[0-9]+}} 22, i{{[0-9]+}}*
- // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}}
- // BLOCKS: ret
-
- // BLOCKS: store double* %{{.+}}, double** %{{.+}},
- // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}},
- // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1)
+
g = 1;
sivar = 11;
- // BLOCKS: store double 1.0{{.+}}, double* %{{.+}},
- // BLOCKS-NOT: [[G]]{{[[^:word:]]}}
- // BLOCKS: store i{{[0-9]+}} 11, i{{[0-9]+}}* %{{.+}},
- // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}}
- // BLOCKS: call void {{%.+}}(i8
^{
g = 2;
sivar = 22;
@@ -177,303 +96,86 @@ int main() {
#endif
}
-// CHECK: [[SIVAR:.+]] = internal global i{{[0-9]+}} 0,
-// CHECK: define{{.*}} i{{[0-9]+}} @main()
-// CHECK: alloca [[S_DOUBLE_TY]],
-// CHECK: [[TEST:%.+]] = alloca [[S_DOUBLE_TY]],
-// CHECK: [[T_VAR_ADDR:%.+]] = alloca i32,
-// CHECK: [[VEC_ADDR:%.+]] = alloca [2 x i32],
-// CHECK: [[S_ARR_ADDR:%.+]] = alloca [2 x [[S_DOUBLE_TY]]],
-// CHECK: [[VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]],
-
-// CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR:@.+]]([[S_DOUBLE_TY]]* {{[^,]*}} [[TEST]],
-
-// CHECK: [[RES:%.+]] = call {{.*}}i32 @__kmpc_master(
-// CHECK-NEXT: [[IS_MASTER:%.+]] = icmp ne i32 [[RES]], 0
-// CHECK-NEXT: br i1 [[IS_MASTER]], label {{%?}}[[THEN:.+]], label {{%?}}[[EXIT:.+]]
-// CHECK: [[THEN]]
+
+
// Store original variables in capture struct.
-// CHECK: [[S_ARR_REF:%.+]] = getelementptr inbounds [[CAP_MAIN_TY]], [[CAP_MAIN_TY]]* %{{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: store [2 x [[S_DOUBLE_TY]]]* %{{.+}}, [2 x [[S_DOUBLE_TY]]]** [[S_ARR_REF]],
-// CHECK: [[VAR_REF:%.+]] = getelementptr inbounds [[CAP_MAIN_TY]], [[CAP_MAIN_TY]]* %{{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 1
-// CHECK: store [[S_DOUBLE_TY]]* %{{.+}}, [[S_DOUBLE_TY]]** [[VAR_REF]],
// Allocate task.
// Returns struct kmp_task_t {
// [[KMP_TASK_T]] task_data;
// [[KMP_TASK_MAIN_TY]] privates;
// };
-// CHECK: [[RES:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i32 9, i64 120, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, [[KMP_TASK_MAIN_TY]]*)* [[TASK_ENTRY:@[^ ]+]] to i32 (i32, i8*)*))
-// CHECK: [[RES_KMP_TASK:%.+]] = bitcast i8* [[RES]] to [[KMP_TASK_MAIN_TY]]*
// Fill kmp_task_t->shareds by copying from original capture argument.
-// CHECK: [[TASK:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: [[SHAREDS_REF_ADDR:%.+]] = getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* [[TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: [[SHAREDS_REF:%.+]] = load i8*, i8** [[SHAREDS_REF_ADDR]],
-// CHECK: [[CAPTURES_ADDR:%.+]] = bitcast [[CAP_MAIN_TY]]* %{{.+}} to i8*
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[SHAREDS_REF]], i8* align 8 [[CAPTURES_ADDR]], i64 16, i1 false)
// Initialize kmp_task_t->privates with default values (no init for simple types, default constructors for classes).
// Also copy address of private copy to the corresponding shareds reference.
-// CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
// Constructors for s_arr and var.
// s_arr;
-// CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: bitcast [2 x [[S_DOUBLE_TY]]]* %{{.+}} to [[S_DOUBLE_TY]]*
-// CHECK: call void [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]* {{[^,]*}} [[S_ARR_CUR:%[^,]+]],
-// CHECK: getelementptr [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* [[S_ARR_CUR]], i{{.+}} 1
-// CHECK: getelementptr [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i{{.+}} 1
-// CHECK: icmp eq
-// CHECK: br i1
// var;
-// CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1
-// CHECK-NEXT: call void [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]* {{[^,]*}} [[PRIVATE_VAR_REF]], [[S_DOUBLE_TY]]* {{.*}},
// t_var;
-// CHECK: [[PRIVATE_T_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2
-// CHECK-NEXT: [[T_VAR:%.+]] = load i32, i32* %{{.+}},
-// CHECK-NEXT: store i32 [[T_VAR]], i32* [[PRIVATE_T_VAR_REF]],
// vec;
-// CHECK: [[PRIVATE_VEC_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3
-// CHECK-NEXT: bitcast [2 x i32]* [[PRIVATE_VEC_REF]] to i8*
-// CHECK-NEXT: bitcast [2 x i32]* %{{.+}} to i8*
-// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(
// sivar;
-// CHECK: [[PRIVATE_SIVAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 4
-// CHECK-NEXT: [[SIVAR:%.+]] = load i32, i32* @{{.+}},
-// CHECK-NEXT: store i32 [[SIVAR]], i32* [[PRIVATE_SIVAR_REF]],
// Provide pointer to destructor function, which will destroy private variables at the end of the task.
-// CHECK: [[DESTRUCTORS_REF:%.+]] = getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* [[TASK]], i{{.+}} 0, i{{.+}} 3
-// CHECK: [[DESTRUCTORS_PTR:%.+]] = bitcast %union{{.+}}* [[DESTRUCTORS_REF]] to i32 (i32, i8*)**
-// CHECK: store i32 (i32, i8*)* bitcast (i32 (i32, [[KMP_TASK_MAIN_TY]]*)* [[DESTRUCTORS:@.+]] to i32 (i32, i8*)*), i32 (i32, i8*)** [[DESTRUCTORS_PTR]],
// Start task.
-// CHECK: call void @__kmpc_taskloop(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_MAIN_TY]]*, [[KMP_TASK_MAIN_TY]]*, i32)* [[MAIN_DUP:@.+]] to i8*))
-// CHECK: call {{.*}}void @__kmpc_end_master(
-// CHECK-NEXT: br label {{%?}}[[EXIT]]
-// CHECK: [[EXIT]]
-
-// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5)
-// CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]**
-// CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0
-// CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}},
-// CHECK: store [2 x [[S_DOUBLE_TY]]]* [[PRIV_S_VAR]], [2 x [[S_DOUBLE_TY]]]** [[ARG3]],
-// CHECK: [[PRIV_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 1
-// CHECK: [[ARG1:%.+]] = load [[S_DOUBLE_TY]]**, [[S_DOUBLE_TY]]*** {{.+}},
-// CHECK: store [[S_DOUBLE_TY]]* [[PRIV_VAR]], [[S_DOUBLE_TY]]** [[ARG1]],
-// CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 2
-// CHECK: [[ARG2:%.+]] = load i32**, i32*** %{{.+}},
-// CHECK: store i32* [[PRIV_T_VAR]], i32** [[ARG2]],
-// CHECK: [[PRIV_VEC:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 3
-// CHECK: [[ARG4:%.+]] = load [2 x i32]**, [2 x i32]*** %{{.+}},
-// CHECK: store [2 x i32]* [[PRIV_VEC]], [2 x i32]** [[ARG4]],
-// CHECK: [[PRIV_SIVAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 4
-// CHECK: [[ARG5:%.+]] = load i{{[0-9]+}}**, i{{[0-9]+}}*** %{{.+}},
-// CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]],
-// CHECK: ret void
-
-// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1)
-
-// CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*,
-// CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*,
-// CHECK: [[PRIV_S_ARR_ADDR:%.+]] = alloca [2 x [[S_DOUBLE_TY]]]*,
-// CHECK: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*,
-// CHECK: [[PRIV_SIVAR_ADDR:%.+]] = alloca i32*,
-// CHECK: store void (i8*, ...)* bitcast (void ([[PRIVATES_MAIN_TY]]*, [[S_DOUBLE_TY]]**, i32**, [2 x [[S_DOUBLE_TY]]]**, [2 x i32]**, i32**)* [[PRIVATES_MAP_FN]] to void (i8*, ...)*), void (i8*, ...)** [[MAP_FN_ADDR:%.+]],
-// CHECK: [[MAP_FN:%.+]] = load void (i8*, ...)*, void (i8*, ...)** [[MAP_FN_ADDR]],
-
-// CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* [[MAP_FN]] to void (i8*,
-// CHECK: call void [[FN]](i8* %{{.+}}, [[S_DOUBLE_TY]]** [[PRIV_VAR_ADDR]], i32** [[PRIV_T_VAR_ADDR]], [2 x [[S_DOUBLE_TY]]]** [[PRIV_S_ARR_ADDR]], [2 x i32]** [[PRIV_VEC_ADDR]], i32** [[PRIV_SIVAR_ADDR]])
-
-// CHECK: [[PRIV_VAR:%.+]] = load [[S_DOUBLE_TY]]*, [[S_DOUBLE_TY]]** [[PRIV_VAR_ADDR]],
-// CHECK: [[PRIV_T_VAR:%.+]] = load i32*, i32** [[PRIV_T_VAR_ADDR]],
-// CHECK: [[PRIV_S_ARR:%.+]] = load [2 x [[S_DOUBLE_TY]]]*, [2 x [[S_DOUBLE_TY]]]** [[PRIV_S_ARR_ADDR]],
-// CHECK: [[PRIV_VEC:%.+]] = load [2 x i32]*, [2 x i32]** [[PRIV_VEC_ADDR]],
-// CHECK: [[PRIV_SIVAR:%.+]] = load i32*, i32** [[PRIV_SIVAR_ADDR]],
+
+
+
+
+
// Privates actually are used.
-// CHECK-DAG: [[PRIV_VAR]]
-// CHECK-DAG: [[PRIV_T_VAR]]
-// CHECK-DAG: [[PRIV_S_ARR]]
-// CHECK-DAG: [[PRIV_VEC]]
-// CHECK-DAG: [[PRIV_SIVAR]]
-
-// CHECK: ret
-
-// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2)
-// CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1
-// CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0
-// CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0
-// CHECK: getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i64 2
-// CHECK: br i1 %
-
-// CHECK: phi [[S_DOUBLE_TY]]*
-// CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]*
-// CHECK: getelementptr [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i32 1
-// CHECK: icmp eq [[S_DOUBLE_TY]]* %
-// CHECK: br i1 %
-
-// CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 1
-// CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]*
-// CHECK: ret void
-
-// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %{{.+}}, [[KMP_TASK_MAIN_TY]]* noalias noundef %{{.+}})
-// CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
-// CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0
-// CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1
-// CHECK: call void @_ZN1SIdED1Ev([[S_DOUBLE_TY]]* {{[^,]*}} [[PRIVATE_VAR_REF]])
-// CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* [[PRIVATE_S_ARR_REF]], i{{.+}} 0, i{{.+}} 0
-// CHECK: getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i{{.+}} 2
-// CHECK: [[PRIVATE_S_ARR_ELEM_REF:%.+]] = getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i{{.+}} -1
-// CHECK: call void @_ZN1SIdED1Ev([[S_DOUBLE_TY]]* {{[^,]*}} [[PRIVATE_S_ARR_ELEM_REF]])
-// CHECK: icmp eq
-// CHECK: br i1
-// CHECK: ret i32
-
-// CHECK: alloca [[S_INT_TY]],
-// CHECK: [[TEST:%.+]] = alloca [[S_INT_TY]],
-// CHECK: [[T_VAR_ADDR:%.+]] = alloca i32, align 128
-// CHECK: [[VEC_ADDR:%.+]] = alloca [2 x i32],
-// CHECK: [[S_ARR_ADDR:%.+]] = alloca [2 x [[S_INT_TY]]],
-// CHECK: [[VAR_ADDR:%.+]] = alloca [[S_INT_TY]],
-
-// CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR:@.+]]([[S_INT_TY]]* {{[^,]*}} [[TEST]],
+
+
+
+
+
+
+
// Store original variables in capture struct.
-// CHECK: [[S_ARR_REF:%.+]] = getelementptr inbounds [[CAP_TMAIN_TY]], [[CAP_TMAIN_TY]]* %{{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: store [2 x [[S_INT_TY]]]* %{{.+}}, [2 x [[S_INT_TY]]]** [[S_ARR_REF]],
-// CHECK: [[VAR_REF:%.+]] = getelementptr inbounds [[CAP_TMAIN_TY]], [[CAP_TMAIN_TY]]* %{{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 1
-// CHECK: store [[S_INT_TY]]* %{{.+}}, [[S_INT_TY]]** [[VAR_REF]],
// Allocate task.
// Returns struct kmp_task_t {
// [[KMP_TASK_T_TY]] task_data;
// [[KMP_TASK_TMAIN_TY]] privates;
// };
-// CHECK: [[RES:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i32 9, i64 256, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, [[KMP_TASK_TMAIN_TY]]*)* [[TASK_ENTRY:@[^ ]+]] to i32 (i32, i8*)*))
-// CHECK: [[RES_KMP_TASK:%.+]] = bitcast i8* [[RES]] to [[KMP_TASK_TMAIN_TY]]*
// Fill kmp_task_t->shareds by copying from original capture argument.
-// CHECK: [[TASK:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: [[SHAREDS_REF_ADDR:%.+]] = getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* [[TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: [[SHAREDS_REF:%.+]] = load i8*, i8** [[SHAREDS_REF_ADDR]],
-// CHECK: [[CAPTURES_ADDR:%.+]] = bitcast [[CAP_TMAIN_TY]]* %{{.+}} to i8*
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[SHAREDS_REF]], i8* align 8 [[CAPTURES_ADDR]], i64 16, i1 false)
// Initialize kmp_task_t->privates with default values (no init for simple types, default constructors for classes).
-// CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
// t_var;
-// CHECK: [[PRIVATE_T_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0
-// CHECK: [[T_VAR:%.+]] = load i32, i32* %{{.+}}, align 128
-// CHECK: store i32 [[T_VAR]], i32* [[PRIVATE_T_VAR_REF]], align 128
// vec;
-// CHECK: [[PRIVATE_VEC_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1
-// CHECK-NEXT: bitcast [2 x i32]* [[PRIVATE_VEC_REF]] to i8*
-// CHECK-NEXT: bitcast [2 x i32]* %{{.+}} to i8*
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(
// Constructors for s_arr and var.
// a_arr;
-// CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
-// CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* [[PRIVATE_S_ARR_REF]], i{{.+}} 0, i{{.+}} 0
-// CHECK: bitcast [2 x [[S_INT_TY]]]* %{{.+}} to [[S_INT_TY]]*
-// CHECK: getelementptr inbounds [[S_INT_TY]], [[S_INT_TY]]* %{{.+}}, i{{.+}} 2
-// CHECK: call void [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]* {{[^,]*}} [[S_ARR_CUR:%[^,]+]],
-// CHECK: getelementptr [[S_INT_TY]], [[S_INT_TY]]* [[S_ARR_CUR]], i{{.+}} 1
-// CHECK: icmp eq
-// CHECK: br i1
// var;
-// CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3
-// CHECK-NEXT: call void [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]* {{[^,]*}} [[PRIVATE_VAR_REF]],
// Provide pointer to destructor function, which will destroy private variables at the end of the task.
-// CHECK: [[DESTRUCTORS_REF:%.+]] = getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* [[TASK]], i{{.+}} 0, i{{.+}} 3
-// CHECK: [[DESTRUCTORS_PTR:%.+]] = bitcast %union{{.+}}* [[DESTRUCTORS_REF]] to i32 (i32, i8*)**
-// CHECK: store i32 (i32, i8*)* bitcast (i32 (i32, [[KMP_TASK_TMAIN_TY]]*)* [[DESTRUCTORS:@.+]] to i32 (i32, i8*)*), i32 (i32, i8*)** [[DESTRUCTORS_PTR]],
// Start task.
-// CHECK: call void @__kmpc_taskloop(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_TMAIN_TY]]*, [[KMP_TASK_TMAIN_TY]]*, i32)* [[TMAIN_DUP:@.+]] to i8*))
-
-// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %{{.+}}, i32** noalias noundef %{{.+}}, [2 x i32]** noalias noundef %{{.+}}, [2 x [[S_INT_TY]]]** noalias noundef %{{.+}}, [[S_INT_TY]]** noalias noundef %{{.+}})
-// CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]**
-// CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0
-// CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}},
-// CHECK: store i32* [[PRIV_T_VAR]], i32** [[ARG1]],
-// CHECK: [[PRIV_VEC:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 1
-// CHECK: [[ARG2:%.+]] = load [2 x i32]**, [2 x i32]*** %{{.+}},
-// CHECK: store [2 x i32]* [[PRIV_VEC]], [2 x i32]** [[ARG2]],
-// CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 2
-// CHECK: [[ARG3:%.+]] = load [2 x [[S_INT_TY]]]**, [2 x [[S_INT_TY]]]*** %{{.+}},
-// CHECK: store [2 x [[S_INT_TY]]]* [[PRIV_S_VAR]], [2 x [[S_INT_TY]]]** [[ARG3]],
-// CHECK: [[PRIV_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 3
-// CHECK: [[ARG4:%.+]] = load [[S_INT_TY]]**, [[S_INT_TY]]*** {{.+}},
-// CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]],
-// CHECK: ret void
-
-// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1)
-// CHECK: alloca i32*,
-// CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*,
-// CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*,
-// CHECK-DAG: [[PRIV_S_ARR_ADDR:%.+]] = alloca [2 x [[S_INT_TY]]]*,
-// CHECK-DAG: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_INT_TY]]*,
-// CHECK: store void (i8*, ...)* bitcast (void ([[PRIVATES_TMAIN_TY]]*, i32**, [2 x i32]**, [2 x [[S_INT_TY]]]**, [[S_INT_TY]]**)* [[PRIVATES_MAP_FN]] to void (i8*, ...)*), void (i8*, ...)** [[MAP_FN_ADDR:%.+]],
-// CHECK: [[MAP_FN:%.+]] = load void (i8*, ...)*, void (i8*, ...)** [[MAP_FN_ADDR]],
-// CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* [[MAP_FN]] to void (i8*,
-// CHECK: call void [[FN]](i8* %{{.+}}, i32** [[PRIV_T_VAR_ADDR]], [2 x i32]** [[PRIV_VEC_ADDR]], [2 x [[S_INT_TY]]]** [[PRIV_S_ARR_ADDR]], [[S_INT_TY]]** [[PRIV_VAR_ADDR]])
-// CHECK: [[PRIV_T_VAR:%.+]] = load i32*, i32** [[PRIV_T_VAR_ADDR]],
-// CHECK: [[PRIV_VEC:%.+]] = load [2 x i32]*, [2 x i32]** [[PRIV_VEC_ADDR]],
-// CHECK: [[PRIV_S_ARR:%.+]] = load [2 x [[S_INT_TY]]]*, [2 x [[S_INT_TY]]]** [[PRIV_S_ARR_ADDR]],
-// CHECK: [[PRIV_VAR:%.+]] = load [[S_INT_TY]]*, [[S_INT_TY]]** [[PRIV_VAR_ADDR]],
+
+
// Privates actually are used.
-// CHECK-DAG: [[PRIV_VAR]]
-// CHECK-DAG: [[PRIV_T_VAR]]
-// CHECK-DAG: [[PRIV_S_ARR]]
-// CHECK-DAG: [[PRIV_VEC]]
-
-// CHECK: ret
-
-// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2)
-// CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2
-// CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2
-// CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0
-// CHECK: getelementptr inbounds [[S_INT_TY]], [[S_INT_TY]]* %{{.+}}, i64 2
-// CHECK: br i1 %
-
-// CHECK: phi [[S_INT_TY]]*
-// CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]*
-// CHECK: getelementptr [[S_INT_TY]], [[S_INT_TY]]* %{{.+}}, i32 1
-// CHECK: icmp eq [[S_INT_TY]]* %
-// CHECK: br i1 %
-
-// CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 3
-// CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]*
-// CHECK: ret void
-
-// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1)
-// CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
-// CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2
-// CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3
-// CHECK: call void @_ZN1SIiED1Ev([[S_INT_TY]]* {{[^,]*}} [[PRIVATE_VAR_REF]])
-// CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* [[PRIVATE_S_ARR_REF]], i{{.+}} 0, i{{.+}} 0
-// CHECK: getelementptr inbounds [[S_INT_TY]], [[S_INT_TY]]* %{{.+}}, i{{.+}} 2
-// CHECK: [[PRIVATE_S_ARR_ELEM_REF:%.+]] = getelementptr inbounds [[S_INT_TY]], [[S_INT_TY]]* %{{.+}}, i{{.+}} -1
-// CHECK: call void @_ZN1SIiED1Ev([[S_INT_TY]]* {{[^,]*}} [[PRIVATE_S_ARR_ELEM_REF]])
-// CHECK: icmp eq
-// CHECK: br i1
-// CHECK: ret i32
+
+
+
+
+
#endif
#else
-// ARRAY-LABEL: array_func
struct St {
int a, b;
St() : a(0), b(0) {}
@@ -482,13 +184,2207 @@ struct St {
};
void array_func(int n, float a[n], St s[2]) {
-// ARRAY: call i8* @__kmpc_omp_task_alloc(
-// ARRAY: call void @__kmpc_taskloop(
-// ARRAY: store float** %{{.+}}, float*** %{{.+}},
-// ARRAY: store %struct.St** %{{.+}}, %struct.St*** %{{.+}},
#pragma omp parallel master taskloop firstprivate(a, s)
for (int i = 0; i < 10; ++i)
;
}
#endif
+// CHECK-LABEL: define {{[^@]+}}@main
+// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8
+// CHECK-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8
+// CHECK-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16
+// CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8
+// CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
+// CHECK-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// CHECK-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]])
+// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00)
+// CHECK-NEXT: store i32 0, i32* [[T_VAR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false)
+// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
+// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00)
+// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
+// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00)
+// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00)
+// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4
+// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
+// CHECK-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
+// CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]])
+// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
+// CHECK-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]]
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
+// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// CHECK: arraydestroy.body:
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK: arraydestroy.done1:
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]]
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]]
+// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
+// CHECK-NEXT: ret i32 [[TMP4]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// CHECK-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_outlined.
+// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
+// CHECK-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
+// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
+// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
+// CHECK-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
+// CHECK-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
+// CHECK-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
+// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
+// CHECK-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
+// CHECK-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
+// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
+// CHECK-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
+// CHECK: omp_if.then:
+// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
+// CHECK-NEXT: store [2 x %struct.S]* [[TMP1]], [2 x %struct.S]** [[TMP7]], align 8
+// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
+// CHECK-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP8]], align 8
+// CHECK-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 9, i64 120, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
+// CHECK-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates*
+// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP10]], i32 0, i32 0
+// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 0
+// CHECK-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 [[TMP14]], i64 16, i1 false)
+// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP10]], i32 0, i32 1
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 0
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP16]], i32 0, i32 0
+// CHECK-NEXT: [[TMP17:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
+// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP18]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK: omp.arraycpy.body:
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00)
+// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP18]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK: omp.arraycpy.done1:
+// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 1
+// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP19]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP2]], double noundef 0.000000e+00)
+// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 2
+// CHECK-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK-NEXT: store i32 [[TMP21]], i32* [[TMP20]], align 8
+// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 3
+// CHECK-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP22]] to i8*
+// CHECK-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i64 8, i1 false)
+// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 4
+// CHECK-NEXT: [[TMP26:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
+// CHECK-NEXT: store i32 [[TMP26]], i32* [[TMP25]], align 4
+// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 3
+// CHECK-NEXT: [[TMP28:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP27]] to i32 (i32, i8*)**
+// CHECK-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_destructor. to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP28]], align 8
+// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 5
+// CHECK-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 6
+// CHECK-NEXT: store i64 9, i64* [[TMP30]], align 8
+// CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 7
+// CHECK-NEXT: store i64 1, i64* [[TMP31]], align 8
+// CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 9
+// CHECK-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i8*
+// CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP33]], i8 0, i64 8, i1 false)
+// CHECK-NEXT: [[TMP34:%.*]] = load i64, i64* [[TMP31]], align 8
+// CHECK-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i8* [[TMP9]], i32 1, i64* [[TMP29]], i64* [[TMP30]], i64 [[TMP34]], i32 1, i32 0, i64 0, i8* bitcast (void (%struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates*, i32)* @.omp_task_dup. to i8*))
+// CHECK-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: br label [[OMP_IF_END]]
+// CHECK: omp_if.end:
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_privates_map.
+// CHECK-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], %struct.S** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]], [2 x %struct.S]** noalias noundef [[TMP3:%.*]], [2 x i32]** noalias noundef [[TMP4:%.*]], i32** noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S**, align 8
+// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8
+// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca [2 x %struct.S]**, align 8
+// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca [2 x i32]**, align 8
+// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca i32**, align 8
+// CHECK-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
+// CHECK-NEXT: store %struct.S** [[TMP1]], %struct.S*** [[DOTADDR1]], align 8
+// CHECK-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8
+// CHECK-NEXT: store [2 x %struct.S]** [[TMP3]], [2 x %struct.S]*** [[DOTADDR3]], align 8
+// CHECK-NEXT: store [2 x i32]** [[TMP4]], [2 x i32]*** [[DOTADDR4]], align 8
+// CHECK-NEXT: store i32** [[TMP5]], i32*** [[DOTADDR5]], align 8
+// CHECK-NEXT: [[TMP6:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
+// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 0
+// CHECK-NEXT: [[TMP8:%.*]] = load [2 x %struct.S]**, [2 x %struct.S]*** [[DOTADDR3]], align 8
+// CHECK-NEXT: store [2 x %struct.S]* [[TMP7]], [2 x %struct.S]** [[TMP8]], align 8
+// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 1
+// CHECK-NEXT: [[TMP10:%.*]] = load %struct.S**, %struct.S*** [[DOTADDR1]], align 8
+// CHECK-NEXT: store %struct.S* [[TMP9]], %struct.S** [[TMP10]], align 8
+// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 2
+// CHECK-NEXT: [[TMP12:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8
+// CHECK-NEXT: store i32* [[TMP11]], i32** [[TMP12]], align 8
+// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 3
+// CHECK-NEXT: [[TMP14:%.*]] = load [2 x i32]**, [2 x i32]*** [[DOTADDR4]], align 8
+// CHECK-NEXT: store [2 x i32]* [[TMP13]], [2 x i32]** [[TMP14]], align 8
+// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 4
+// CHECK-NEXT: [[TMP16:%.*]] = load i32**, i32*** [[DOTADDR5]], align 8
+// CHECK-NEXT: store i32* [[TMP15]], i32** [[TMP16]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_entry.
+// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
+// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [2 x %struct.S]*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [2 x i32]*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR4_I:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[I_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
+// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
+// CHECK-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
+// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
+// CHECK-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
+// CHECK-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
+// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5
+// CHECK-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6
+// CHECK-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7
+// CHECK-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8
+// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8
+// CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8
+// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9
+// CHECK-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
+// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
+// CHECK-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, %struct.S**, i32**, [2 x %struct.S]**, [2 x i32]**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
+// CHECK-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, %struct.S**, i32**, [2 x %struct.S]**, [2 x i32]**, i32**)*
+// CHECK-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [2 x %struct.S]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]
+// CHECK-NEXT: [[TMP26:%.*]] = load %struct.S*, %struct.S** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP28:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP29:%.*]] = load [2 x i32]*, [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR4_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP31]] to i32
+// CHECK-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
+// CHECK: omp.inner.for.cond.i:
+// CHECK-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// CHECK-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP32]] to i64
+// CHECK-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP33]]
+// CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
+// CHECK: omp.inner.for.body.i:
+// CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// CHECK-NEXT: store i32 [[TMP34]], i32* [[I_I]], align 4, !noalias !14
+// CHECK-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP27]], align 4
+// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP29]], i64 0, i64 0
+// CHECK-NEXT: store i32 [[TMP35]], i32* [[ARRAYIDX_I]], align 4
+// CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP28]], i64 0, i64 0
+// CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[ARRAYIDX6_I]] to i8*
+// CHECK-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP26]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP36]], i8* align 8 [[TMP37]], i64 8, i1 false)
+// CHECK-NEXT: store i32 33, i32* [[TMP30]], align 4
+// CHECK-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// CHECK-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP38]], 1
+// CHECK-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]]
+// CHECK: .omp_outlined..1.exit:
+// CHECK-NEXT: ret i32 0
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_dup.
+// CHECK-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP0]], %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTADDR2]], align 4
+// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP5]], i32 0, i32 0
+// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
+// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
+// CHECK-NEXT: [[TMP9:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
+// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP8]], i32 0, i32 0
+// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP9]], i32 0, i32 0
+// CHECK-NEXT: [[TMP12:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[TMP11]], align 8
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP10]], i32 0, i32 0
+// CHECK-NEXT: [[TMP13:%.*]] = bitcast [2 x %struct.S]* [[TMP12]] to %struct.S*
+// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP14]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK: omp.arraycpy.body:
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00)
+// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP14]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK: omp.arraycpy.done3:
+// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP8]], i32 0, i32 1
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP9]], i32 0, i32 1
+// CHECK-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[TMP16]], align 8
+// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP15]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP17]], double noundef 0.000000e+00)
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_destructor.
+// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP2]], i32 0, i32 1
+// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// CHECK: arraydestroy.body:
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK: arraydestroy.done2:
+// CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4
+// CHECK-NEXT: ret i32 [[TMP7]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
+// CHECK-SAME: () #[[ATTR9:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
+// CHECK-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4
+// CHECK-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
+// CHECK-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
+// CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
+// CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
+// CHECK-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]])
+// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0)
+// CHECK-NEXT: store i32 0, i32* [[T_VAR]], align 128
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
+// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
+// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
+// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
+// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
+// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
+// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128
+// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
+// CHECK-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
+// CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]])
+// CHECK-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
+// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// CHECK: arraydestroy.body:
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK: arraydestroy.done1:
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]]
+// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
+// CHECK-NEXT: ret i32 [[TMP4]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: store double 0.000000e+00, double* [[F]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// CHECK-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
+// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8
+// CHECK-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]]
+// CHECK-NEXT: store double [[ADD]], double* [[F]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// CHECK-NEXT: store double [[TMP0]], double* [[F]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// CHECK-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// CHECK-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_outlined..2
+// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
+// CHECK-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
+// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
+// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
+// CHECK-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
+// CHECK-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
+// CHECK-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
+// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
+// CHECK-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
+// CHECK-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
+// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
+// CHECK-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
+// CHECK: omp_if.then:
+// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[AGG_CAPTURED]], i32 0, i32 0
+// CHECK-NEXT: store [2 x %struct.S.0]* [[TMP1]], [2 x %struct.S.0]** [[TMP7]], align 8
+// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[AGG_CAPTURED]], i32 0, i32 1
+// CHECK-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP8]], align 8
+// CHECK-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 9, i64 256, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_entry..5 to i32 (i32, i8*)*))
+// CHECK-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.2*
+// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP10]], i32 0, i32 0
+// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 0
+// CHECK-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 128
+// CHECK-NEXT: [[TMP14:%.*]] = bitcast %struct.anon.1* [[AGG_CAPTURED]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 [[TMP14]], i64 16, i1 false)
+// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP10]], i32 0, i32 2
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 0
+// CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK-NEXT: store i32 [[TMP17]], i32* [[TMP16]], align 128
+// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 1
+// CHECK-NEXT: [[TMP19:%.*]] = bitcast [2 x i32]* [[TMP18]] to i8*
+// CHECK-NEXT: [[TMP20:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 8, i1 false)
+// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 2
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP21]], i32 0, i32 0
+// CHECK-NEXT: [[TMP22:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
+// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP23]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK: omp.arraycpy.body:
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP22]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0)
+// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP23]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK: omp.arraycpy.done1:
+// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 3
+// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP24]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP2]], i32 noundef 0)
+// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 3
+// CHECK-NEXT: [[TMP26:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP25]] to i32 (i32, i8*)**
+// CHECK-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_destructor..7 to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP26]], align 8
+// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 5
+// CHECK-NEXT: store i64 0, i64* [[TMP27]], align 8
+// CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 6
+// CHECK-NEXT: store i64 9, i64* [[TMP28]], align 16
+// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 7
+// CHECK-NEXT: store i64 1, i64* [[TMP29]], align 8
+// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 9
+// CHECK-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i8*
+// CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP31]], i8 0, i64 8, i1 false)
+// CHECK-NEXT: [[TMP32:%.*]] = load i64, i64* [[TMP29]], align 8
+// CHECK-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i8* [[TMP9]], i32 1, i64* [[TMP27]], i64* [[TMP28]], i64 [[TMP32]], i32 1, i32 0, i64 0, i8* bitcast (void (%struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2*, i32)* @.omp_task_dup..6 to i8*))
+// CHECK-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: br label [[OMP_IF_END]]
+// CHECK: omp_if.end:
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_privates_map..4
+// CHECK-SAME: (%struct..kmp_privates.t.3* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], [2 x i32]** noalias noundef [[TMP2:%.*]], [2 x %struct.S.0]** noalias noundef [[TMP3:%.*]], %struct.S.0** noalias noundef [[TMP4:%.*]]) #[[ATTR6]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.3*, align 8
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8
+// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca [2 x i32]**, align 8
+// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca [2 x %struct.S.0]**, align 8
+// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca %struct.S.0**, align 8
+// CHECK-NEXT: store %struct..kmp_privates.t.3* [[TMP0]], %struct..kmp_privates.t.3** [[DOTADDR]], align 8
+// CHECK-NEXT: store i32** [[TMP1]], i32*** [[DOTADDR1]], align 8
+// CHECK-NEXT: store [2 x i32]** [[TMP2]], [2 x i32]*** [[DOTADDR2]], align 8
+// CHECK-NEXT: store [2 x %struct.S.0]** [[TMP3]], [2 x %struct.S.0]*** [[DOTADDR3]], align 8
+// CHECK-NEXT: store %struct.S.0** [[TMP4]], %struct.S.0*** [[DOTADDR4]], align 8
+// CHECK-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t.3*, %struct..kmp_privates.t.3** [[DOTADDR]], align 8
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 0
+// CHECK-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR1]], align 8
+// CHECK-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8
+// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 1
+// CHECK-NEXT: [[TMP9:%.*]] = load [2 x i32]**, [2 x i32]*** [[DOTADDR2]], align 8
+// CHECK-NEXT: store [2 x i32]* [[TMP8]], [2 x i32]** [[TMP9]], align 8
+// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 2
+// CHECK-NEXT: [[TMP11:%.*]] = load [2 x %struct.S.0]**, [2 x %struct.S.0]*** [[DOTADDR3]], align 8
+// CHECK-NEXT: store [2 x %struct.S.0]* [[TMP10]], [2 x %struct.S.0]** [[TMP11]], align 8
+// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 3
+// CHECK-NEXT: [[TMP13:%.*]] = load %struct.S.0**, %struct.S.0*** [[DOTADDR4]], align 8
+// CHECK-NEXT: store %struct.S.0* [[TMP12]], %struct.S.0** [[TMP13]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_entry..5
+// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
+// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.1*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [2 x i32]*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [2 x %struct.S.0]*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[I_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8
+// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
+// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 0
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 128
+// CHECK-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.1*
+// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 2
+// CHECK-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t.3* [[TMP9]] to i8*
+// CHECK-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates.2* [[TMP3]] to i8*
+// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5
+// CHECK-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6
+// CHECK-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 16
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7
+// CHECK-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8
+// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8
+// CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 64
+// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9
+// CHECK-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
+// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !28
+// CHECK-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t.3*, i32**, [2 x i32]**, [2 x %struct.S.0]**, %struct.S.0**)* @.omp_task_privates_map..4 to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !28
+// CHECK-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: [[TMP22:%.*]] = load %struct.anon.1*, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, i32**, [2 x i32]**, [2 x %struct.S.0]**, %struct.S.0**)*
+// CHECK-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], %struct.S.0** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
+// CHECK-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: [[TMP27:%.*]] = load [2 x i32]*, [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !28
+// CHECK-NEXT: [[TMP28:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !28
+// CHECK-NEXT: [[TMP29:%.*]] = load %struct.S.0*, %struct.S.0** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !28
+// CHECK-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP30]] to i32
+// CHECK-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28
+// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
+// CHECK: omp.inner.for.cond.i:
+// CHECK-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !28
+// CHECK-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP31]] to i64
+// CHECK-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !28
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP32]]
+// CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
+// CHECK: omp.inner.for.body.i:
+// CHECK-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !28
+// CHECK-NEXT: store i32 [[TMP33]], i32* [[I_I]], align 4, !noalias !28
+// CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP26]], align 128
+// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP27]], i64 0, i64 0
+// CHECK-NEXT: store i32 [[TMP34]], i32* [[ARRAYIDX_I]], align 4
+// CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP28]], i64 0, i64 0
+// CHECK-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5_I]] to i8*
+// CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false)
+// CHECK-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !28
+// CHECK-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP37]], 1
+// CHECK-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !28
+// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]]
+// CHECK: .omp_outlined..3.exit:
+// CHECK-NEXT: ret i32 0
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_dup..6
+// CHECK-SAME: (%struct.kmp_task_t_with_privates.2* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8
+// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP0]], %struct.kmp_task_t_with_privates.2** [[DOTADDR]], align 8
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTADDR2]], align 4
+// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP5]], i32 0, i32 0
+// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 128
+// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 2
+// CHECK-NEXT: [[TMP9:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.1*
+// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP8]], i32 0, i32 2
+// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], %struct.anon.1* [[TMP9]], i32 0, i32 0
+// CHECK-NEXT: [[TMP12:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[TMP11]], align 8
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP10]], i32 0, i32 0
+// CHECK-NEXT: [[TMP13:%.*]] = bitcast [2 x %struct.S.0]* [[TMP12]] to %struct.S.0*
+// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP14]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK: omp.arraycpy.body:
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0)
+// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP14]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK: omp.arraycpy.done3:
+// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP8]], i32 0, i32 3
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP9]], i32 0, i32 1
+// CHECK-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP16]], align 8
+// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP15]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP17]], i32 noundef 0)
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_destructor..7
+// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8
+// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP2]], i32 0, i32 2
+// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 2
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 3
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// CHECK: arraydestroy.body:
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK: arraydestroy.done2:
+// CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4
+// CHECK-NEXT: ret i32 [[TMP7]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: store i32 0, i32* [[F]], align 4
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// CHECK-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
+// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
+// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
+// CHECK-NEXT: store i32 [[ADD]], i32* [[F]], align 4
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// LAMBDA-LABEL: define {{[^@]+}}@main
+// LAMBDA-SAME: () #[[ATTR0:[0-9]+]] {
+// LAMBDA-NEXT: entry:
+// LAMBDA-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
+// LAMBDA-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// LAMBDA-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
+// LAMBDA-NEXT: ret i32 0
+//
+//
+// LAMBDA-LABEL: define {{[^@]+}}@.omp_outlined.
+// LAMBDA-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] {
+// LAMBDA-NEXT: entry:
+// LAMBDA-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
+// LAMBDA-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
+// LAMBDA-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
+// LAMBDA-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// LAMBDA-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
+// LAMBDA-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// LAMBDA-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
+// LAMBDA-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]])
+// LAMBDA-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
+// LAMBDA-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
+// LAMBDA: omp_if.then:
+// LAMBDA-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// LAMBDA-NEXT: [[TMP4:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 96, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
+// LAMBDA-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.kmp_task_t_with_privates*
+// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 0
+// LAMBDA-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 1
+// LAMBDA-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 0
+// LAMBDA-NEXT: [[TMP9:%.*]] = load volatile double, double* @g, align 8
+// LAMBDA-NEXT: store volatile double [[TMP9]], double* [[TMP8]], align 8
+// LAMBDA-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 1
+// LAMBDA-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
+// LAMBDA-NEXT: store i32 [[TMP11]], i32* [[TMP10]], align 8
+// LAMBDA-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 5
+// LAMBDA-NEXT: store i64 0, i64* [[TMP12]], align 8
+// LAMBDA-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 6
+// LAMBDA-NEXT: store i64 9, i64* [[TMP13]], align 8
+// LAMBDA-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 7
+// LAMBDA-NEXT: store i64 1, i64* [[TMP14]], align 8
+// LAMBDA-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 9
+// LAMBDA-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i8*
+// LAMBDA-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP16]], i8 0, i64 8, i1 false)
+// LAMBDA-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP14]], align 8
+// LAMBDA-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP4]], i32 1, i64* [[TMP12]], i64* [[TMP13]], i64 [[TMP17]], i32 1, i32 0, i64 0, i8* null)
+// LAMBDA-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// LAMBDA-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// LAMBDA-NEXT: br label [[OMP_IF_END]]
+// LAMBDA: omp_if.end:
+// LAMBDA-NEXT: ret void
+//
+//
+// LAMBDA-LABEL: define {{[^@]+}}@.omp_task_privates_map.
+// LAMBDA-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] {
+// LAMBDA-NEXT: entry:
+// LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
+// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8
+// LAMBDA-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8
+// LAMBDA-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
+// LAMBDA-NEXT: store double** [[TMP1]], double*** [[DOTADDR1]], align 8
+// LAMBDA-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8
+// LAMBDA-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
+// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0
+// LAMBDA-NEXT: [[TMP5:%.*]] = load double**, double*** [[DOTADDR1]], align 8
+// LAMBDA-NEXT: store double* [[TMP4]], double** [[TMP5]], align 8
+// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1
+// LAMBDA-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8
+// LAMBDA-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8
+// LAMBDA-NEXT: ret void
+//
+//
+// LAMBDA-LABEL: define {{[^@]+}}@.omp_task_entry.
+// LAMBDA-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
+// LAMBDA-NEXT: entry:
+// LAMBDA-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
+// LAMBDA-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
+// LAMBDA-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
+// LAMBDA-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
+// LAMBDA-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
+// LAMBDA-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
+// LAMBDA-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
+// LAMBDA-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8
+// LAMBDA-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
+// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca double*, align 8
+// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8
+// LAMBDA-NEXT: [[I_I:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[REF_TMP_I:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
+// LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// LAMBDA-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// LAMBDA-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// LAMBDA-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
+// LAMBDA-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
+// LAMBDA-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
+// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
+// LAMBDA-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
+// LAMBDA-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
+// LAMBDA-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
+// LAMBDA-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
+// LAMBDA-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
+// LAMBDA-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5
+// LAMBDA-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8
+// LAMBDA-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6
+// LAMBDA-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8
+// LAMBDA-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7
+// LAMBDA-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8
+// LAMBDA-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8
+// LAMBDA-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8
+// LAMBDA-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9
+// LAMBDA-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8
+// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
+// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
+// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
+// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
+// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
+// LAMBDA-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
+// LAMBDA-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, double**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
+// LAMBDA-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, double**, i32**)*
+// LAMBDA-NEXT: call void [[TMP25]](i8* [[TMP24]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]]
+// LAMBDA-NEXT: [[TMP26:%.*]] = load double*, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP28]] to i32
+// LAMBDA-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
+// LAMBDA: omp.inner.for.cond.i:
+// LAMBDA-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// LAMBDA-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP29]] to i64
+// LAMBDA-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP30]]
+// LAMBDA-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
+// LAMBDA: omp.inner.for.body.i:
+// LAMBDA-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// LAMBDA-NEXT: store i32 [[TMP31]], i32* [[I_I]], align 4, !noalias !14
+// LAMBDA-NEXT: store double 1.000000e+00, double* [[TMP26]], align 8
+// LAMBDA-NEXT: store i32 11, i32* [[TMP27]], align 4
+// LAMBDA-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP_I]], i32 0, i32 0
+// LAMBDA-NEXT: store double* [[TMP26]], double** [[TMP32]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP_I]], i32 0, i32 1
+// LAMBDA-NEXT: store i32* [[TMP27]], i32** [[TMP33]], align 8, !noalias !14
+// LAMBDA-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]])
+// LAMBDA-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// LAMBDA-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP34]], 1
+// LAMBDA-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I]]
+// LAMBDA: .omp_outlined..1.exit:
+// LAMBDA-NEXT: ret i32 0
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@main
+// BLOCKS-SAME: () #[[ATTR1:[0-9]+]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// BLOCKS-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8
+// BLOCKS-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)*
+// BLOCKS-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*))
+// BLOCKS-NEXT: ret i32 0
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@__main_block_invoke
+// BLOCKS-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
+// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
+// BLOCKS-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
+// BLOCKS-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
+// BLOCKS-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
+// BLOCKS-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
+// BLOCKS-NEXT: ret void
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@.omp_outlined.
+// BLOCKS-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
+// BLOCKS-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
+// BLOCKS-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
+// BLOCKS-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// BLOCKS-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
+// BLOCKS-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// BLOCKS-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
+// BLOCKS-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// BLOCKS-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
+// BLOCKS-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
+// BLOCKS: omp_if.then:
+// BLOCKS-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// BLOCKS-NEXT: [[TMP4:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 96, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
+// BLOCKS-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.kmp_task_t_with_privates*
+// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 0
+// BLOCKS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 1
+// BLOCKS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 0
+// BLOCKS-NEXT: [[TMP9:%.*]] = load volatile double, double* @g, align 8
+// BLOCKS-NEXT: store volatile double [[TMP9]], double* [[TMP8]], align 8
+// BLOCKS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 1
+// BLOCKS-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
+// BLOCKS-NEXT: store i32 [[TMP11]], i32* [[TMP10]], align 8
+// BLOCKS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 5
+// BLOCKS-NEXT: store i64 0, i64* [[TMP12]], align 8
+// BLOCKS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 6
+// BLOCKS-NEXT: store i64 9, i64* [[TMP13]], align 8
+// BLOCKS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 7
+// BLOCKS-NEXT: store i64 1, i64* [[TMP14]], align 8
+// BLOCKS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 9
+// BLOCKS-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i8*
+// BLOCKS-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP16]], i8 0, i64 8, i1 false)
+// BLOCKS-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP14]], align 8
+// BLOCKS-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP4]], i32 1, i64* [[TMP12]], i64* [[TMP13]], i64 [[TMP17]], i32 1, i32 0, i64 0, i8* null)
+// BLOCKS-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// BLOCKS-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// BLOCKS-NEXT: br label [[OMP_IF_END]]
+// BLOCKS: omp_if.end:
+// BLOCKS-NEXT: ret void
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@_block_invoke
+// BLOCKS-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
+// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8
+// BLOCKS-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
+// BLOCKS-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*
+// BLOCKS-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8
+// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5
+// BLOCKS-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8
+// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6
+// BLOCKS-NEXT: store i32 22, i32* [[BLOCK_CAPTURE_ADDR1]], align 8
+// BLOCKS-NEXT: ret void
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@.omp_task_privates_map.
+// BLOCKS-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
+// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8
+// BLOCKS-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8
+// BLOCKS-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
+// BLOCKS-NEXT: store double** [[TMP1]], double*** [[DOTADDR1]], align 8
+// BLOCKS-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8
+// BLOCKS-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
+// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0
+// BLOCKS-NEXT: [[TMP5:%.*]] = load double**, double*** [[DOTADDR1]], align 8
+// BLOCKS-NEXT: store double* [[TMP4]], double** [[TMP5]], align 8
+// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1
+// BLOCKS-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8
+// BLOCKS-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8
+// BLOCKS-NEXT: ret void
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@.omp_task_entry.
+// BLOCKS-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
+// BLOCKS-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
+// BLOCKS-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
+// BLOCKS-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
+// BLOCKS-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
+// BLOCKS-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
+// BLOCKS-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
+// BLOCKS-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8
+// BLOCKS-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
+// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca double*, align 8
+// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8
+// BLOCKS-NEXT: [[I_I:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: [[BLOCK_I:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8
+// BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// BLOCKS-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// BLOCKS-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// BLOCKS-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
+// BLOCKS-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
+// BLOCKS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
+// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
+// BLOCKS-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
+// BLOCKS-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
+// BLOCKS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
+// BLOCKS-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
+// BLOCKS-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
+// BLOCKS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5
+// BLOCKS-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8
+// BLOCKS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6
+// BLOCKS-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8
+// BLOCKS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7
+// BLOCKS-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8
+// BLOCKS-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8
+// BLOCKS-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8
+// BLOCKS-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9
+// BLOCKS-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8
+// BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
+// BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
+// BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
+// BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
+// BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
+// BLOCKS-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
+// BLOCKS-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, double**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
+// BLOCKS-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, double**, i32**)*
+// BLOCKS-NEXT: call void [[TMP25]](i8* [[TMP24]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]]
+// BLOCKS-NEXT: [[TMP26:%.*]] = load double*, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP28]] to i32
+// BLOCKS-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// BLOCKS-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
+// BLOCKS: omp.inner.for.cond.i:
+// BLOCKS-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// BLOCKS-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP29]] to i64
+// BLOCKS-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP30]]
+// BLOCKS-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
+// BLOCKS: omp.inner.for.body.i:
+// BLOCKS-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// BLOCKS-NEXT: store i32 [[TMP31]], i32* [[I_I]], align 4, !noalias !14
+// BLOCKS-NEXT: store double 1.000000e+00, double* [[TMP26]], align 8
+// BLOCKS-NEXT: store i32 11, i32* [[TMP27]], align 4
+// BLOCKS-NEXT: [[BLOCK_ISA_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 0
+// BLOCKS-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[BLOCK_FLAGS_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 1
+// BLOCKS-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[BLOCK_RESERVED_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 2
+// BLOCKS-NEXT: store i32 0, i32* [[BLOCK_RESERVED_I]], align 4, !noalias !14
+// BLOCKS-NEXT: [[BLOCK_INVOKE_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 3
+// BLOCKS-NEXT: store i8* bitcast (void (i8*)* @_block_invoke to i8*), i8** [[BLOCK_INVOKE_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[BLOCK_DESCRIPTOR_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 4
+// BLOCKS-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[BLOCK_CAPTURED_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 5
+// BLOCKS-NEXT: [[TMP32:%.*]] = load volatile double, double* [[TMP26]], align 8
+// BLOCKS-NEXT: store volatile double [[TMP32]], double* [[BLOCK_CAPTURED_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[BLOCK_CAPTURED3_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 6
+// BLOCKS-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP27]], align 4
+// BLOCKS-NEXT: store i32 [[TMP33]], i32* [[BLOCK_CAPTURED3_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP34:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]] to void ()*
+// BLOCKS-NEXT: [[BLOCK_LITERAL_I:%.*]] = bitcast void ()* [[TMP34]] to %struct.__block_literal_generic*
+// BLOCKS-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL_I]], i32 0, i32 3
+// BLOCKS-NEXT: [[TMP36:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL_I]] to i8*
+// BLOCKS-NEXT: [[TMP37:%.*]] = load i8*, i8** [[TMP35]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP38:%.*]] = bitcast i8* [[TMP37]] to void (i8*)*
+// BLOCKS-NEXT: call void [[TMP38]](i8* noundef [[TMP36]]) #[[ATTR4]]
+// BLOCKS-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// BLOCKS-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP39]], 1
+// BLOCKS-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// BLOCKS-NEXT: br label [[OMP_INNER_FOR_COND_I]]
+// BLOCKS: .omp_outlined..1.exit:
+// BLOCKS-NEXT: ret i32 0
+//
+//
+// ARRAY-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St
+// ARRAY-SAME: (i32 noundef [[N:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] {
+// ARRAY-NEXT: entry:
+// ARRAY-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
+// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8
+// ARRAY-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// ARRAY-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
+// ARRAY-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8
+// ARRAY-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// ARRAY-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// ARRAY-NEXT: [[TMP2:%.*]] = load float*, float** [[A_ADDR]], align 8
+// ARRAY-NEXT: [[TMP3:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8
+// ARRAY-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, float*, %struct.St*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], float* [[TMP2]], %struct.St* [[TMP3]])
+// ARRAY-NEXT: ret void
+//
+//
+// ARRAY-LABEL: define {{[^@]+}}@.omp_outlined.
+// ARRAY-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR1:[0-9]+]] {
+// ARRAY-NEXT: entry:
+// ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
+// ARRAY-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
+// ARRAY-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
+// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8
+// ARRAY-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
+// ARRAY-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// ARRAY-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
+// ARRAY-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// ARRAY-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
+// ARRAY-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8
+// ARRAY-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// ARRAY-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// ARRAY-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
+// ARRAY-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
+// ARRAY-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
+// ARRAY-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
+// ARRAY: omp_if.then:
+// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
+// ARRAY-NEXT: store i64 [[TMP0]], i64* [[TMP5]], align 8
+// ARRAY-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
+// ARRAY-NEXT: [[TMP6:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i64 96, i64 8, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
+// ARRAY-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to %struct.kmp_task_t_with_privates*
+// ARRAY-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP7]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
+// ARRAY-NEXT: [[TMP11:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
+// ARRAY-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 [[TMP11]], i64 8, i1 false)
+// ARRAY-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP7]], i32 0, i32 1
+// ARRAY-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP12]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8
+// ARRAY-NEXT: store float* [[TMP14]], float** [[TMP13]], align 8
+// ARRAY-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP12]], i32 0, i32 1
+// ARRAY-NEXT: [[TMP16:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8
+// ARRAY-NEXT: store %struct.St* [[TMP16]], %struct.St** [[TMP15]], align 8
+// ARRAY-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 5
+// ARRAY-NEXT: store i64 0, i64* [[TMP17]], align 8
+// ARRAY-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 6
+// ARRAY-NEXT: store i64 9, i64* [[TMP18]], align 8
+// ARRAY-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 7
+// ARRAY-NEXT: store i64 1, i64* [[TMP19]], align 8
+// ARRAY-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 9
+// ARRAY-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i8*
+// ARRAY-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP21]], i8 0, i64 8, i1 false)
+// ARRAY-NEXT: [[TMP22:%.*]] = load i64, i64* [[TMP19]], align 8
+// ARRAY-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i8* [[TMP6]], i32 1, i64* [[TMP17]], i64* [[TMP18]], i64 [[TMP22]], i32 1, i32 0, i64 0, i8* null)
+// ARRAY-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
+// ARRAY-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
+// ARRAY-NEXT: br label [[OMP_IF_END]]
+// ARRAY: omp_if.end:
+// ARRAY-NEXT: ret void
+//
+//
+// ARRAY-LABEL: define {{[^@]+}}@.omp_task_privates_map.
+// ARRAY-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], float*** noalias noundef [[TMP1:%.*]], %struct.St*** noalias noundef [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] {
+// ARRAY-NEXT: entry:
+// ARRAY-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
+// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca float***, align 8
+// ARRAY-NEXT: [[DOTADDR2:%.*]] = alloca %struct.St***, align 8
+// ARRAY-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
+// ARRAY-NEXT: store float*** [[TMP1]], float**** [[DOTADDR1]], align 8
+// ARRAY-NEXT: store %struct.St*** [[TMP2]], %struct.St**** [[DOTADDR2]], align 8
+// ARRAY-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
+// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP5:%.*]] = load float***, float**** [[DOTADDR1]], align 8
+// ARRAY-NEXT: store float** [[TMP4]], float*** [[TMP5]], align 8
+// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1
+// ARRAY-NEXT: [[TMP7:%.*]] = load %struct.St***, %struct.St**** [[DOTADDR2]], align 8
+// ARRAY-NEXT: store %struct.St** [[TMP6]], %struct.St*** [[TMP7]], align 8
+// ARRAY-NEXT: ret void
+//
+//
+// ARRAY-LABEL: define {{[^@]+}}@.omp_task_entry.
+// ARRAY-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
+// ARRAY-NEXT: entry:
+// ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
+// ARRAY-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
+// ARRAY-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
+// ARRAY-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
+// ARRAY-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
+// ARRAY-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
+// ARRAY-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
+// ARRAY-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8
+// ARRAY-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
+// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca float**, align 8
+// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca %struct.St**, align 8
+// ARRAY-NEXT: [[I_I:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// ARRAY-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// ARRAY-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// ARRAY-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
+// ARRAY-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
+// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
+// ARRAY-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
+// ARRAY-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
+// ARRAY-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
+// ARRAY-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
+// ARRAY-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5
+// ARRAY-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8
+// ARRAY-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6
+// ARRAY-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8
+// ARRAY-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7
+// ARRAY-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8
+// ARRAY-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8
+// ARRAY-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8
+// ARRAY-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9
+// ARRAY-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8
+// ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
+// ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
+// ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
+// ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
+// ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
+// ARRAY-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
+// ARRAY-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, float***, %struct.St***)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
+// ARRAY-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP22]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP24:%.*]] = load i64, i64* [[TMP23]], align 8
+// ARRAY-NEXT: [[TMP25:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP26:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP27:%.*]] = bitcast void (i8*, ...)* [[TMP25]] to void (i8*, float***, %struct.St***)*
+// ARRAY-NEXT: call void [[TMP27]](i8* [[TMP26]], float*** [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.St*** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]]
+// ARRAY-NEXT: [[TMP28:%.*]] = load float**, float*** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP29:%.*]] = load %struct.St**, %struct.St*** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP30]] to i32
+// ARRAY-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// ARRAY-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
+// ARRAY: omp.inner.for.cond.i:
+// ARRAY-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// ARRAY-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP31]] to i64
+// ARRAY-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP32]]
+// ARRAY-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
+// ARRAY: omp.inner.for.body.i:
+// ARRAY-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// ARRAY-NEXT: store i32 [[TMP33]], i32* [[I_I]], align 4, !noalias !14
+// ARRAY-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// ARRAY-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP34]], 1
+// ARRAY-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// ARRAY-NEXT: br label [[OMP_INNER_FOR_COND_I]]
+// ARRAY: .omp_outlined..1.exit:
+// ARRAY-NEXT: ret i32 0
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@main
+// SIMD-ONLY0-SAME: () #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8
+// SIMD-ONLY0-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8
+// SIMD-ONLY0-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16
+// SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8
+// SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]])
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00)
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[T_VAR]], align 4
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false)
+// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00)
+// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00)
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00)
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[I]], align 4
+// SIMD-ONLY0-NEXT: br label [[FOR_COND:%.*]]
+// SIMD-ONLY0: for.cond:
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10
+// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// SIMD-ONLY0: for.body:
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
+// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
+// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[VAR]] to i8*
+// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false)
+// SIMD-ONLY0-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4
+// SIMD-ONLY0-NEXT: br label [[FOR_INC:%.*]]
+// SIMD-ONLY0: for.inc:
+// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY0-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1
+// SIMD-ONLY0-NEXT: store i32 [[INC]], i32* [[I]], align 4
+// SIMD-ONLY0-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
+// SIMD-ONLY0: for.end:
+// SIMD-ONLY0-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
+// SIMD-ONLY0-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]]
+// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// SIMD-ONLY0: arraydestroy.body:
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
+// SIMD-ONLY0: arraydestroy.done2:
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4
+// SIMD-ONLY0-NEXT: ret i32 [[TMP7]]
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
+// SIMD-ONLY0-SAME: () #[[ATTR3:[0-9]+]] {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
+// SIMD-ONLY0-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4
+// SIMD-ONLY0-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
+// SIMD-ONLY0-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
+// SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
+// SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]])
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0)
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[T_VAR]], align 128
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
+// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
+// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[I]], align 4
+// SIMD-ONLY0-NEXT: br label [[FOR_COND:%.*]]
+// SIMD-ONLY0: for.cond:
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10
+// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// SIMD-ONLY0: for.body:
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 128
+// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8*
+// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[VAR]] to i8*
+// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 4, i1 false)
+// SIMD-ONLY0-NEXT: br label [[FOR_INC:%.*]]
+// SIMD-ONLY0: for.inc:
+// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY0-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1
+// SIMD-ONLY0-NEXT: store i32 [[INC]], i32* [[I]], align 4
+// SIMD-ONLY0-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
+// SIMD-ONLY0: for.end:
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// SIMD-ONLY0: arraydestroy.body:
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
+// SIMD-ONLY0: arraydestroy.done2:
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4
+// SIMD-ONLY0-NEXT: ret i32 [[TMP7]]
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: store double 0.000000e+00, double* [[F]], align 8
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]]
+// SIMD-ONLY0-NEXT: store double [[ADD]], double* [[F]], align 8
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP0]], double* [[F]], align 8
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[F]], align 4
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
+// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[F]], align 4
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// SIMD-ONLY0-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@main
+// SIMD-ONLY1-SAME: () #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8
+// SIMD-ONLY1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8
+// SIMD-ONLY1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16
+// SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8
+// SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]])
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00)
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[T_VAR]], align 4
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false)
+// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00)
+// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00)
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00)
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[I]], align 4
+// SIMD-ONLY1-NEXT: br label [[FOR_COND:%.*]]
+// SIMD-ONLY1: for.cond:
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10
+// SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// SIMD-ONLY1: for.body:
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4
+// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8*
+// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[VAR]] to i8*
+// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false)
+// SIMD-ONLY1-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4
+// SIMD-ONLY1-NEXT: br label [[FOR_INC:%.*]]
+// SIMD-ONLY1: for.inc:
+// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1
+// SIMD-ONLY1-NEXT: store i32 [[INC]], i32* [[I]], align 4
+// SIMD-ONLY1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
+// SIMD-ONLY1: for.end:
+// SIMD-ONLY1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
+// SIMD-ONLY1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]]
+// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// SIMD-ONLY1: arraydestroy.body:
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
+// SIMD-ONLY1: arraydestroy.done2:
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4
+// SIMD-ONLY1-NEXT: ret i32 [[TMP7]]
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
+// SIMD-ONLY1-SAME: () #[[ATTR3:[0-9]+]] {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
+// SIMD-ONLY1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4
+// SIMD-ONLY1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
+// SIMD-ONLY1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
+// SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
+// SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]])
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0)
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[T_VAR]], align 128
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
+// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
+// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[I]], align 4
+// SIMD-ONLY1-NEXT: br label [[FOR_COND:%.*]]
+// SIMD-ONLY1: for.cond:
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], 10
+// SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// SIMD-ONLY1: for.body:
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 128
+// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8*
+// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[VAR]] to i8*
+// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 4, i1 false)
+// SIMD-ONLY1-NEXT: br label [[FOR_INC:%.*]]
+// SIMD-ONLY1: for.inc:
+// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1
+// SIMD-ONLY1-NEXT: store i32 [[INC]], i32* [[I]], align 4
+// SIMD-ONLY1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
+// SIMD-ONLY1: for.end:
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// SIMD-ONLY1: arraydestroy.body:
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
+// SIMD-ONLY1: arraydestroy.done2:
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4
+// SIMD-ONLY1-NEXT: ret i32 [[TMP7]]
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: store double 0.000000e+00, double* [[F]], align 8
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]]
+// SIMD-ONLY1-NEXT: store double [[ADD]], double* [[F]], align 8
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store double [[TMP0]], double* [[F]], align 8
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[F]], align 4
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
+// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// SIMD-ONLY1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY2-LABEL: define {{[^@]+}}@main
+// SIMD-ONLY2-SAME: () #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY2-NEXT: entry:
+// SIMD-ONLY2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
+// SIMD-ONLY2-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
+// SIMD-ONLY2-NEXT: ret i32 0
+//
+//
+// SIMD-ONLY3-LABEL: define {{[^@]+}}@main
+// SIMD-ONLY3-SAME: () #[[ATTR1:[0-9]+]] {
+// SIMD-ONLY3-NEXT: entry:
+// SIMD-ONLY3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY3-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8
+// SIMD-ONLY3-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)*
+// SIMD-ONLY3-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*))
+// SIMD-ONLY3-NEXT: ret i32 0
+//
+//
+// SIMD-ONLY3-LABEL: define {{[^@]+}}@__main_block_invoke
+// SIMD-ONLY3-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
+// SIMD-ONLY3-NEXT: entry:
+// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
+// SIMD-ONLY3-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY3-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8
+// SIMD-ONLY3-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
+// SIMD-ONLY3-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
+// SIMD-ONLY3-NEXT: store i32 0, i32* [[I]], align 4
+// SIMD-ONLY3-NEXT: br label [[FOR_COND:%.*]]
+// SIMD-ONLY3: for.cond:
+// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
+// SIMD-ONLY3-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// SIMD-ONLY3: for.body:
+// SIMD-ONLY3-NEXT: store double 1.000000e+00, double* @g, align 8
+// SIMD-ONLY3-NEXT: store i32 11, i32* @_ZZ4mainE5sivar, align 4
+// SIMD-ONLY3-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 0
+// SIMD-ONLY3-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 1
+// SIMD-ONLY3-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 2
+// SIMD-ONLY3-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4
+// SIMD-ONLY3-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 3
+// SIMD-ONLY3-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 4
+// SIMD-ONLY3-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 5
+// SIMD-ONLY3-NEXT: [[TMP1:%.*]] = load volatile double, double* @g, align 8
+// SIMD-ONLY3-NEXT: store volatile double [[TMP1]], double* [[BLOCK_CAPTURED]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]], i32 0, i32 6
+// SIMD-ONLY3-NEXT: [[TMP2:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
+// SIMD-ONLY3-NEXT: store i32 [[TMP2]], i32* [[BLOCK_CAPTURED2]], align 8
+// SIMD-ONLY3-NEXT: [[TMP3:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK1]] to void ()*
+// SIMD-ONLY3-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP3]] to %struct.__block_literal_generic*
+// SIMD-ONLY3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
+// SIMD-ONLY3-NEXT: [[TMP5:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
+// SIMD-ONLY3-NEXT: [[TMP6:%.*]] = load i8*, i8** [[TMP4]], align 8
+// SIMD-ONLY3-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to void (i8*)*
+// SIMD-ONLY3-NEXT: call void [[TMP7]](i8* noundef [[TMP5]])
+// SIMD-ONLY3-NEXT: br label [[FOR_INC:%.*]]
+// SIMD-ONLY3: for.inc:
+// SIMD-ONLY3-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1
+// SIMD-ONLY3-NEXT: store i32 [[INC]], i32* [[I]], align 4
+// SIMD-ONLY3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
+// SIMD-ONLY3: for.end:
+// SIMD-ONLY3-NEXT: ret void
+//
+//
+// SIMD-ONLY3-LABEL: define {{[^@]+}}@__main_block_invoke_2
+// SIMD-ONLY3-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
+// SIMD-ONLY3-NEXT: entry:
+// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8
+// SIMD-ONLY3-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*
+// SIMD-ONLY3-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5
+// SIMD-ONLY3-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6
+// SIMD-ONLY3-NEXT: store i32 22, i32* [[BLOCK_CAPTURE_ADDR1]], align 8
+// SIMD-ONLY3-NEXT: ret void
+//
+//
+// SIMD-ONLY4-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St
+// SIMD-ONLY4-SAME: (i32 noundef [[N:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY4-NEXT: entry:
+// SIMD-ONLY4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
+// SIMD-ONLY4-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8
+// SIMD-ONLY4-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
+// SIMD-ONLY4-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8
+// SIMD-ONLY4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// SIMD-ONLY4-NEXT: store i32 0, i32* [[I]], align 4
+// SIMD-ONLY4-NEXT: br label [[FOR_COND:%.*]]
+// SIMD-ONLY4: for.cond:
+// SIMD-ONLY4-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY4-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 10
+// SIMD-ONLY4-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// SIMD-ONLY4: for.body:
+// SIMD-ONLY4-NEXT: br label [[FOR_INC:%.*]]
+// SIMD-ONLY4: for.inc:
+// SIMD-ONLY4-NEXT: [[TMP3:%.*]] = load i32, i32* [[I]], align 4
+// SIMD-ONLY4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP3]], 1
+// SIMD-ONLY4-NEXT: store i32 [[INC]], i32* [[I]], align 4
+// SIMD-ONLY4-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
+// SIMD-ONLY4: for.end:
+// SIMD-ONLY4-NEXT: ret void
+//
diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp
index f4ded3c7797e9..31e610d0ddffa 100644
--- a/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp
@@ -1,3 +1,4 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
@@ -7,11 +8,10 @@
// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s
-// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}
+// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY2 %s
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY3 %s
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY4 %s
// expected-no-diagnostics
#ifndef ARRAY
@@ -30,15 +30,6 @@ struct S {
volatile double g;
-// CHECK-DAG: [[KMP_TASK_T_TY:%.+]] = type { i8*, i32 (i32, i8*)*, i32, %union{{.+}}, %union{{.+}}, i64, i64, i64, i32, i8* }
-// CHECK-DAG: [[S_DOUBLE_TY:%.+]] = type { double }
-// CHECK-DAG: [[PRIVATES_MAIN_TY:%.+]] = type {{.?}}{ [2 x [[S_DOUBLE_TY]]], [[S_DOUBLE_TY]], i32, [2 x i32]
-// CHECK-DAG: [[CAP_MAIN_TY:%.+]] = type { [2 x [[S_DOUBLE_TY]]]*, [[S_DOUBLE_TY]]* }
-// CHECK-DAG: [[KMP_TASK_MAIN_TY:%.+]] = type { [[KMP_TASK_T_TY]], [[PRIVATES_MAIN_TY]] }
-// CHECK-DAG: [[S_INT_TY:%.+]] = type { i32 }
-// CHECK-DAG: [[CAP_TMAIN_TY:%.+]] = type { [2 x [[S_INT_TY]]]*, [[S_INT_TY]]* }
-// CHECK-DAG: [[PRIVATES_TMAIN_TY:%.+]] = type { i32, [2 x i32], [2 x [[S_INT_TY]]], [[S_INT_TY]], [104 x i8] }
-// CHECK-DAG: [[KMP_TASK_TMAIN_TY:%.+]] = type { [[KMP_TASK_T_TY]], [{{[0-9]+}} x i8], [[PRIVATES_TMAIN_TY]] }
template <typename T>
T tmain() {
S<T> ttt;
@@ -58,48 +49,14 @@ T tmain() {
int main() {
static int sivar;
#ifdef LAMBDA
- // LAMBDA: [[G:@.+]] ={{.*}} global double
- // LAMBDA: [[SIVAR:@.+]] = internal global i{{[0-9]+}} 0,
- // LAMBDA-LABEL: @main
- // LAMBDA: call{{( x86_thiscallcc)?}} void [[OUTER_LAMBDA:@.+]](
[&]() {
- // LAMBDA: define{{.*}} internal{{.*}} void [[OUTER_LAMBDA]](
-// LAMBDA: [[RES:%.+]] = call {{.*}}i32 @__kmpc_master(
-// LAMBDA-NEXT: [[IS_MASTER:%.+]] = icmp ne i32 [[RES]], 0
-// LAMBDA-NEXT: br i1 [[IS_MASTER]], label {{%?}}[[THEN:.+]], label {{%?}}[[EXIT:.+]]
-// LAMBDA: [[THEN]]
-// LAMBDA: [[RES:%.+]] = call i8* @__kmpc_omp_task_alloc(%{{[^ ]+}} @{{[^,]+}}, i32 %{{[^,]+}}, i32 1, i64 96, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %{{[^*]+}}*)* [[TASK_ENTRY:@[^ ]+]] to i32 (i32, i8*)*))
-// LAMBDA: [[PRIVATES:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i{{.+}} 0, i{{.+}} 1
-// LAMBDA: [[G_PRIVATE_ADDR:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0
-// LAMBDA: [[G_VAL:%.+]] = load volatile double, double* @{{.+}},
-// LAMBDA: store volatile double [[G_VAL]], double* [[G_PRIVATE_ADDR]]
-
-// LAMBDA: [[SIVAR_PRIVATE_ADDR:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1
-// LAMBDA: [[SIVAR_VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* @{{.+}},
-// LAMBDA: store i{{[0-9]+}} [[SIVAR_VAL]], i{{[0-9]+}}* [[SIVAR_PRIVATE_ADDR]]
-
-// LAMBDA: call void @__kmpc_taskloop(%{{.+}}* @{{.+}}, i32 %{{.+}}, i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* null)
-// LAMBDA: call {{.*}}void @__kmpc_end_master(
-// LAMBDA-NEXT: br label {{%?}}[[EXIT]]
-// LAMBDA: [[EXIT]]
-// LAMBDA: ret
+
+
#pragma omp parallel master taskloop simd firstprivate(g, sivar)
for (int i = 0; i < 10; ++i) {
- // LAMBDA: define {{.+}} void [[INNER_LAMBDA:@.+]](%{{.+}}* {{[^,]*}} [[ARG_PTR:%.+]])
- // LAMBDA: store %{{.+}}* [[ARG_PTR]], %{{.+}}** [[ARG_PTR_REF:%.+]],
- // LAMBDA: [[ARG_PTR:%.+]] = load %{{.+}}*, %{{.+}}** [[ARG_PTR_REF]]
- // LAMBDA: [[G_PTR_REF:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[ARG_PTR]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // LAMBDA: [[G_REF:%.+]] = load double*, double** [[G_PTR_REF]]
- // LAMBDA: store double 2.0{{.+}}, double* [[G_REF]]
-
- // LAMBDA: store double* %{{.+}}, double** %{{.+}},
- // LAMBDA: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1)
+
g = 1;
sivar = 11;
- // LAMBDA: store double 1.0{{.+}}, double* %{{.+}},
- // LAMBDA: store i{{[0-9]+}} 11, i{{[0-9]+}}* %{{.+}},
- // LAMBDA: call void [[INNER_LAMBDA]](%
- // LAMBDA: ret
[&]() {
g = 2;
sivar = 22;
@@ -108,51 +65,13 @@ int main() {
}();
return 0;
#elif defined(BLOCKS)
- // BLOCKS: [[G:@.+]] ={{.*}} global double
- // BLOCKS: [[SIVAR:@.+]] = internal global i{{[0-9]+}} 0,
- // BLOCKS-LABEL: @main
- // BLOCKS: call void {{%.+}}(i8
^{
- // BLOCKS: define{{.*}} internal{{.*}} void {{.+}}(i8*
- // BLOCKS: [[RES:%.+]] = call {{.*}}i32 @__kmpc_master(
- // BLOCKS-NEXT: [[IS_MASTER:%.+]] = icmp ne i32 [[RES]], 0
- // BLOCKS-NEXT: br i1 [[IS_MASTER]], label {{%?}}[[THEN:.+]], label {{%?}}[[EXIT:.+]]
- // BLOCKS: [[THEN]]
- // BLOCKS: [[RES:%.+]] = call i8* @__kmpc_omp_task_alloc(%{{[^ ]+}} @{{[^,]+}}, i32 %{{[^,]+}}, i32 1, i64 96, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %{{[^*]+}}*)* [[TASK_ENTRY:@[^ ]+]] to i32 (i32, i8*)*))
- // BLOCKS: [[PRIVATES:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i{{.+}} 0, i{{.+}} 1
- // BLOCKS: [[G_PRIVATE_ADDR:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0
- // BLOCKS: [[G_VAL:%.+]] = load volatile double, double* @{{.+}},
- // BLOCKS: store volatile double [[G_VAL]], double* [[G_PRIVATE_ADDR]]
-
- // BLOCKS: [[SIVAR_PRIVATE_ADDR:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1
- // BLOCKS: [[SIVAR_VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* @{{.+}},
- // BLOCKS: store i{{[0-9]+}} [[SIVAR_VAL]], i{{[0-9]+}}* [[SIVAR_PRIVATE_ADDR]]
- // BLOCKS: call void @__kmpc_taskloop(%{{.+}}* @{{.+}}, i32 %{{.+}}, i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* null)
- // BLOCKS: call {{.*}}void @__kmpc_end_master(
- // BLOCKS-NEXT: br label {{%?}}[[EXIT]]
- // BLOCKS: [[EXIT]]
- // BLOCKS: ret
+
#pragma omp parallel master taskloop simd firstprivate(g, sivar)
for (int i = 0; i < 10; ++i) {
- // BLOCKS: define {{.+}} void {{@.+}}(i8*
- // BLOCKS-NOT: [[G]]{{[[^:word:]]}}
- // BLOCKS: store double 2.0{{.+}}, double*
- // BLOCKS-NOT: [[G]]{{[[^:word:]]}}
- // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}}
- // BLOCKS: store i{{[0-9]+}} 22, i{{[0-9]+}}*
- // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}}
- // BLOCKS: ret
-
- // BLOCKS: store double* %{{.+}}, double** %{{.+}},
- // BLOCKS: store i{{[0-9]+}}* %{{.+}}, i{{[0-9]+}}** %{{.+}},
- // BLOCKS: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, %{{.+}}* noalias noundef %1)
+
g = 1;
sivar = 11;
- // BLOCKS: store double 1.0{{.+}}, double* %{{.+}},
- // BLOCKS-NOT: [[G]]{{[[^:word:]]}}
- // BLOCKS: store i{{[0-9]+}} 11, i{{[0-9]+}}* %{{.+}},
- // BLOCKS-NOT: [[SIVAR]]{{[[^:word:]]}}
- // BLOCKS: call void {{%.+}}(i8
^{
g = 2;
sivar = 22;
@@ -177,303 +96,86 @@ int main() {
#endif
}
-// CHECK: [[SIVAR:.+]] = internal global i{{[0-9]+}} 0,
-// CHECK: define{{.*}} i{{[0-9]+}} @main()
-// CHECK: alloca [[S_DOUBLE_TY]],
-// CHECK: [[TEST:%.+]] = alloca [[S_DOUBLE_TY]],
-// CHECK: [[T_VAR_ADDR:%.+]] = alloca i32,
-// CHECK: [[VEC_ADDR:%.+]] = alloca [2 x i32],
-// CHECK: [[S_ARR_ADDR:%.+]] = alloca [2 x [[S_DOUBLE_TY]]],
-// CHECK: [[VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]],
-
-// CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR:@.+]]([[S_DOUBLE_TY]]* {{[^,]*}} [[TEST]],
-
-// CHECK: [[RES:%.+]] = call {{.*}}i32 @__kmpc_master(
-// CHECK-NEXT: [[IS_MASTER:%.+]] = icmp ne i32 [[RES]], 0
-// CHECK-NEXT: br i1 [[IS_MASTER]], label {{%?}}[[THEN:.+]], label {{%?}}[[EXIT:.+]]
-// CHECK: [[THEN]]
+
+
// Store original variables in capture struct.
-// CHECK: [[S_ARR_REF:%.+]] = getelementptr inbounds [[CAP_MAIN_TY]], [[CAP_MAIN_TY]]* %{{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: store [2 x [[S_DOUBLE_TY]]]* %{{.+}}, [2 x [[S_DOUBLE_TY]]]** [[S_ARR_REF]],
-// CHECK: [[VAR_REF:%.+]] = getelementptr inbounds [[CAP_MAIN_TY]], [[CAP_MAIN_TY]]* %{{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 1
-// CHECK: store [[S_DOUBLE_TY]]* %{{.+}}, [[S_DOUBLE_TY]]** [[VAR_REF]],
// Allocate task.
// Returns struct kmp_task_t {
// [[KMP_TASK_T]] task_data;
// [[KMP_TASK_MAIN_TY]] privates;
// };
-// CHECK: [[RES:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i32 9, i64 120, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, [[KMP_TASK_MAIN_TY]]*)* [[TASK_ENTRY:@[^ ]+]] to i32 (i32, i8*)*))
-// CHECK: [[RES_KMP_TASK:%.+]] = bitcast i8* [[RES]] to [[KMP_TASK_MAIN_TY]]*
// Fill kmp_task_t->shareds by copying from original capture argument.
-// CHECK: [[TASK:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: [[SHAREDS_REF_ADDR:%.+]] = getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* [[TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: [[SHAREDS_REF:%.+]] = load i8*, i8** [[SHAREDS_REF_ADDR]],
-// CHECK: [[CAPTURES_ADDR:%.+]] = bitcast [[CAP_MAIN_TY]]* %{{.+}} to i8*
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[SHAREDS_REF]], i8* align 8 [[CAPTURES_ADDR]], i64 16, i1 false)
// Initialize kmp_task_t->privates with default values (no init for simple types, default constructors for classes).
// Also copy address of private copy to the corresponding shareds reference.
-// CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
// Constructors for s_arr and var.
// s_arr;
-// CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: bitcast [2 x [[S_DOUBLE_TY]]]* %{{.+}} to [[S_DOUBLE_TY]]*
-// CHECK: call void [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]* {{[^,]*}} [[S_ARR_CUR:%[^,]+]],
-// CHECK: getelementptr [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* [[S_ARR_CUR]], i{{.+}} 1
-// CHECK: getelementptr [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i{{.+}} 1
-// CHECK: icmp eq
-// CHECK: br i1
// var;
-// CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1
-// CHECK-NEXT: call void [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]* {{[^,]*}} [[PRIVATE_VAR_REF]], [[S_DOUBLE_TY]]* {{.*}},
// t_var;
-// CHECK: [[PRIVATE_T_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2
-// CHECK-NEXT: [[T_VAR:%.+]] = load i32, i32* %{{.+}},
-// CHECK-NEXT: store i32 [[T_VAR]], i32* [[PRIVATE_T_VAR_REF]],
// vec;
-// CHECK: [[PRIVATE_VEC_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3
-// CHECK-NEXT: bitcast [2 x i32]* [[PRIVATE_VEC_REF]] to i8*
-// CHECK-NEXT: bitcast [2 x i32]* %{{.+}} to i8*
-// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(
// sivar;
-// CHECK: [[PRIVATE_SIVAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 4
-// CHECK-NEXT: [[SIVAR:%.+]] = load i{{.+}}, i{{.+}}* @{{.+}},
-// CHECK-NEXT: store i32 [[SIVAR]], i32* [[PRIVATE_SIVAR_REF]],
// Provide pointer to destructor function, which will destroy private variables at the end of the task.
-// CHECK: [[DESTRUCTORS_REF:%.+]] = getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* [[TASK]], i{{.+}} 0, i{{.+}} 3
-// CHECK: [[DESTRUCTORS_PTR:%.+]] = bitcast %union{{.+}}* [[DESTRUCTORS_REF]] to i32 (i32, i8*)**
-// CHECK: store i32 (i32, i8*)* bitcast (i32 (i32, [[KMP_TASK_MAIN_TY]]*)* [[DESTRUCTORS:@.+]] to i32 (i32, i8*)*), i32 (i32, i8*)** [[DESTRUCTORS_PTR]],
// Start task.
-// CHECK: call void @__kmpc_taskloop(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_MAIN_TY]]*, [[KMP_TASK_MAIN_TY]]*, i32)* [[MAIN_DUP:@.+]] to i8*))
-// CHECK: call {{.*}}void @__kmpc_end_master(
-// CHECK-NEXT: br label {{%?}}[[EXIT]]
-// CHECK: [[EXIT]]
-
-// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_MAIN_TY]]* noalias noundef %0, [[S_DOUBLE_TY]]** noalias noundef %1, i32** noalias noundef %2, [2 x [[S_DOUBLE_TY]]]** noalias noundef %3, [2 x i32]** noalias noundef %4, i32** noalias noundef %5)
-// CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_MAIN_TY]]*, [[PRIVATES_MAIN_TY]]**
-// CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 0
-// CHECK: [[ARG3:%.+]] = load [2 x [[S_DOUBLE_TY]]]**, [2 x [[S_DOUBLE_TY]]]*** %{{.+}},
-// CHECK: store [2 x [[S_DOUBLE_TY]]]* [[PRIV_S_VAR]], [2 x [[S_DOUBLE_TY]]]** [[ARG3]],
-// CHECK: [[PRIV_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 1
-// CHECK: [[ARG1:%.+]] = load [[S_DOUBLE_TY]]**, [[S_DOUBLE_TY]]*** {{.+}},
-// CHECK: store [[S_DOUBLE_TY]]* [[PRIV_VAR]], [[S_DOUBLE_TY]]** [[ARG1]],
-// CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 2
-// CHECK: [[ARG2:%.+]] = load i32**, i32*** %{{.+}},
-// CHECK: store i32* [[PRIV_T_VAR]], i32** [[ARG2]],
-// CHECK: [[PRIV_VEC:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 3
-// CHECK: [[ARG4:%.+]] = load [2 x i32]**, [2 x i32]*** %{{.+}},
-// CHECK: store [2 x i32]* [[PRIV_VEC]], [2 x i32]** [[ARG4]],
-// CHECK: [[PRIV_SIVAR:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i32 0, i32 4
-// CHECK: [[ARG5:%.+]] = load i{{[0-9]+}}**, i{{[0-9]+}}*** %{{.+}},
-// CHECK: store i{{[0-9]+}}* [[PRIV_SIVAR]], i{{[0-9]+}}** [[ARG5]],
-// CHECK: ret void
-
-// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1)
-
-// CHECK: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_DOUBLE_TY]]*,
-// CHECK: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*,
-// CHECK: [[PRIV_S_ARR_ADDR:%.+]] = alloca [2 x [[S_DOUBLE_TY]]]*,
-// CHECK: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*,
-// CHECK: [[PRIV_SIVAR_ADDR:%.+]] = alloca i32*,
-// CHECK: store void (i8*, ...)* bitcast (void ([[PRIVATES_MAIN_TY]]*, [[S_DOUBLE_TY]]**, i32**, [2 x [[S_DOUBLE_TY]]]**, [2 x i32]**, i32**)* [[PRIVATES_MAP_FN]] to void (i8*, ...)*), void (i8*, ...)** [[MAP_FN_ADDR:%.+]],
-// CHECK: [[MAP_FN:%.+]] = load void (i8*, ...)*, void (i8*, ...)** [[MAP_FN_ADDR]],
-
-// CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* [[MAP_FN]] to void (i8*,
-// CHECK: call void [[FN]](i8* %{{.+}}, [[S_DOUBLE_TY]]** [[PRIV_VAR_ADDR]], i32** [[PRIV_T_VAR_ADDR]], [2 x [[S_DOUBLE_TY]]]** [[PRIV_S_ARR_ADDR]], [2 x i32]** [[PRIV_VEC_ADDR]], i32** [[PRIV_SIVAR_ADDR]])
-
-// CHECK: [[PRIV_VAR:%.+]] = load [[S_DOUBLE_TY]]*, [[S_DOUBLE_TY]]** [[PRIV_VAR_ADDR]],
-// CHECK: [[PRIV_T_VAR:%.+]] = load i32*, i32** [[PRIV_T_VAR_ADDR]],
-// CHECK: [[PRIV_S_ARR:%.+]] = load [2 x [[S_DOUBLE_TY]]]*, [2 x [[S_DOUBLE_TY]]]** [[PRIV_S_ARR_ADDR]],
-// CHECK: [[PRIV_VEC:%.+]] = load [2 x i32]*, [2 x i32]** [[PRIV_VEC_ADDR]],
-// CHECK: [[PRIV_SIVAR:%.+]] = load i32*, i32** [[PRIV_SIVAR_ADDR]],
+
+
+
+
+
// Privates actually are used.
-// CHECK-DAG: [[PRIV_VAR]]
-// CHECK-DAG: [[PRIV_T_VAR]]
-// CHECK-DAG: [[PRIV_S_ARR]]
-// CHECK-DAG: [[PRIV_VEC]]
-// CHECK-DAG: [[PRIV_SIVAR]]
-
-// CHECK: ret
-
-// CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2)
-// CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1
-// CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0
-// CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0
-// CHECK: getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i64 2
-// CHECK: br i1 %
-
-// CHECK: phi [[S_DOUBLE_TY]]*
-// CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]*
-// CHECK: getelementptr [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i32 1
-// CHECK: icmp eq [[S_DOUBLE_TY]]* %
-// CHECK: br i1 %
-
-// CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 1
-// CHECK: call {{.*}} [[S_DOUBLE_TY_COPY_CONSTR]]([[S_DOUBLE_TY]]*
-// CHECK: ret void
-
-// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %{{.+}}, [[KMP_TASK_MAIN_TY]]* noalias noundef %{{.+}})
-// CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
-// CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0
-// CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1
-// CHECK: call void @_ZN1SIdED1Ev([[S_DOUBLE_TY]]* {{[^,]*}} [[PRIVATE_VAR_REF]])
-// CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* [[PRIVATE_S_ARR_REF]], i{{.+}} 0, i{{.+}} 0
-// CHECK: getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i{{.+}} 2
-// CHECK: [[PRIVATE_S_ARR_ELEM_REF:%.+]] = getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i{{.+}} -1
-// CHECK: call void @_ZN1SIdED1Ev([[S_DOUBLE_TY]]* {{[^,]*}} [[PRIVATE_S_ARR_ELEM_REF]])
-// CHECK: icmp eq
-// CHECK: br i1
-// CHECK: ret i32
-
-// CHECK: alloca [[S_INT_TY]],
-// CHECK: [[TEST:%.+]] = alloca [[S_INT_TY]],
-// CHECK: [[T_VAR_ADDR:%.+]] = alloca i32, align 128
-// CHECK: [[VEC_ADDR:%.+]] = alloca [2 x i32],
-// CHECK: [[S_ARR_ADDR:%.+]] = alloca [2 x [[S_INT_TY]]],
-// CHECK: [[VAR_ADDR:%.+]] = alloca [[S_INT_TY]],
-
-// CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR:@.+]]([[S_INT_TY]]* {{[^,]*}} [[TEST]],
+
+
+
+
+
+
+
// Store original variables in capture struct.
-// CHECK: [[S_ARR_REF:%.+]] = getelementptr inbounds [[CAP_TMAIN_TY]], [[CAP_TMAIN_TY]]* %{{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: store [2 x [[S_INT_TY]]]* %{{.+}}, [2 x [[S_INT_TY]]]** [[S_ARR_REF]],
-// CHECK: [[VAR_REF:%.+]] = getelementptr inbounds [[CAP_TMAIN_TY]], [[CAP_TMAIN_TY]]* %{{.+}}, i{{[0-9]+}} 0, i{{[0-9]+}} 1
-// CHECK: store [[S_INT_TY]]* %{{.+}}, [[S_INT_TY]]** [[VAR_REF]],
// Allocate task.
// Returns struct kmp_task_t {
// [[KMP_TASK_T_TY]] task_data;
// [[KMP_TASK_TMAIN_TY]] privates;
// };
-// CHECK: [[RES:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i32 9, i64 256, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, [[KMP_TASK_TMAIN_TY]]*)* [[TASK_ENTRY:@[^ ]+]] to i32 (i32, i8*)*))
-// CHECK: [[RES_KMP_TASK:%.+]] = bitcast i8* [[RES]] to [[KMP_TASK_TMAIN_TY]]*
// Fill kmp_task_t->shareds by copying from original capture argument.
-// CHECK: [[TASK:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: [[SHAREDS_REF_ADDR:%.+]] = getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* [[TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: [[SHAREDS_REF:%.+]] = load i8*, i8** [[SHAREDS_REF_ADDR]],
-// CHECK: [[CAPTURES_ADDR:%.+]] = bitcast [[CAP_TMAIN_TY]]* %{{.+}} to i8*
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[SHAREDS_REF]], i8* align 8 [[CAPTURES_ADDR]], i64 16, i1 false)
// Initialize kmp_task_t->privates with default values (no init for simple types, default constructors for classes).
-// CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
// t_var;
-// CHECK: [[PRIVATE_T_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0
-// CHECK: [[T_VAR:%.+]] = load i32, i32* %{{.+}}, align 128
-// CHECK: store i32 [[T_VAR]], i32* [[PRIVATE_T_VAR_REF]], align 128
// vec;
-// CHECK: [[PRIVATE_VEC_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1
-// CHECK-NEXT: bitcast [2 x i32]* [[PRIVATE_VEC_REF]] to i8*
-// CHECK-NEXT: bitcast [2 x i32]* %{{.+}} to i8*
-// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(
// Constructors for s_arr and var.
// a_arr;
-// CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
-// CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* [[PRIVATE_S_ARR_REF]], i{{.+}} 0, i{{.+}} 0
-// CHECK: bitcast [2 x [[S_INT_TY]]]* %{{.+}} to [[S_INT_TY]]*
-// CHECK: getelementptr inbounds [[S_INT_TY]], [[S_INT_TY]]* %{{.+}}, i{{.+}} 2
-// CHECK: call void [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]* {{[^,]*}} [[S_ARR_CUR:%[^,]+]],
-// CHECK: getelementptr [[S_INT_TY]], [[S_INT_TY]]* [[S_ARR_CUR]], i{{.+}} 1
-// CHECK: icmp eq
-// CHECK: br i1
// var;
-// CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3
-// CHECK-NEXT: call void [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]* {{[^,]*}} [[PRIVATE_VAR_REF]],
// Provide pointer to destructor function, which will destroy private variables at the end of the task.
-// CHECK: [[DESTRUCTORS_REF:%.+]] = getelementptr inbounds [[KMP_TASK_T_TY]], [[KMP_TASK_T_TY]]* [[TASK]], i{{.+}} 0, i{{.+}} 3
-// CHECK: [[DESTRUCTORS_PTR:%.+]] = bitcast %union{{.+}}* [[DESTRUCTORS_REF]] to i32 (i32, i8*)**
-// CHECK: store i32 (i32, i8*)* bitcast (i32 (i32, [[KMP_TASK_TMAIN_TY]]*)* [[DESTRUCTORS:@.+]] to i32 (i32, i8*)*), i32 (i32, i8*)** [[DESTRUCTORS_PTR]],
// Start task.
-// CHECK: call void @__kmpc_taskloop(%struct.ident_t* @{{.+}}, i32 %{{.+}}, i8* [[RES]], i32 1, i64* %{{.+}}, i64* %{{.+}}, i64 %{{.+}}, i32 1, i32 0, i64 0, i8* bitcast (void ([[KMP_TASK_TMAIN_TY]]*, [[KMP_TASK_TMAIN_TY]]*, i32)* [[TMAIN_DUP:@.+]] to i8*))
-
-// CHECK: define internal void [[PRIVATES_MAP_FN:@.+]]([[PRIVATES_TMAIN_TY]]* noalias noundef %{{.+}}, i32** noalias noundef %{{.+}}, [2 x i32]** noalias noundef %{{.+}}, [2 x [[S_INT_TY]]]** noalias noundef %{{.+}}, [[S_INT_TY]]** noalias noundef %{{.+}})
-// CHECK: [[PRIVATES:%.+]] = load [[PRIVATES_TMAIN_TY]]*, [[PRIVATES_TMAIN_TY]]**
-// CHECK: [[PRIV_T_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 0
-// CHECK: [[ARG1:%.+]] = load i32**, i32*** %{{.+}},
-// CHECK: store i32* [[PRIV_T_VAR]], i32** [[ARG1]],
-// CHECK: [[PRIV_VEC:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 1
-// CHECK: [[ARG2:%.+]] = load [2 x i32]**, [2 x i32]*** %{{.+}},
-// CHECK: store [2 x i32]* [[PRIV_VEC]], [2 x i32]** [[ARG2]],
-// CHECK: [[PRIV_S_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 2
-// CHECK: [[ARG3:%.+]] = load [2 x [[S_INT_TY]]]**, [2 x [[S_INT_TY]]]*** %{{.+}},
-// CHECK: store [2 x [[S_INT_TY]]]* [[PRIV_S_VAR]], [2 x [[S_INT_TY]]]** [[ARG3]],
-// CHECK: [[PRIV_VAR:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i32 0, i32 3
-// CHECK: [[ARG4:%.+]] = load [[S_INT_TY]]**, [[S_INT_TY]]*** {{.+}},
-// CHECK: store [[S_INT_TY]]* [[PRIV_VAR]], [[S_INT_TY]]** [[ARG4]],
-// CHECK: ret void
-
-// CHECK: define internal noundef i32 [[TASK_ENTRY]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1)
-// CHECK: alloca i32*,
-// CHECK-DAG: [[PRIV_T_VAR_ADDR:%.+]] = alloca i32*,
-// CHECK-DAG: [[PRIV_VEC_ADDR:%.+]] = alloca [2 x i32]*,
-// CHECK-DAG: [[PRIV_S_ARR_ADDR:%.+]] = alloca [2 x [[S_INT_TY]]]*,
-// CHECK-DAG: [[PRIV_VAR_ADDR:%.+]] = alloca [[S_INT_TY]]*,
-// CHECK: store void (i8*, ...)* bitcast (void ([[PRIVATES_TMAIN_TY]]*, i32**, [2 x i32]**, [2 x [[S_INT_TY]]]**, [[S_INT_TY]]**)* [[PRIVATES_MAP_FN]] to void (i8*, ...)*), void (i8*, ...)** [[MAP_FN_ADDR:%.+]],
-// CHECK: [[MAP_FN:%.+]] = load void (i8*, ...)*, void (i8*, ...)** [[MAP_FN_ADDR]],
-// CHECK: [[FN:%.+]] = bitcast void (i8*, ...)* [[MAP_FN]] to void (i8*,
-// CHECK: call void [[FN]](i8* %{{.+}}, i32** [[PRIV_T_VAR_ADDR]], [2 x i32]** [[PRIV_VEC_ADDR]], [2 x [[S_INT_TY]]]** [[PRIV_S_ARR_ADDR]], [[S_INT_TY]]** [[PRIV_VAR_ADDR]])
-// CHECK: [[PRIV_T_VAR:%.+]] = load i32*, i32** [[PRIV_T_VAR_ADDR]],
-// CHECK: [[PRIV_VEC:%.+]] = load [2 x i32]*, [2 x i32]** [[PRIV_VEC_ADDR]],
-// CHECK: [[PRIV_S_ARR:%.+]] = load [2 x [[S_INT_TY]]]*, [2 x [[S_INT_TY]]]** [[PRIV_S_ARR_ADDR]],
-// CHECK: [[PRIV_VAR:%.+]] = load [[S_INT_TY]]*, [[S_INT_TY]]** [[PRIV_VAR_ADDR]],
+
+
// Privates actually are used.
-// CHECK-DAG: [[PRIV_VAR]]
-// CHECK-DAG: [[PRIV_T_VAR]]
-// CHECK-DAG: [[PRIV_S_ARR]]
-// CHECK-DAG: [[PRIV_VEC]]
-
-// CHECK: ret
-
-// CHECK: define internal void [[TMAIN_DUP]]([[KMP_TASK_TMAIN_TY]]* noundef %0, [[KMP_TASK_TMAIN_TY]]* noundef %1, i32 noundef %2)
-// CHECK: getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* %{{.+}}, i32 0, i32 2
-// CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 2
-// CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* %{{.+}}, i32 0, i32 0
-// CHECK: getelementptr inbounds [[S_INT_TY]], [[S_INT_TY]]* %{{.+}}, i64 2
-// CHECK: br i1 %
-
-// CHECK: phi [[S_INT_TY]]*
-// CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]*
-// CHECK: getelementptr [[S_INT_TY]], [[S_INT_TY]]* %{{.+}}, i32 1
-// CHECK: icmp eq [[S_INT_TY]]* %
-// CHECK: br i1 %
-
-// CHECK: getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* %{{.+}}, i32 0, i32 3
-// CHECK: call {{.*}} [[S_INT_TY_COPY_CONSTR]]([[S_INT_TY]]*
-// CHECK: ret void
-
-// CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_TMAIN_TY]]* noalias noundef %1)
-// CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_TMAIN_TY]], [[KMP_TASK_TMAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
-// CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 2
-// CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_TMAIN_TY]], [[PRIVATES_TMAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 3
-// CHECK: call void @_ZN1SIiED1Ev([[S_INT_TY]]* {{[^,]*}} [[PRIVATE_VAR_REF]])
-// CHECK: getelementptr inbounds [2 x [[S_INT_TY]]], [2 x [[S_INT_TY]]]* [[PRIVATE_S_ARR_REF]], i{{.+}} 0, i{{.+}} 0
-// CHECK: getelementptr inbounds [[S_INT_TY]], [[S_INT_TY]]* %{{.+}}, i{{.+}} 2
-// CHECK: [[PRIVATE_S_ARR_ELEM_REF:%.+]] = getelementptr inbounds [[S_INT_TY]], [[S_INT_TY]]* %{{.+}}, i{{.+}} -1
-// CHECK: call void @_ZN1SIiED1Ev([[S_INT_TY]]* {{[^,]*}} [[PRIVATE_S_ARR_ELEM_REF]])
-// CHECK: icmp eq
-// CHECK: br i1
-// CHECK: ret i32
+
+
+
+
+
#endif
#else
-// ARRAY-LABEL: array_func
struct St {
int a, b;
St() : a(0), b(0) {}
@@ -482,13 +184,2309 @@ struct St {
};
void array_func(int n, float a[n], St s[2]) {
-// ARRAY: call i8* @__kmpc_omp_task_alloc(
-// ARRAY: call void @__kmpc_taskloop(
-// ARRAY: store float** %{{.+}}, float*** %{{.+}},
-// ARRAY: store %struct.St** %{{.+}}, %struct.St*** %{{.+}},
#pragma omp parallel master taskloop simd firstprivate(a, s)
for (int i = 0; i < 10; ++i)
;
}
#endif
+// CHECK-LABEL: define {{[^@]+}}@main
+// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8
+// CHECK-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8
+// CHECK-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16
+// CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8
+// CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
+// CHECK-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// CHECK-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]])
+// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00)
+// CHECK-NEXT: store i32 0, i32* [[T_VAR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false)
+// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
+// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00)
+// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
+// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00)
+// CHECK-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00)
+// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4
+// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
+// CHECK-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
+// CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]])
+// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
+// CHECK-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]]
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
+// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// CHECK: arraydestroy.body:
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK: arraydestroy.done1:
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]]
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]]
+// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
+// CHECK-NEXT: ret i32 [[TMP4]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// CHECK-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_outlined.
+// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S]* noundef nonnull align 8 dereferenceable(16) [[S_ARR:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR:%.*]]) #[[ATTR3:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
+// CHECK-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
+// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
+// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
+// CHECK-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
+// CHECK-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
+// CHECK-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
+// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
+// CHECK-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
+// CHECK-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
+// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
+// CHECK-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
+// CHECK: omp_if.then:
+// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
+// CHECK-NEXT: store [2 x %struct.S]* [[TMP1]], [2 x %struct.S]** [[TMP7]], align 8
+// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
+// CHECK-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP8]], align 8
+// CHECK-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 9, i64 120, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
+// CHECK-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates*
+// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP10]], i32 0, i32 0
+// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 0
+// CHECK-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 [[TMP14]], i64 16, i1 false)
+// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP10]], i32 0, i32 1
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 0
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP16]], i32 0, i32 0
+// CHECK-NEXT: [[TMP17:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S*
+// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP18]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK: omp.arraycpy.body:
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP17]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00)
+// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP18]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK: omp.arraycpy.done1:
+// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 1
+// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP19]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP2]], double noundef 0.000000e+00)
+// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 2
+// CHECK-NEXT: [[TMP21:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK-NEXT: store i32 [[TMP21]], i32* [[TMP20]], align 8
+// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 3
+// CHECK-NEXT: [[TMP23:%.*]] = bitcast [2 x i32]* [[TMP22]] to i8*
+// CHECK-NEXT: [[TMP24:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP23]], i8* align 4 [[TMP24]], i64 8, i1 false)
+// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP15]], i32 0, i32 4
+// CHECK-NEXT: [[TMP26:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
+// CHECK-NEXT: store i32 [[TMP26]], i32* [[TMP25]], align 4
+// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 3
+// CHECK-NEXT: [[TMP28:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP27]] to i32 (i32, i8*)**
+// CHECK-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_destructor. to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP28]], align 8
+// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 5
+// CHECK-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 6
+// CHECK-NEXT: store i64 9, i64* [[TMP30]], align 8
+// CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 7
+// CHECK-NEXT: store i64 1, i64* [[TMP31]], align 8
+// CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 9
+// CHECK-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i8*
+// CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP33]], i8 0, i64 8, i1 false)
+// CHECK-NEXT: [[TMP34:%.*]] = load i64, i64* [[TMP31]], align 8
+// CHECK-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i8* [[TMP9]], i32 1, i64* [[TMP29]], i64* [[TMP30]], i64 [[TMP34]], i32 1, i32 0, i64 0, i8* bitcast (void (%struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates*, i32)* @.omp_task_dup. to i8*))
+// CHECK-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: br label [[OMP_IF_END]]
+// CHECK: omp_if.end:
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_privates_map.
+// CHECK-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], %struct.S** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]], [2 x %struct.S]** noalias noundef [[TMP3:%.*]], [2 x i32]** noalias noundef [[TMP4:%.*]], i32** noalias noundef [[TMP5:%.*]]) #[[ATTR6:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.S**, align 8
+// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8
+// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca [2 x %struct.S]**, align 8
+// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca [2 x i32]**, align 8
+// CHECK-NEXT: [[DOTADDR5:%.*]] = alloca i32**, align 8
+// CHECK-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
+// CHECK-NEXT: store %struct.S** [[TMP1]], %struct.S*** [[DOTADDR1]], align 8
+// CHECK-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8
+// CHECK-NEXT: store [2 x %struct.S]** [[TMP3]], [2 x %struct.S]*** [[DOTADDR3]], align 8
+// CHECK-NEXT: store [2 x i32]** [[TMP4]], [2 x i32]*** [[DOTADDR4]], align 8
+// CHECK-NEXT: store i32** [[TMP5]], i32*** [[DOTADDR5]], align 8
+// CHECK-NEXT: [[TMP6:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
+// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 0
+// CHECK-NEXT: [[TMP8:%.*]] = load [2 x %struct.S]**, [2 x %struct.S]*** [[DOTADDR3]], align 8
+// CHECK-NEXT: store [2 x %struct.S]* [[TMP7]], [2 x %struct.S]** [[TMP8]], align 8
+// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 1
+// CHECK-NEXT: [[TMP10:%.*]] = load %struct.S**, %struct.S*** [[DOTADDR1]], align 8
+// CHECK-NEXT: store %struct.S* [[TMP9]], %struct.S** [[TMP10]], align 8
+// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 2
+// CHECK-NEXT: [[TMP12:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8
+// CHECK-NEXT: store i32* [[TMP11]], i32** [[TMP12]], align 8
+// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 3
+// CHECK-NEXT: [[TMP14:%.*]] = load [2 x i32]**, [2 x i32]*** [[DOTADDR4]], align 8
+// CHECK-NEXT: store [2 x i32]* [[TMP13]], [2 x i32]** [[TMP14]], align 8
+// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP6]], i32 0, i32 4
+// CHECK-NEXT: [[TMP16:%.*]] = load i32**, i32*** [[DOTADDR5]], align 8
+// CHECK-NEXT: store i32* [[TMP15]], i32** [[TMP16]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_entry.
+// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
+// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [2 x %struct.S]*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [2 x i32]*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR4_I:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[I_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
+// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
+// CHECK-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
+// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
+// CHECK-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
+// CHECK-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
+// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5
+// CHECK-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6
+// CHECK-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7
+// CHECK-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8
+// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8
+// CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8
+// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9
+// CHECK-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
+// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
+// CHECK-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, %struct.S**, i32**, [2 x %struct.S]**, [2 x i32]**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
+// CHECK-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, %struct.S**, i32**, [2 x %struct.S]**, [2 x i32]**, i32**)*
+// CHECK-NEXT: call void [[TMP25]](i8* [[TMP24]], %struct.S** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [2 x %struct.S]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR4_I]]) #[[ATTR4]]
+// CHECK-NEXT: [[TMP26:%.*]] = load %struct.S*, %struct.S** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP28:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP29:%.*]] = load [2 x i32]*, [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR4_I]], align 8, !noalias !14
+// CHECK-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP31]] to i32
+// CHECK-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
+// CHECK: omp.inner.for.cond.i:
+// CHECK-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]]
+// CHECK-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP32]] to i64
+// CHECK-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP33]]
+// CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
+// CHECK: omp.inner.for.body.i:
+// CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// CHECK-NEXT: store i32 [[TMP34]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// CHECK-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP27]], align 4, !llvm.access.group [[ACC_GRP15]]
+// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP29]], i64 0, i64 0
+// CHECK-NEXT: store i32 [[TMP35]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP15]]
+// CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP28]], i64 0, i64 0
+// CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[ARRAYIDX6_I]] to i8*
+// CHECK-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP26]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP36]], i8* align 8 [[TMP37]], i64 8, i1 false), !llvm.access.group [[ACC_GRP15]]
+// CHECK-NEXT: store i32 33, i32* [[TMP30]], align 4, !llvm.access.group [[ACC_GRP15]]
+// CHECK-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// CHECK-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP38]], 1
+// CHECK-NEXT: store i32 [[ADD7_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
+// CHECK: .omp_outlined..1.exit:
+// CHECK-NEXT: ret i32 0
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_dup.
+// CHECK-SAME: (%struct.kmp_task_t_with_privates* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP0]], %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTADDR2]], align 4
+// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP5]], i32 0, i32 0
+// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
+// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
+// CHECK-NEXT: [[TMP9:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
+// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP8]], i32 0, i32 0
+// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP9]], i32 0, i32 0
+// CHECK-NEXT: [[TMP12:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[TMP11]], align 8
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP10]], i32 0, i32 0
+// CHECK-NEXT: [[TMP13:%.*]] = bitcast [2 x %struct.S]* [[TMP12]] to %struct.S*
+// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP14]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK: omp.arraycpy.body:
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP13]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]], double noundef 0.000000e+00)
+// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP14]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK: omp.arraycpy.done3:
+// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP8]], i32 0, i32 1
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP9]], i32 0, i32 1
+// CHECK-NEXT: [[TMP17:%.*]] = load %struct.S*, %struct.S** [[TMP16]], align 8
+// CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP15]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP17]], double noundef 0.000000e+00)
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_destructor.
+// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP2]], i32 0, i32 1
+// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// CHECK: arraydestroy.body:
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// CHECK-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK: arraydestroy.done2:
+// CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4
+// CHECK-NEXT: ret i32 [[TMP7]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
+// CHECK-SAME: () #[[ATTR9:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
+// CHECK-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4
+// CHECK-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
+// CHECK-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
+// CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
+// CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
+// CHECK-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]])
+// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0)
+// CHECK-NEXT: store i32 0, i32* [[T_VAR]], align 128
+// CHECK-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
+// CHECK-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
+// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
+// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
+// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
+// CHECK-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
+// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 128
+// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32*
+// CHECK-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8
+// CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]])
+// CHECK-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
+// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// CHECK: arraydestroy.body:
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK: arraydestroy.done1:
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]]
+// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
+// CHECK-NEXT: ret i32 [[TMP4]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: store double 0.000000e+00, double* [[F]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// CHECK-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
+// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8
+// CHECK-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]]
+// CHECK-NEXT: store double [[ADD]], double* [[F]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// CHECK-NEXT: store double [[TMP0]], double* [[F]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev
+// CHECK-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// CHECK-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// CHECK-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// CHECK-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_outlined..2
+// CHECK-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [2 x i32]* noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], [2 x %struct.S.0]* noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
+// CHECK-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
+// CHECK-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8
+// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
+// CHECK-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8
+// CHECK-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
+// CHECK-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
+// CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32*
+// CHECK-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
+// CHECK-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4
+// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
+// CHECK-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
+// CHECK: omp_if.then:
+// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[AGG_CAPTURED]], i32 0, i32 0
+// CHECK-NEXT: store [2 x %struct.S.0]* [[TMP1]], [2 x %struct.S.0]** [[TMP7]], align 8
+// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[AGG_CAPTURED]], i32 0, i32 1
+// CHECK-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP8]], align 8
+// CHECK-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: [[TMP9:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 9, i64 256, i64 16, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_entry..5 to i32 (i32, i8*)*))
+// CHECK-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to %struct.kmp_task_t_with_privates.2*
+// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP10]], i32 0, i32 0
+// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 0
+// CHECK-NEXT: [[TMP13:%.*]] = load i8*, i8** [[TMP12]], align 128
+// CHECK-NEXT: [[TMP14:%.*]] = bitcast %struct.anon.1* [[AGG_CAPTURED]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 [[TMP14]], i64 16, i1 false)
+// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP10]], i32 0, i32 2
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 0
+// CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK-NEXT: store i32 [[TMP17]], i32* [[TMP16]], align 128
+// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 1
+// CHECK-NEXT: [[TMP19:%.*]] = bitcast [2 x i32]* [[TMP18]] to i8*
+// CHECK-NEXT: [[TMP20:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 8, i1 false)
+// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 2
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP21]], i32 0, i32 0
+// CHECK-NEXT: [[TMP22:%.*]] = bitcast [2 x %struct.S.0]* [[TMP1]] to %struct.S.0*
+// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP23]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK: omp.arraycpy.body:
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP22]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0)
+// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP23]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK: omp.arraycpy.done1:
+// CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP15]], i32 0, i32 3
+// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP24]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP2]], i32 noundef 0)
+// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 3
+// CHECK-NEXT: [[TMP26:%.*]] = bitcast %union.kmp_cmplrdata_t* [[TMP25]] to i32 (i32, i8*)**
+// CHECK-NEXT: store i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates.2*)* @.omp_task_destructor..7 to i32 (i32, i8*)*), i32 (i32, i8*)** [[TMP26]], align 8
+// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 5
+// CHECK-NEXT: store i64 0, i64* [[TMP27]], align 8
+// CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 6
+// CHECK-NEXT: store i64 9, i64* [[TMP28]], align 16
+// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 7
+// CHECK-NEXT: store i64 1, i64* [[TMP29]], align 8
+// CHECK-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP11]], i32 0, i32 9
+// CHECK-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i8*
+// CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP31]], i8 0, i64 8, i1 false)
+// CHECK-NEXT: [[TMP32:%.*]] = load i64, i64* [[TMP29]], align 8
+// CHECK-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i8* [[TMP9]], i32 1, i64* [[TMP27]], i64* [[TMP28]], i64 [[TMP32]], i32 1, i32 0, i64 0, i8* bitcast (void (%struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2*, i32)* @.omp_task_dup..6 to i8*))
+// CHECK-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]])
+// CHECK-NEXT: br label [[OMP_IF_END]]
+// CHECK: omp_if.end:
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_privates_map..4
+// CHECK-SAME: (%struct..kmp_privates.t.3* noalias noundef [[TMP0:%.*]], i32** noalias noundef [[TMP1:%.*]], [2 x i32]** noalias noundef [[TMP2:%.*]], [2 x %struct.S.0]** noalias noundef [[TMP3:%.*]], %struct.S.0** noalias noundef [[TMP4:%.*]]) #[[ATTR6]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t.3*, align 8
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32**, align 8
+// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca [2 x i32]**, align 8
+// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca [2 x %struct.S.0]**, align 8
+// CHECK-NEXT: [[DOTADDR4:%.*]] = alloca %struct.S.0**, align 8
+// CHECK-NEXT: store %struct..kmp_privates.t.3* [[TMP0]], %struct..kmp_privates.t.3** [[DOTADDR]], align 8
+// CHECK-NEXT: store i32** [[TMP1]], i32*** [[DOTADDR1]], align 8
+// CHECK-NEXT: store [2 x i32]** [[TMP2]], [2 x i32]*** [[DOTADDR2]], align 8
+// CHECK-NEXT: store [2 x %struct.S.0]** [[TMP3]], [2 x %struct.S.0]*** [[DOTADDR3]], align 8
+// CHECK-NEXT: store %struct.S.0** [[TMP4]], %struct.S.0*** [[DOTADDR4]], align 8
+// CHECK-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t.3*, %struct..kmp_privates.t.3** [[DOTADDR]], align 8
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 0
+// CHECK-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR1]], align 8
+// CHECK-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8
+// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 1
+// CHECK-NEXT: [[TMP9:%.*]] = load [2 x i32]**, [2 x i32]*** [[DOTADDR2]], align 8
+// CHECK-NEXT: store [2 x i32]* [[TMP8]], [2 x i32]** [[TMP9]], align 8
+// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 2
+// CHECK-NEXT: [[TMP11:%.*]] = load [2 x %struct.S.0]**, [2 x %struct.S.0]*** [[DOTADDR3]], align 8
+// CHECK-NEXT: store [2 x %struct.S.0]* [[TMP10]], [2 x %struct.S.0]** [[TMP11]], align 8
+// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP5]], i32 0, i32 3
+// CHECK-NEXT: [[TMP13:%.*]] = load %struct.S.0**, %struct.S.0*** [[DOTADDR4]], align 8
+// CHECK-NEXT: store %struct.S.0* [[TMP12]], %struct.S.0** [[TMP13]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_entry..5
+// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
+// CHECK-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8
+// CHECK-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon.1*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i32*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [2 x i32]*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [2 x %struct.S.0]*, align 8
+// CHECK-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[I_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8
+// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
+// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 0
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 128
+// CHECK-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.1*
+// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 2
+// CHECK-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t.3* [[TMP9]] to i8*
+// CHECK-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates.2* [[TMP3]] to i8*
+// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5
+// CHECK-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6
+// CHECK-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 16
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7
+// CHECK-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8
+// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8
+// CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 64
+// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9
+// CHECK-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]])
+// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]])
+// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !32
+// CHECK-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t.3*, i32**, [2 x i32]**, [2 x %struct.S.0]**, %struct.S.0**)* @.omp_task_privates_map..4 to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !32
+// CHECK-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: store %struct.anon.1* [[TMP8]], %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: [[TMP22:%.*]] = load %struct.anon.1*, %struct.anon.1** [[__CONTEXT_ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, i32**, [2 x i32]**, [2 x %struct.S.0]**, %struct.S.0**)*
+// CHECK-NEXT: call void [[TMP25]](i8* [[TMP24]], i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [2 x %struct.S.0]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], %struct.S.0** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
+// CHECK-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: [[TMP27:%.*]] = load [2 x i32]*, [2 x i32]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !32
+// CHECK-NEXT: [[TMP28:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !32
+// CHECK-NEXT: [[TMP29:%.*]] = load %struct.S.0*, %struct.S.0** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !32
+// CHECK-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !32
+// CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP30]] to i32
+// CHECK-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !32
+// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
+// CHECK: omp.inner.for.cond.i:
+// CHECK-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33:![0-9]+]]
+// CHECK-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP31]] to i64
+// CHECK-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !32, !llvm.access.group [[ACC_GRP33]]
+// CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP32]]
+// CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
+// CHECK: omp.inner.for.body.i:
+// CHECK-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]]
+// CHECK-NEXT: store i32 [[TMP33]], i32* [[I_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]]
+// CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP26]], align 128, !llvm.access.group [[ACC_GRP33]]
+// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP27]], i64 0, i64 0
+// CHECK-NEXT: store i32 [[TMP34]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP33]]
+// CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP28]], i64 0, i64 0
+// CHECK-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5_I]] to i8*
+// CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8*
+// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false), !llvm.access.group [[ACC_GRP33]]
+// CHECK-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]]
+// CHECK-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP37]], 1
+// CHECK-NEXT: store i32 [[ADD6_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]]
+// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP34:![0-9]+]]
+// CHECK: .omp_outlined..3.exit:
+// CHECK-NEXT: ret i32 0
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_dup..6
+// CHECK-SAME: (%struct.kmp_task_t_with_privates.2* noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noundef [[TMP1:%.*]], i32 noundef [[TMP2:%.*]]) #[[ATTR7]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8
+// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP0]], %struct.kmp_task_t_with_privates.2** [[DOTADDR]], align 8
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: store i32 [[TMP2]], i32* [[DOTADDR2]], align 4
+// CHECK-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR]], align 8
+// CHECK-NEXT: [[TMP4:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP5]], i32 0, i32 0
+// CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 128
+// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], %struct.kmp_task_t_with_privates.2* [[TMP3]], i32 0, i32 2
+// CHECK-NEXT: [[TMP9:%.*]] = bitcast i8* [[TMP7]] to %struct.anon.1*
+// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP8]], i32 0, i32 2
+// CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], %struct.anon.1* [[TMP9]], i32 0, i32 0
+// CHECK-NEXT: [[TMP12:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[TMP11]], align 8
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP10]], i32 0, i32 0
+// CHECK-NEXT: [[TMP13:%.*]] = bitcast [2 x %struct.S.0]* [[TMP12]] to %struct.S.0*
+// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP14]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK: omp.arraycpy.body:
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP13]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 noundef 0)
+// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
+// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP14]]
+// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK: omp.arraycpy.done3:
+// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP8]], i32 0, i32 3
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP9]], i32 0, i32 1
+// CHECK-NEXT: [[TMP17:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP16]], align 8
+// CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP15]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP17]], i32 noundef 0)
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@.omp_task_destructor..7
+// CHECK-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates.2* noalias noundef [[TMP1:%.*]]) #[[ATTR7]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates.2*, align 8
+// CHECK-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// CHECK-NEXT: store %struct.kmp_task_t_with_privates.2* [[TMP1]], %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP2:%.*]] = load %struct.kmp_task_t_with_privates.2*, %struct.kmp_task_t_with_privates.2** [[DOTADDR1]], align 8
+// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], %struct.kmp_task_t_with_privates.2* [[TMP2]], i32 0, i32 2
+// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3:%.*]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 2
+// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T_3]], %struct..kmp_privates.t.3* [[TMP3]], i32 0, i32 3
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP4]], i32 0, i32 0
+// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// CHECK: arraydestroy.body:
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// CHECK-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK: arraydestroy.done2:
+// CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[RETVAL]], align 4
+// CHECK-NEXT: ret i32 [[TMP7]]
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: store i32 0, i32* [[F]], align 4
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// CHECK-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
+// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
+// CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
+// CHECK-NEXT: store i32 [[ADD]], i32* [[F]], align 4
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
+// CHECK-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// CHECK-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// CHECK-NEXT: ret void
+//
+//
+// LAMBDA-LABEL: define {{[^@]+}}@main
+// LAMBDA-SAME: () #[[ATTR0:[0-9]+]] {
+// LAMBDA-NEXT: entry:
+// LAMBDA-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
+// LAMBDA-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// LAMBDA-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
+// LAMBDA-NEXT: ret i32 0
+//
+//
+// LAMBDA-LABEL: define {{[^@]+}}@.omp_outlined.
+// LAMBDA-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] {
+// LAMBDA-NEXT: entry:
+// LAMBDA-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
+// LAMBDA-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
+// LAMBDA-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
+// LAMBDA-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// LAMBDA-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
+// LAMBDA-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// LAMBDA-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
+// LAMBDA-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]])
+// LAMBDA-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
+// LAMBDA-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
+// LAMBDA: omp_if.then:
+// LAMBDA-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// LAMBDA-NEXT: [[TMP4:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 96, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
+// LAMBDA-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.kmp_task_t_with_privates*
+// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 0
+// LAMBDA-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 1
+// LAMBDA-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 0
+// LAMBDA-NEXT: [[TMP9:%.*]] = load volatile double, double* @g, align 8
+// LAMBDA-NEXT: store volatile double [[TMP9]], double* [[TMP8]], align 8
+// LAMBDA-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 1
+// LAMBDA-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
+// LAMBDA-NEXT: store i32 [[TMP11]], i32* [[TMP10]], align 8
+// LAMBDA-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 5
+// LAMBDA-NEXT: store i64 0, i64* [[TMP12]], align 8
+// LAMBDA-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 6
+// LAMBDA-NEXT: store i64 9, i64* [[TMP13]], align 8
+// LAMBDA-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 7
+// LAMBDA-NEXT: store i64 1, i64* [[TMP14]], align 8
+// LAMBDA-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 9
+// LAMBDA-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i8*
+// LAMBDA-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP16]], i8 0, i64 8, i1 false)
+// LAMBDA-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP14]], align 8
+// LAMBDA-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP4]], i32 1, i64* [[TMP12]], i64* [[TMP13]], i64 [[TMP17]], i32 1, i32 0, i64 0, i8* null)
+// LAMBDA-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// LAMBDA-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// LAMBDA-NEXT: br label [[OMP_IF_END]]
+// LAMBDA: omp_if.end:
+// LAMBDA-NEXT: ret void
+//
+//
+// LAMBDA-LABEL: define {{[^@]+}}@.omp_task_privates_map.
+// LAMBDA-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR5:[0-9]+]] {
+// LAMBDA-NEXT: entry:
+// LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
+// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8
+// LAMBDA-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8
+// LAMBDA-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
+// LAMBDA-NEXT: store double** [[TMP1]], double*** [[DOTADDR1]], align 8
+// LAMBDA-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8
+// LAMBDA-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
+// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0
+// LAMBDA-NEXT: [[TMP5:%.*]] = load double**, double*** [[DOTADDR1]], align 8
+// LAMBDA-NEXT: store double* [[TMP4]], double** [[TMP5]], align 8
+// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1
+// LAMBDA-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8
+// LAMBDA-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8
+// LAMBDA-NEXT: ret void
+//
+//
+// LAMBDA-LABEL: define {{[^@]+}}@.omp_task_entry.
+// LAMBDA-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
+// LAMBDA-NEXT: entry:
+// LAMBDA-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
+// LAMBDA-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
+// LAMBDA-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
+// LAMBDA-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
+// LAMBDA-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
+// LAMBDA-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
+// LAMBDA-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
+// LAMBDA-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8
+// LAMBDA-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
+// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca double*, align 8
+// LAMBDA-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8
+// LAMBDA-NEXT: [[I_I:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[REF_TMP_I:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
+// LAMBDA-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// LAMBDA-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// LAMBDA-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// LAMBDA-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// LAMBDA-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
+// LAMBDA-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// LAMBDA-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
+// LAMBDA-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
+// LAMBDA-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
+// LAMBDA-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
+// LAMBDA-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
+// LAMBDA-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
+// LAMBDA-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
+// LAMBDA-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
+// LAMBDA-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5
+// LAMBDA-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8
+// LAMBDA-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6
+// LAMBDA-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8
+// LAMBDA-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7
+// LAMBDA-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8
+// LAMBDA-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8
+// LAMBDA-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8
+// LAMBDA-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9
+// LAMBDA-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8
+// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
+// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
+// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
+// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
+// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
+// LAMBDA-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
+// LAMBDA-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, double**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
+// LAMBDA-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, double**, i32**)*
+// LAMBDA-NEXT: call void [[TMP25]](i8* [[TMP24]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]]
+// LAMBDA-NEXT: [[TMP26:%.*]] = load double*, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// LAMBDA-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP28]] to i32
+// LAMBDA-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
+// LAMBDA: omp.inner.for.cond.i:
+// LAMBDA-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]]
+// LAMBDA-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP29]] to i64
+// LAMBDA-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// LAMBDA-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP30]]
+// LAMBDA-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
+// LAMBDA: omp.inner.for.body.i:
+// LAMBDA-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// LAMBDA-NEXT: store i32 [[TMP31]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// LAMBDA-NEXT: store double 1.000000e+00, double* [[TMP26]], align 8, !llvm.access.group [[ACC_GRP15]]
+// LAMBDA-NEXT: store i32 11, i32* [[TMP27]], align 4, !llvm.access.group [[ACC_GRP15]]
+// LAMBDA-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP_I]], i32 0, i32 0
+// LAMBDA-NEXT: store double* [[TMP26]], double** [[TMP32]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// LAMBDA-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP_I]], i32 0, i32 1
+// LAMBDA-NEXT: store i32* [[TMP27]], i32** [[TMP33]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// LAMBDA-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]), !llvm.access.group [[ACC_GRP15]]
+// LAMBDA-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// LAMBDA-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP34]], 1
+// LAMBDA-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
+// LAMBDA: .omp_outlined..1.exit:
+// LAMBDA-NEXT: ret i32 0
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@main
+// BLOCKS-SAME: () #[[ATTR1:[0-9]+]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// BLOCKS-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8
+// BLOCKS-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)*
+// BLOCKS-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*))
+// BLOCKS-NEXT: ret i32 0
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@__main_block_invoke
+// BLOCKS-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
+// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
+// BLOCKS-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
+// BLOCKS-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
+// BLOCKS-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
+// BLOCKS-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
+// BLOCKS-NEXT: ret void
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@.omp_outlined.
+// BLOCKS-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
+// BLOCKS-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
+// BLOCKS-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
+// BLOCKS-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// BLOCKS-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
+// BLOCKS-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// BLOCKS-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
+// BLOCKS-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// BLOCKS-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
+// BLOCKS-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
+// BLOCKS: omp_if.then:
+// BLOCKS-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// BLOCKS-NEXT: [[TMP4:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i64 96, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
+// BLOCKS-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to %struct.kmp_task_t_with_privates*
+// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 0
+// BLOCKS-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP5]], i32 0, i32 1
+// BLOCKS-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 0
+// BLOCKS-NEXT: [[TMP9:%.*]] = load volatile double, double* @g, align 8
+// BLOCKS-NEXT: store volatile double [[TMP9]], double* [[TMP8]], align 8
+// BLOCKS-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP7]], i32 0, i32 1
+// BLOCKS-NEXT: [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4
+// BLOCKS-NEXT: store i32 [[TMP11]], i32* [[TMP10]], align 8
+// BLOCKS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 5
+// BLOCKS-NEXT: store i64 0, i64* [[TMP12]], align 8
+// BLOCKS-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 6
+// BLOCKS-NEXT: store i64 9, i64* [[TMP13]], align 8
+// BLOCKS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 7
+// BLOCKS-NEXT: store i64 1, i64* [[TMP14]], align 8
+// BLOCKS-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP6]], i32 0, i32 9
+// BLOCKS-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i8*
+// BLOCKS-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP16]], i8 0, i64 8, i1 false)
+// BLOCKS-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP14]], align 8
+// BLOCKS-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* [[TMP4]], i32 1, i64* [[TMP12]], i64* [[TMP13]], i64 [[TMP17]], i32 1, i32 0, i64 0, i8* null)
+// BLOCKS-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// BLOCKS-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
+// BLOCKS-NEXT: br label [[OMP_IF_END]]
+// BLOCKS: omp_if.end:
+// BLOCKS-NEXT: ret void
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@_block_invoke
+// BLOCKS-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
+// BLOCKS-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8
+// BLOCKS-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
+// BLOCKS-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*
+// BLOCKS-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8
+// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5
+// BLOCKS-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8
+// BLOCKS-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6
+// BLOCKS-NEXT: store i32 22, i32* [[BLOCK_CAPTURE_ADDR1]], align 8
+// BLOCKS-NEXT: ret void
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@.omp_task_privates_map.
+// BLOCKS-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], double** noalias noundef [[TMP1:%.*]], i32** noalias noundef [[TMP2:%.*]]) #[[ATTR6:[0-9]+]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
+// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca double**, align 8
+// BLOCKS-NEXT: [[DOTADDR2:%.*]] = alloca i32**, align 8
+// BLOCKS-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
+// BLOCKS-NEXT: store double** [[TMP1]], double*** [[DOTADDR1]], align 8
+// BLOCKS-NEXT: store i32** [[TMP2]], i32*** [[DOTADDR2]], align 8
+// BLOCKS-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
+// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0
+// BLOCKS-NEXT: [[TMP5:%.*]] = load double**, double*** [[DOTADDR1]], align 8
+// BLOCKS-NEXT: store double* [[TMP4]], double** [[TMP5]], align 8
+// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1
+// BLOCKS-NEXT: [[TMP7:%.*]] = load i32**, i32*** [[DOTADDR2]], align 8
+// BLOCKS-NEXT: store i32* [[TMP6]], i32** [[TMP7]], align 8
+// BLOCKS-NEXT: ret void
+//
+//
+// BLOCKS-LABEL: define {{[^@]+}}@.omp_task_entry.
+// BLOCKS-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
+// BLOCKS-NEXT: entry:
+// BLOCKS-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
+// BLOCKS-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
+// BLOCKS-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
+// BLOCKS-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
+// BLOCKS-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
+// BLOCKS-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
+// BLOCKS-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
+// BLOCKS-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8
+// BLOCKS-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
+// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca double*, align 8
+// BLOCKS-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca i32*, align 8
+// BLOCKS-NEXT: [[I_I:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: [[BLOCK_I:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8
+// BLOCKS-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// BLOCKS-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// BLOCKS-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// BLOCKS-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// BLOCKS-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
+// BLOCKS-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// BLOCKS-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
+// BLOCKS-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
+// BLOCKS-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
+// BLOCKS-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
+// BLOCKS-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
+// BLOCKS-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
+// BLOCKS-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
+// BLOCKS-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
+// BLOCKS-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5
+// BLOCKS-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8
+// BLOCKS-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6
+// BLOCKS-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8
+// BLOCKS-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7
+// BLOCKS-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8
+// BLOCKS-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8
+// BLOCKS-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8
+// BLOCKS-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9
+// BLOCKS-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8
+// BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
+// BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
+// BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
+// BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
+// BLOCKS-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
+// BLOCKS-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
+// BLOCKS-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, double**, i32**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
+// BLOCKS-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP23:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP24:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP25:%.*]] = bitcast void (i8*, ...)* [[TMP23]] to void (i8*, double**, i32**)*
+// BLOCKS-NEXT: call void [[TMP25]](i8* [[TMP24]], double** [[DOTFIRSTPRIV_PTR_ADDR_I]], i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]]
+// BLOCKS-NEXT: [[TMP26:%.*]] = load double*, double** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// BLOCKS-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP28]] to i32
+// BLOCKS-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// BLOCKS-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
+// BLOCKS: omp.inner.for.cond.i:
+// BLOCKS-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]]
+// BLOCKS-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP29]] to i64
+// BLOCKS-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP30]]
+// BLOCKS-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
+// BLOCKS: omp.inner.for.body.i:
+// BLOCKS-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: store i32 [[TMP31]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: store double 1.000000e+00, double* [[TMP26]], align 8, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: store i32 11, i32* [[TMP27]], align 4, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[BLOCK_ISA_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 0
+// BLOCKS-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[BLOCK_FLAGS_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 1
+// BLOCKS-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[BLOCK_RESERVED_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 2
+// BLOCKS-NEXT: store i32 0, i32* [[BLOCK_RESERVED_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[BLOCK_INVOKE_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 3
+// BLOCKS-NEXT: store i8* bitcast (void (i8*)* @_block_invoke to i8*), i8** [[BLOCK_INVOKE_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[BLOCK_DESCRIPTOR_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 4
+// BLOCKS-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.2 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[BLOCK_CAPTURED_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 5
+// BLOCKS-NEXT: [[TMP32:%.*]] = load volatile double, double* [[TMP26]], align 8, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: store volatile double [[TMP32]], double* [[BLOCK_CAPTURED_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[BLOCK_CAPTURED3_I:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]], i32 0, i32 6
+// BLOCKS-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP27]], align 4, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: store i32 [[TMP33]], i32* [[BLOCK_CAPTURED3_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[TMP34:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK_I]] to void ()*
+// BLOCKS-NEXT: [[BLOCK_LITERAL_I:%.*]] = bitcast void ()* [[TMP34]] to %struct.__block_literal_generic*
+// BLOCKS-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL_I]], i32 0, i32 3
+// BLOCKS-NEXT: [[TMP36:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL_I]] to i8*
+// BLOCKS-NEXT: [[TMP37:%.*]] = load i8*, i8** [[TMP35]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[TMP38:%.*]] = bitcast i8* [[TMP37]] to void (i8*)*
+// BLOCKS-NEXT: call void [[TMP38]](i8* noundef [[TMP36]]) #[[ATTR4]], !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP39]], 1
+// BLOCKS-NEXT: store i32 [[ADD4_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// BLOCKS-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
+// BLOCKS: .omp_outlined..1.exit:
+// BLOCKS-NEXT: ret i32 0
+//
+//
+// ARRAY-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St
+// ARRAY-SAME: (i32 noundef [[N:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] {
+// ARRAY-NEXT: entry:
+// ARRAY-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
+// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8
+// ARRAY-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// ARRAY-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
+// ARRAY-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8
+// ARRAY-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// ARRAY-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// ARRAY-NEXT: [[TMP2:%.*]] = load float*, float** [[A_ADDR]], align 8
+// ARRAY-NEXT: [[TMP3:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8
+// ARRAY-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, float*, %struct.St*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP1]], float* [[TMP2]], %struct.St* [[TMP3]])
+// ARRAY-NEXT: ret void
+//
+//
+// ARRAY-LABEL: define {{[^@]+}}@.omp_outlined.
+// ARRAY-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR1:[0-9]+]] {
+// ARRAY-NEXT: entry:
+// ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
+// ARRAY-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
+// ARRAY-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// ARRAY-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
+// ARRAY-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8
+// ARRAY-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8
+// ARRAY-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// ARRAY-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
+// ARRAY-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// ARRAY-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
+// ARRAY-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8
+// ARRAY-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// ARRAY-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
+// ARRAY-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
+// ARRAY-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
+// ARRAY-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
+// ARRAY-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
+// ARRAY: omp_if.then:
+// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
+// ARRAY-NEXT: store i64 [[TMP0]], i64* [[TMP5]], align 8
+// ARRAY-NEXT: call void @__kmpc_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
+// ARRAY-NEXT: [[TMP6:%.*]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1, i64 96, i64 8, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*))
+// ARRAY-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to %struct.kmp_task_t_with_privates*
+// ARRAY-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP7]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP10:%.*]] = load i8*, i8** [[TMP9]], align 8
+// ARRAY-NEXT: [[TMP11:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
+// ARRAY-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 [[TMP11]], i64 8, i1 false)
+// ARRAY-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP7]], i32 0, i32 1
+// ARRAY-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP12]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP14:%.*]] = load float*, float** [[A_ADDR]], align 8
+// ARRAY-NEXT: store float* [[TMP14]], float** [[TMP13]], align 8
+// ARRAY-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP12]], i32 0, i32 1
+// ARRAY-NEXT: [[TMP16:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8
+// ARRAY-NEXT: store %struct.St* [[TMP16]], %struct.St** [[TMP15]], align 8
+// ARRAY-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 5
+// ARRAY-NEXT: store i64 0, i64* [[TMP17]], align 8
+// ARRAY-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 6
+// ARRAY-NEXT: store i64 9, i64* [[TMP18]], align 8
+// ARRAY-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 7
+// ARRAY-NEXT: store i64 1, i64* [[TMP19]], align 8
+// ARRAY-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP8]], i32 0, i32 9
+// ARRAY-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i8*
+// ARRAY-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP21]], i8 0, i64 8, i1 false)
+// ARRAY-NEXT: [[TMP22:%.*]] = load i64, i64* [[TMP19]], align 8
+// ARRAY-NEXT: call void @__kmpc_taskloop(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i8* [[TMP6]], i32 1, i64* [[TMP17]], i64* [[TMP18]], i64 [[TMP22]], i32 1, i32 0, i64 0, i8* null)
+// ARRAY-NEXT: call void @__kmpc_end_taskgroup(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
+// ARRAY-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
+// ARRAY-NEXT: br label [[OMP_IF_END]]
+// ARRAY: omp_if.end:
+// ARRAY-NEXT: ret void
+//
+//
+// ARRAY-LABEL: define {{[^@]+}}@.omp_task_privates_map.
+// ARRAY-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], float*** noalias noundef [[TMP1:%.*]], %struct.St*** noalias noundef [[TMP2:%.*]]) #[[ATTR4:[0-9]+]] {
+// ARRAY-NEXT: entry:
+// ARRAY-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
+// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca float***, align 8
+// ARRAY-NEXT: [[DOTADDR2:%.*]] = alloca %struct.St***, align 8
+// ARRAY-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
+// ARRAY-NEXT: store float*** [[TMP1]], float**** [[DOTADDR1]], align 8
+// ARRAY-NEXT: store %struct.St*** [[TMP2]], %struct.St**** [[DOTADDR2]], align 8
+// ARRAY-NEXT: [[TMP3:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
+// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP5:%.*]] = load float***, float**** [[DOTADDR1]], align 8
+// ARRAY-NEXT: store float** [[TMP4]], float*** [[TMP5]], align 8
+// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP3]], i32 0, i32 1
+// ARRAY-NEXT: [[TMP7:%.*]] = load %struct.St***, %struct.St**** [[DOTADDR2]], align 8
+// ARRAY-NEXT: store %struct.St** [[TMP6]], %struct.St*** [[TMP7]], align 8
+// ARRAY-NEXT: ret void
+//
+//
+// ARRAY-LABEL: define {{[^@]+}}@.omp_task_entry.
+// ARRAY-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
+// ARRAY-NEXT: entry:
+// ARRAY-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
+// ARRAY-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
+// ARRAY-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
+// ARRAY-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
+// ARRAY-NEXT: [[DOTLB__ADDR_I:%.*]] = alloca i64, align 8
+// ARRAY-NEXT: [[DOTUB__ADDR_I:%.*]] = alloca i64, align 8
+// ARRAY-NEXT: [[DOTST__ADDR_I:%.*]] = alloca i64, align 8
+// ARRAY-NEXT: [[DOTLITER__ADDR_I:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[DOTREDUCTIONS__ADDR_I:%.*]] = alloca i8*, align 8
+// ARRAY-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
+// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca float**, align 8
+// ARRAY-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca %struct.St**, align 8
+// ARRAY-NEXT: [[I_I:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[DOTOMP_IV_I:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
+// ARRAY-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
+// ARRAY-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
+// ARRAY-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// ARRAY-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
+// ARRAY-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
+// ARRAY-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
+// ARRAY-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
+// ARRAY-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
+// ARRAY-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
+// ARRAY-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
+// ARRAY-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
+// ARRAY-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 5
+// ARRAY-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8
+// ARRAY-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 6
+// ARRAY-NEXT: [[TMP15:%.*]] = load i64, i64* [[TMP14]], align 8
+// ARRAY-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 7
+// ARRAY-NEXT: [[TMP17:%.*]] = load i64, i64* [[TMP16]], align 8
+// ARRAY-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 8
+// ARRAY-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 8
+// ARRAY-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 9
+// ARRAY-NEXT: [[TMP21:%.*]] = load i8*, i8** [[TMP20]], align 8
+// ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]])
+// ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]])
+// ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]])
+// ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]])
+// ARRAY-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
+// ARRAY-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !14
+// ARRAY-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, float***, %struct.St***)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i64 [[TMP13]], i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i64 [[TMP15]], i64* [[DOTUB__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i64 [[TMP17]], i64* [[DOTST__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store i32 [[TMP19]], i32* [[DOTLITER__ADDR_I]], align 4, !noalias !14
+// ARRAY-NEXT: store i8* [[TMP21]], i8** [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP22:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP22]], i32 0, i32 0
+// ARRAY-NEXT: [[TMP24:%.*]] = load i64, i64* [[TMP23]], align 8
+// ARRAY-NEXT: [[TMP25:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP26:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP27:%.*]] = bitcast void (i8*, ...)* [[TMP25]] to void (i8*, float***, %struct.St***)*
+// ARRAY-NEXT: call void [[TMP27]](i8* [[TMP26]], float*** [[DOTFIRSTPRIV_PTR_ADDR_I]], %struct.St*** [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]]
+// ARRAY-NEXT: [[TMP28:%.*]] = load float**, float*** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP29:%.*]] = load %struct.St**, %struct.St*** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLB__ADDR_I]], align 8, !noalias !14
+// ARRAY-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP30]] to i32
+// ARRAY-NEXT: store i32 [[CONV_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14
+// ARRAY-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]]
+// ARRAY: omp.inner.for.cond.i:
+// ARRAY-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15:![0-9]+]]
+// ARRAY-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP31]] to i64
+// ARRAY-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTUB__ADDR_I]], align 8, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// ARRAY-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP32]]
+// ARRAY-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
+// ARRAY: omp.inner.for.body.i:
+// ARRAY-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// ARRAY-NEXT: store i32 [[TMP33]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// ARRAY-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// ARRAY-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP34]], 1
+// ARRAY-NEXT: store i32 [[ADD3_I]], i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]]
+// ARRAY-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]]
+// ARRAY: .omp_outlined..1.exit:
+// ARRAY-NEXT: ret i32 0
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@main
+// SIMD-ONLY0-SAME: () #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8
+// SIMD-ONLY0-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8
+// SIMD-ONLY0-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16
+// SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8
+// SIMD-ONLY0-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]])
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00)
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[T_VAR]], align 4
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false)
+// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00)
+// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00)
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00)
+// SIMD-ONLY0-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY0-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY0-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
+// SIMD-ONLY0-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4
+// SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// SIMD-ONLY0: omp.inner.for.cond:
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
+// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
+// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// SIMD-ONLY0: omp.inner.for.body:
+// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY0-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
+// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
+// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[VAR]] to i8*
+// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP6]], i8* align 8 [[TMP7]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY0-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY0-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// SIMD-ONLY0: omp.body.continue:
+// SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// SIMD-ONLY0: omp.inner.for.inc:
+// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
+// SIMD-ONLY0-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
+// SIMD-ONLY0: omp.inner.for.end:
+// SIMD-ONLY0-NEXT: store i32 10, i32* [[I]], align 4
+// SIMD-ONLY0-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
+// SIMD-ONLY0-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]]
+// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// SIMD-ONLY0: arraydestroy.body:
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]
+// SIMD-ONLY0: arraydestroy.done4:
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4
+// SIMD-ONLY0-NEXT: ret i32 [[TMP10]]
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
+// SIMD-ONLY0-SAME: () #[[ATTR3:[0-9]+]] {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
+// SIMD-ONLY0-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4
+// SIMD-ONLY0-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
+// SIMD-ONLY0-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
+// SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
+// SIMD-ONLY0-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]])
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0)
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[T_VAR]], align 128
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
+// SIMD-ONLY0-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
+// SIMD-ONLY0-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
+// SIMD-ONLY0-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY0-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY0-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
+// SIMD-ONLY0-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4
+// SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// SIMD-ONLY0: omp.inner.for.cond:
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
+// SIMD-ONLY0-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
+// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY0-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// SIMD-ONLY0: omp.inner.for.body:
+// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY0-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
+// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8*
+// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[VAR]] to i8*
+// SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY0-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// SIMD-ONLY0: omp.body.continue:
+// SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// SIMD-ONLY0: omp.inner.for.inc:
+// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
+// SIMD-ONLY0-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY0-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// SIMD-ONLY0: omp.inner.for.end:
+// SIMD-ONLY0-NEXT: store i32 10, i32* [[I]], align 4
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// SIMD-ONLY0: arraydestroy.body:
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]
+// SIMD-ONLY0: arraydestroy.done4:
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4
+// SIMD-ONLY0-NEXT: ret i32 [[TMP10]]
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: store double 0.000000e+00, double* [[F]], align 8
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]]
+// SIMD-ONLY0-NEXT: store double [[ADD]], double* [[F]], align 8
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed
+// SIMD-ONLY0-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP0]], double* [[F]], align 8
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[F]], align 4
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
+// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[F]], align 4
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// SIMD-ONLY0-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
+// SIMD-ONLY0-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY0-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@main
+// SIMD-ONLY1-SAME: () #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S:%.*]], align 8
+// SIMD-ONLY1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8
+// SIMD-ONLY1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16
+// SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8
+// SIMD-ONLY1-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// SIMD-ONLY1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// SIMD-ONLY1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]])
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]], double noundef 0.000000e+00)
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[T_VAR]], align 4
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false)
+// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_BEGIN]], double noundef 1.000000e+00)
+// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT]], double noundef 2.000000e+00)
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC1Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]], double noundef 3.000000e+00)
+// SIMD-ONLY1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY1-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
+// SIMD-ONLY1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4
+// SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// SIMD-ONLY1: omp.inner.for.cond:
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
+// SIMD-ONLY1-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
+// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]
+// SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// SIMD-ONLY1: omp.inner.for.body:
+// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
+// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8*
+// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[VAR]] to i8*
+// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP6]], i8* align 8 [[TMP7]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY1-NEXT: store i32 33, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// SIMD-ONLY1: omp.body.continue:
+// SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// SIMD-ONLY1: omp.inner.for.inc:
+// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
+// SIMD-ONLY1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
+// SIMD-ONLY1: omp.inner.for.end:
+// SIMD-ONLY1-NEXT: store i32 10, i32* [[I]], align 4
+// SIMD-ONLY1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
+// SIMD-ONLY1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]]
+// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2
+// SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// SIMD-ONLY1: arraydestroy.body:
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]
+// SIMD-ONLY1: arraydestroy.done4:
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4
+// SIMD-ONLY1-NEXT: ret i32 [[TMP10]]
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ev
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1ERKS0_d
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, double* [[T_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2ERKS0_d(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[TMP0]], double noundef [[TMP1]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC1Ed
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdEC2Ed(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]], double noundef [[TMP0]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
+// SIMD-ONLY1-SAME: () #[[ATTR3:[0-9]+]] {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[TTT:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
+// SIMD-ONLY1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4
+// SIMD-ONLY1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128
+// SIMD-ONLY1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
+// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
+// SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4
+// SIMD-ONLY1-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// SIMD-ONLY1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// SIMD-ONLY1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]])
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]], i32 noundef 0)
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[T_VAR]], align 128
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8*
+// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false)
+// SIMD-ONLY1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
+// SIMD-ONLY1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3)
+// SIMD-ONLY1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY1-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
+// SIMD-ONLY1-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4
+// SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// SIMD-ONLY1: omp.inner.for.cond:
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
+// SIMD-ONLY1-NEXT: [[CONV1:%.*]] = sext i32 [[TMP2]] to i64
+// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP3]]
+// SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// SIMD-ONLY1: omp.inner.for.body:
+// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP4]], 1
+// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0
+// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8*
+// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[VAR]] to i8*
+// SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// SIMD-ONLY1: omp.body.continue:
+// SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// SIMD-ONLY1: omp.inner.for.inc:
+// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
+// SIMD-ONLY1-NEXT: store i32 [[ADD3]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
+// SIMD-ONLY1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
+// SIMD-ONLY1: omp.inner.for.end:
+// SIMD-ONLY1-NEXT: store i32 10, i32* [[I]], align 4
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
+// SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
+// SIMD-ONLY1: arraydestroy.body:
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
+// SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]]
+// SIMD-ONLY1: arraydestroy.done4:
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, i32* [[RETVAL]], align 4
+// SIMD-ONLY1-NEXT: ret i32 [[TMP10]]
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIdED2Ev(%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ev
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: store double 0.000000e+00, double* [[F]], align 8
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2ERKS0_d
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], %struct.S* noundef nonnull align 8 dereferenceable(8) [[S:%.*]], double noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store double [[T]], double* [[T_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, double* [[F2]], align 8
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load double, double* [[T_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[ADD:%.*]] = fadd double [[TMP1]], [[TMP2]]
+// SIMD-ONLY1-NEXT: store double [[ADD]], double* [[F]], align 8
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdEC2Ed
+// SIMD-ONLY1-SAME: (%struct.S* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], double noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
+// SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca double, align 8
+// SIMD-ONLY1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store double [[A]], double* [[A_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load double, double* [[A_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store double [[TMP0]], double* [[F]], align 8
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_i
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2ERKS0_i(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[TMP0]], i32 noundef [[TMP1]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[F]], align 4
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_i
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* noundef nonnull align 4 dereferenceable(4) [[S:%.*]], i32 noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[T_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store i32 [[T]], i32* [[T_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
+// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[F]], align 4
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// SIMD-ONLY1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
+// SIMD-ONLY1-SAME: (%struct.S.0* noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
+// SIMD-ONLY1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: ret void
+//
+//
+// SIMD-ONLY2-LABEL: define {{[^@]+}}@main
+// SIMD-ONLY2-SAME: () #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY2-NEXT: entry:
+// SIMD-ONLY2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
+// SIMD-ONLY2-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
+// SIMD-ONLY2-NEXT: ret i32 0
+//
+//
+// SIMD-ONLY3-LABEL: define {{[^@]+}}@main
+// SIMD-ONLY3-SAME: () #[[ATTR1:[0-9]+]] {
+// SIMD-ONLY3-NEXT: entry:
+// SIMD-ONLY3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// SIMD-ONLY3-NEXT: store i32 0, i32* [[RETVAL]], align 4
+// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8
+// SIMD-ONLY3-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)*
+// SIMD-ONLY3-NEXT: call void [[TMP1]](i8* noundef bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*))
+// SIMD-ONLY3-NEXT: ret i32 0
+//
+//
+// SIMD-ONLY3-LABEL: define {{[^@]+}}@__main_block_invoke
+// SIMD-ONLY3-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
+// SIMD-ONLY3-NEXT: entry:
+// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
+// SIMD-ONLY3-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// SIMD-ONLY3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// SIMD-ONLY3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// SIMD-ONLY3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// SIMD-ONLY3-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY3-NEXT: [[BLOCK2:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, align 8
+// SIMD-ONLY3-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
+// SIMD-ONLY3-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
+// SIMD-ONLY3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY3-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8
+// SIMD-ONLY3-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY3-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
+// SIMD-ONLY3-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4
+// SIMD-ONLY3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// SIMD-ONLY3: omp.inner.for.cond:
+// SIMD-ONLY3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
+// SIMD-ONLY3-NEXT: [[CONV1:%.*]] = sext i32 [[TMP1]] to i64
+// SIMD-ONLY3-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP2]]
+// SIMD-ONLY3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// SIMD-ONLY3: omp.inner.for.body:
+// SIMD-ONLY3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
+// SIMD-ONLY3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// SIMD-ONLY3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: store double 1.000000e+00, double* @g, align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: store i32 11, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 0
+// SIMD-ONLY3-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 1
+// SIMD-ONLY3-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 2
+// SIMD-ONLY3-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 3
+// SIMD-ONLY3-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 4
+// SIMD-ONLY3-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 5
+// SIMD-ONLY3-NEXT: [[TMP4:%.*]] = load volatile double, double* @g, align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: store volatile double [[TMP4]], double* [[BLOCK_CAPTURED]], align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]], i32 0, i32 6
+// SIMD-ONLY3-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: store i32 [[TMP5]], i32* [[BLOCK_CAPTURED3]], align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[TMP6:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK2]] to void ()*
+// SIMD-ONLY3-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP6]] to %struct.__block_literal_generic*
+// SIMD-ONLY3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3
+// SIMD-ONLY3-NEXT: [[TMP8:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8*
+// SIMD-ONLY3-NEXT: [[TMP9:%.*]] = load i8*, i8** [[TMP7]], align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to void (i8*)*
+// SIMD-ONLY3-NEXT: call void [[TMP10]](i8* noundef [[TMP8]]), !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// SIMD-ONLY3: omp.body.continue:
+// SIMD-ONLY3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// SIMD-ONLY3: omp.inner.for.inc:
+// SIMD-ONLY3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
+// SIMD-ONLY3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
+// SIMD-ONLY3: omp.inner.for.end:
+// SIMD-ONLY3-NEXT: store i32 10, i32* [[I]], align 4
+// SIMD-ONLY3-NEXT: ret void
+//
+//
+// SIMD-ONLY3-LABEL: define {{[^@]+}}@__main_block_invoke_2
+// SIMD-ONLY3-SAME: (i8* noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
+// SIMD-ONLY3-NEXT: entry:
+// SIMD-ONLY3-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*, align 8
+// SIMD-ONLY3-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>*
+// SIMD-ONLY3-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>** [[BLOCK_ADDR]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 5
+// SIMD-ONLY3-NEXT: store double 2.000000e+00, double* [[BLOCK_CAPTURE_ADDR]], align 8
+// SIMD-ONLY3-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, double, i32 }>* [[BLOCK]], i32 0, i32 6
+// SIMD-ONLY3-NEXT: store i32 22, i32* [[BLOCK_CAPTURE_ADDR1]], align 8
+// SIMD-ONLY3-NEXT: ret void
+//
+//
+// SIMD-ONLY4-LABEL: define {{[^@]+}}@_Z10array_funciPfP2St
+// SIMD-ONLY4-SAME: (i32 noundef [[N:%.*]], float* noundef [[A:%.*]], %struct.St* noundef [[S:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY4-NEXT: entry:
+// SIMD-ONLY4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8
+// SIMD-ONLY4-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8
+// SIMD-ONLY4-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// SIMD-ONLY4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
+// SIMD-ONLY4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
+// SIMD-ONLY4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// SIMD-ONLY4-NEXT: [[I:%.*]] = alloca i32, align 4
+// SIMD-ONLY4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8
+// SIMD-ONLY4-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8
+// SIMD-ONLY4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// SIMD-ONLY4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY4-NEXT: store i64 9, i64* [[DOTOMP_UB]], align 8
+// SIMD-ONLY4-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
+// SIMD-ONLY4-NEXT: [[CONV:%.*]] = trunc i64 [[TMP2]] to i32
+// SIMD-ONLY4-NEXT: store i32 [[CONV]], i32* [[DOTOMP_IV]], align 4
+// SIMD-ONLY4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
+// SIMD-ONLY4: omp.inner.for.cond:
+// SIMD-ONLY4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
+// SIMD-ONLY4-NEXT: [[CONV1:%.*]] = sext i32 [[TMP3]] to i64
+// SIMD-ONLY4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY4-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV1]], [[TMP4]]
+// SIMD-ONLY4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// SIMD-ONLY4: omp.inner.for.body:
+// SIMD-ONLY4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1
+// SIMD-ONLY4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// SIMD-ONLY4-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// SIMD-ONLY4: omp.body.continue:
+// SIMD-ONLY4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// SIMD-ONLY4: omp.inner.for.inc:
+// SIMD-ONLY4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
+// SIMD-ONLY4-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
+// SIMD-ONLY4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
+// SIMD-ONLY4: omp.inner.for.end:
+// SIMD-ONLY4-NEXT: store i32 10, i32* [[I]], align 4
+// SIMD-ONLY4-NEXT: ret void
+//
diff --git a/clang/test/OpenMP/target_firstprivate_codegen.cpp b/clang/test/OpenMP/target_firstprivate_codegen.cpp
index 4f8f5ae37472c..05a6e891204f2 100644
--- a/clang/test/OpenMP/target_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/target_firstprivate_codegen.cpp
@@ -1,38 +1,37 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
// Test host codegen.
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK0
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
-// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
+// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK1
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK2
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
-// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
+// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK3
// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
-// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
+// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY01 %s
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY02 %s
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
-// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}
+// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY03 %s
// Test target codegen - host bc file has to be created first.
// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
-// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64
+// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK1
// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK2
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
-// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32
+// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK3
// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
-// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
+// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY11 %s
// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
-// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s
+// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY12 %s
// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
-// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
-// SIMD-ONLY1-NOT: {{__kmpc|__tgt}}
+// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY13 %s
// expected-no-diagnostics
#ifndef HEADER
@@ -47,28 +46,9 @@ struct TT {
int ga = 5;
#pragma omp end declare target
-// CHECK-DAG: [[TT:%.+]] = type { i64, i8 }
-// CHECK-DAG: [[TTII:%.+]] = type { i32, i32 }
-// CHECK-DAG: [[S1:%.+]] = type { double }
-
-// TCHECK-DAG: [[TT:%.+]] = type { i64, i8 }
-// TCHECK-DAG: [[TTII:%.+]] = type { i32, i32 }
-// TCHECK-DAG: [[S1:%.+]] = type { double }
-
-// CHECK-DAG: [[SIZET:@.+]] = private unnamed_addr constant [3 x i{{32|64}}] [i[[SZ:32|64]] 4, i{{64|32}} {{8|4}}, i[[SZ:32|64]] 4]
-// CHECK-DAG: [[MAPT:@.+]] = private unnamed_addr constant [3 x i64] [i64 288, i64 49, i64 288]
-// CHECK-DAG: [[SIZET2:@.+]] = private unnamed_addr constant [9 x i64] [i64 2, i64 40, i64 {{4|8}}, i64 0, i64 400, i64 {{4|8}}, i64 {{4|8}}, i64 0, i64 {{12|16}}]
-// CHECK-DAG: [[MAPT2:@.+]] = private unnamed_addr constant [9 x i64] [i64 288, i64 161, i64 800, i64 161, i64 161, i64 800, i64 800, i64 161, i64 161]
-// CHECK-DAG: [[SIZET3:@.+]] = private unnamed_addr constant [2 x i{{32|64}}] [i{{32|64}} 0, i{{32|64}} 8]
-// CHECK-DAG: [[MAPT3:@.+]] = private unnamed_addr constant [2 x i64] [i64 32, i64 161]
-// CHECK-DAG: [[SIZET4:@.+]] = private unnamed_addr constant [5 x i64] [i64 8, i64 4, i64 {{4|8}}, i64 {{4|8}}, i64 0]
-// CHECK-DAG: [[MAPT4:@.+]] = private unnamed_addr constant [5 x i64] [i64 547, i64 288, i64 800, i64 800, i64 161]
-// CHECK-DAG: [[SIZET5:@.+]] = private unnamed_addr constant [3 x i{{32|64}}] [i[[SZ]] 4, i[[SZ]] 1, i[[SZ]] 40]
-// CHECK-DAG: [[MAPT5:@.+]] = private unnamed_addr constant [3 x i64] [i64 288, i64 288, i64 161]
-// CHECK-DAG: [[SIZET6:@.+]] = private unnamed_addr constant [2 x i{{32|64}}] [i[[SZ]] 4, i[[SZ]] 40]
-// CHECK-DAG: [[MAPT6:@.+]] = private unnamed_addr constant [2 x i64] [i64 288, i64 161]
-
-// CHECK: define {{.*}}[[FOO:@.+]](
+
+
+
int foo(int n, double *ptr) {
int a = 0;
short aa = 0;
@@ -85,75 +65,7 @@ int foo(int n, double *ptr) {
}
// a is passed by value to tgt_target
- // CHECK: [[N_ADDR:%.+]] = alloca i{{[0-9]+}},
- // CHECK: [[PTR_ADDR:%.+]] = alloca double*,
- // CHECK: [[A:%.+]] = alloca i{{[0-9]+}},
- // CHECK: [[A2:%.+]] = alloca i{{[0-9]+}},
- // CHECK: [[B:%.+]] = alloca [10 x float],
- // CHECK: [[SSTACK:%.+]] = alloca i8*,
- // CHECK: [[C:%.+]] = alloca [5 x [10 x double]],
- // CHECK: [[D:%.+]] = alloca [[TT]],
- // CHECK: [[FP_E:%.+]] = alloca [[TTII]],
- // CHECK: [[P:%.+]] = alloca i32*, align 64
- // CHECK: [[ACAST:%.+]] = alloca i{{[0-9]+}},
- // CHECK: [[BASE_PTR_ARR:%.+]] = alloca [3 x i8*],
- // CHECK: [[PTR_ARR:%.+]] = alloca [3 x i8*],
- // CHECK: [[A2CAST:%.+]] = alloca i{{[0-9]+}},
- // CHECK: [[BASE_PTR_ARR2:%.+]] = alloca [9 x i8*],
- // CHECK: [[PTR_ARR2:%.+]] = alloca [9 x i8*],
- // CHECK: [[SIZET2:%.+]] = alloca [9 x i{{[0-9]+}}],
- // CHECK: [[BASE_PTR_ARR3:%.+]] = alloca [2 x i8*],
- // CHECK: [[PTR_ARR3:%.+]] = alloca [2 x i8*],
- // CHECK: [[N_ADDR_VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[N_ADDR]],
- // CHECK-64: [[N_EXT:%.+]] = zext i{{[0-9]+}} [[N_ADDR_VAL]] to i{{[0-9]+}}
- // CHECK: [[SSAVE_RET:%.+]] = call i8* @llvm.stacksave()
- // CHECK: store i8* [[SSAVE_RET]], i8** [[SSTACK]],
- // CHECK-64: [[BN_VLA:%.+]] = alloca float, i{{[0-9]+}} [[N_EXT]],
- // CHECK-32: [[BN_VLA:%.+]] = alloca float, i{{[0-9]+}} [[N_ADDR_VAL]],
- // CHECK: [[N_ADDR_VAL2:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[N_ADDR]],
- // CHECK-64: [[N_EXT2:%.+]] = zext i{{[0-9]+}} [[N_ADDR_VAL2]] to i{{[0-9]+}}
- // CHECK-64: [[CN_SIZE:%.+]] = mul{{.+}} i{{[0-9]+}} 5, [[N_EXT2]]
- // CHECK-32: [[CN_SIZE:%.+]] = mul{{.+}} i{{[0-9]+}} 5, [[N_ADDR_VAL2]]
- // CHECK: [[CN_VLA:%.+]] = alloca double, i{{[0-9]+}} [[CN_SIZE]],
- // CHECK: [[AVAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[A]],
- // CHECK-64: [[CONV:%.+]] = bitcast i{{[0-9]+}}* [[ACAST]] to i{{[0-9]+}}*
- // CHECK-64: store i{{[0-9]+}} [[AVAL]], i{{[0-9]+}}* [[CONV]],
- // CHECK-32: store i{{[0-9]+}} [[AVAL]], i{{[0-9]+}}* [[ACAST]],
- // CHECK: [[ACAST_VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[ACAST]],
- // CHECK: [[P_PTR:%.+]] = load i32*, i32** [[P]], align 64
- // CHECK: [[BASE_PTR_GEP:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BASE_PTR_ARR]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[ACAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[ACAST_VAL]], i{{[0-9]+}}* [[ACAST_TOPTR]],
- // CHECK: [[PTR_GEP:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[PTR_ARR]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[ACAST_TOPTR2:%.+]] = bitcast i8** [[PTR_GEP]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[ACAST_VAL]], i{{[0-9]+}}* [[ACAST_TOPTR2]],
- // CHECK: [[BASE_PTR_GEP:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BASE_PTR_ARR]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
- // CHECK: [[PCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP]] to i32***
- // CHECK: store i32** [[P]], i32*** [[PCAST_TOPTR]],
- // CHECK: [[PTR_GEP:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[PTR_ARR]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
- // CHECK: [[PCAST_TOPTR2:%.+]] = bitcast i8** [[PTR_GEP]] to i32**
- // CHECK: store i32* [[P_PTR]], i32** [[PCAST_TOPTR2]],
- // CHECK: [[BASE_PTR_GEP:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BASE_PTR_ARR]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
- // CHECK: [[PCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP]] to i{{64|32}}*
- // CHECK: store i{{64|32}} [[GA_VAL:%.*]], i{{64|32}}* [[PCAST_TOPTR]],
- // CHECK: [[PTR_GEP:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[PTR_ARR]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
- // CHECK: [[PCAST_TOPTR2:%.+]] = bitcast i8** [[PTR_GEP]] to i{{64|32}}*
- // CHECK: store i{{64|32}} [[GA_VAL]], i{{64|32}}* [[PCAST_TOPTR2]],
- // CHECK: [[BASE_PTR_GEP_ARG:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BASE_PTR_ARR]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[PTR_GEP_ARG:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[PTR_ARR]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: {{.+}} = call i32 @__tgt_target_kernel(%struct.ident_t* @{{.+}}, i64 -1, i32 -1, i32 0, i8* @.{{.+}}.region_id, %struct.__tgt_kernel_arguments* [[ARGS:%.+]])
-
- // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], i32** noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[P_IN:%.+]], i{{[0-9]+}} noundef [[GA_IN:%.+]])
- // TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}},
- // TCHECK: [[P_ADDR:%.+]] = alloca i32**,
- // TCHECK: [[GA_ADDR:%.+]] = alloca i{{64|32}},
- // TCHECK: [[P_PRIV:%.+]] = alloca i32*,
- // TCHECK-NOT: alloca i{{[0-9]+}}
- // TCHECK: store i{{[0-9]+}} [[A_IN]], i{{[0-9]+}}* [[A_ADDR]],
- // TCHECK: store i32** [[P_IN]], i32*** [[P_ADDR]],
- // TCHECK: store i{{[0-9]+}} [[GA_IN]], i{{[0-9]+}}* [[GA_ADDR]],
- // TCHECK-NOT: store i{{[0-9]+}} %
- // TCHECK: ret void
+
#pragma omp target firstprivate(aa, b, bn, c, cn, d)
{
@@ -166,198 +78,44 @@ int foo(int n, double *ptr) {
d.Y = 1;
}
- // CHECK: [[A2VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[A2]],
- // CHECK: [[A2CASTCONV:%.+]] = bitcast i{{[0-9]+}}* [[A2CAST]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[A2VAL]], i{{[0-9]+}}* [[A2CASTCONV]],
- // CHECK: [[A2CAST_VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[A2CAST]],
- // CHECK-64: [[BN_SIZE:%.+]] = mul{{.+}} i{{[0-9]+}} [[N_EXT]], 4
- // CHECK-32: [[BN_SZ_SIZE:%.+]] = mul{{.+}} i{{[0-9]+}} [[N_ADDR_VAL]], 4
- // CHECK-32: [[BN_SIZE:%.+]] = sext i32 [[BN_SZ_SIZE]] to i64
- // CHECK-64: [[CN_SIZE_1:%.+]] = mul{{.+}} i{{[0-9]+}} 5, [[N_EXT2]]
- // CHECK-32: [[CN_SIZE_1:%.+]] = mul{{.+}} i{{[0-9]+}} 5, [[N_ADDR_VAL2]]
- // CHECK-64: [[CN_SIZE_2:%.+]] = mul{{.+}} i{{[0-9]+}} [[CN_SIZE_1]], 8
- // CHECK-32: [[CN_SZ_SIZE_2:%.+]] = mul{{.+}} i{{[0-9]+}} [[CN_SIZE_1]], 8
- // CHECK-32: [[CN_SIZE_2:%.+]] = sext i32 [[CN_SZ_SIZE_2]] to i64
// firstprivate(aa) --> base_ptr = aa, ptr = aa, size = 2 (short)
- // CHECK: [[BASE_PTR_GEP2_0:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BASE_PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[ACAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP2_0]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[A2CAST_VAL]], i{{[0-9]+}}* [[ACAST_TOPTR]],
- // CHECK: [[PTR_GEP2_0:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[ACAST_TOPTR:%.+]] = bitcast i8** [[PTR_GEP2_0]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[A2CAST_VAL]], i{{[0-9]+}}* [[ACAST_TOPTR]],
// firstprivate(b): base_ptr = &b[0], ptr = &b[0], size = 40 (sizeof(float)*10)
- // CHECK: [[BASE_PTR_GEP2_1:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BASE_PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP2_1]] to [10 x float]**
- // CHECK: store [10 x float]* [[B]], [10 x float]** [[BCAST_TOPTR]],
- // CHECK: [[PTR_GEP2_1:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTR_GEP2_1]] to [10 x float]**
- // CHECK: store [10 x float]* [[B]], [10 x float]** [[BCAST_TOPTR]],
// firstprivate(bn), 2 entries, n and bn: (1) base_ptr = n, ptr = n, size = 8 ; (2) base_ptr = &c[0], ptr = &c[0], size = n*sizeof(float)
- // CHECK: [[BASE_PTR_GEP2_2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BASE_PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP2_2]] to i{{[0-9]+}}*
- // CHECK-64: store i{{[0-9]+}} [[N_EXT]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK-32: store i{{[0-9]+}} [[N_ADDR_VAL]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[PTR_GEP2_2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTR_GEP2_2]] to i{{[0-9]+}}*
- // CHECK-64: store i{{[0-9]+}} [[N_EXT]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK-32: store i{{[0-9]+}} [[N_ADDR_VAL]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[BASE_PTR_GEP2_3:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BASE_PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 3
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP2_3]] to float**
- // CHECK: store float* [[BN_VLA]], float** [[BCAST_TOPTR]],
- // CHECK: [[SIZE_GEPBN_3:%.+]] = getelementptr inbounds [9 x i{{[0-9]+}}], [9 x i{{[0-9]+}}]* [[SIZET2]], i{{[0-9]+}} 0, i{{[0-9]+}} 3
- // CHECK: store i{{[0-9]+}} [[BN_SIZE]], i{{[0-9]+}}* [[SIZE_GEPBN_3]]
// firstprivate(c): base_ptr = &c[0], ptr = &c[0], size = 400 (5*10*sizeof(double))
- // CHECK: [[BASE_PTR_GEP2_4:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BASE_PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 4
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP2_4]] to [5 x [10 x double]]**
- // CHECK: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[BCAST_TOPTR]],
- // CHECK: [[PTR_GEP2_4:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 4
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTR_GEP2_4]] to [5 x [10 x double]]**
- // CHECK: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[BCAST_TOPTR]],
// firstprivate(cn), 3 entries, 5, n, cn: (1) base_ptr = 5, ptr = 5, size = 8; (2) (1) base_ptr = n, ptr = n, size = 8; (3) base_ptr = &cn[0], ptr = &cn[0], size = 5*n*sizeof(double)
- // CHECK: [[BASE_PTR_GEP2_5:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BASE_PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 5
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP2_5]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} 5, i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[PTR_GEP2_5:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 5
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTR_GEP2_5]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} 5, i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[BASE_PTR_GEP2_6:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BASE_PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 6
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP2_6]] to i{{[0-9]+}}*
- // CHECK-64: store i{{[0-9]+}} [[N_EXT2]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK-32: store i{{[0-9]+}} [[N_ADDR_VAL2]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[PTR_GEP2_6:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 6
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTR_GEP2_6]] to i{{[0-9]+}}*
- // CHECK-64: store i{{[0-9]+}} [[N_EXT2]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK-32: store i{{[0-9]+}} [[N_ADDR_VAL2]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[BASE_PTR_GEP2_7:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BASE_PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 7
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP2_7]] to double**
- // CHECK: store double* [[CN_VLA]], double** [[BCAST_TOPTR]],
- // CHECK: [[PTR_GEP2_7:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 7
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTR_GEP2_7]] to double**
- // CHECK: store double* [[CN_VLA]], double** [[BCAST_TOPTR]],
- // CHECK: [[SIZE_GEPCN_7:%.+]] = getelementptr inbounds [9 x i{{[0-9]+}}], [9 x i{{[0-9]+}}]* [[SIZET2]], i{{[0-9]+}} 0, i{{[0-9]+}} 7
- // CHECK: store i{{[0-9]+}} [[CN_SIZE_2]], i{{[0-9]+}}* [[SIZE_GEPCN_7]],
// firstprivate(d): base_ptr = &d, ptr = &d, size = 16
- // CHECK: [[BASE_PTR_GEP2_8:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BASE_PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 8
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP2_8]] to [[TT]]**
- // CHECK: store [[TT]]* [[D]], [[TT]]** [[BCAST_TOPTR]],
- // CHECK: [[PTR_GEP2_8:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 8
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTR_GEP2_8]] to [[TT]]**
- // CHECK: store [[TT]]* [[D]], [[TT]]** [[BCAST_TOPTR]],
-
- // CHECK: [[BASE_PTR_GEP_ARG2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BASE_PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[PTR_GEP_ARG2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[PTR_ARR2]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[SIZES_ARG2:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[SIZET2]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: {{.+}} = call i32 @__tgt_target_kernel(%struct.ident_t* @{{.+}}, i64 -1, i32 -1, i32 0, i8* @.{{.+}}.region_id, %struct.__tgt_kernel_arguments* [[ARGS:%.+]])
+
// make sure that firstprivate variables are generated in all cases and that we use those instances for operations inside the
// target region
- // TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A2_IN:%.+]], [10 x float]* {{.+}} [[B_IN:%.+]], i{{[0-9]+}} noundef [[BN_SZ:%.+]], float* {{.+}} [[BN_IN:%.+]], [5 x [10 x double]]* {{.+}} [[C_IN:%.+]], i{{[0-9]+}} noundef [[CN_SZ1:%.+]], i{{[0-9]+}} noundef [[CN_SZ2:%.+]], double* {{.+}} [[CN_IN:%.+]], [[TT]]* {{.+}} [[D_IN:%.+]])
- // TCHECK: [[A2_ADDR:%.+]] = alloca i{{[0-9]+}},
- // TCHECK: [[B_ADDR:%.+]] = alloca [10 x float]*,
- // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}},
- // TCHECK: [[BN_ADDR:%.+]] = alloca float*,
- // TCHECK: [[C_ADDR:%.+]] = alloca [5 x [10 x double]]*,
- // TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}},
- // TCHECK: [[VLA_ADDR4:%.+]] = alloca i{{[0-9]+}},
- // TCHECK: [[CN_ADDR:%.+]] = alloca double*,
- // TCHECK: [[D_ADDR:%.+]] = alloca [[TT]]*,
- // TCHECK-NOT: alloca i{{[0-9]+}},
- // TCHECK: [[B_PRIV:%.+]] = alloca [10 x float],
- // TCHECK: [[SSTACK:%.+]] = alloca i8*,
- // TCHECK: [[C_PRIV:%.+]] = alloca [5 x [10 x double]],
- // TCHECK: [[D_PRIV:%.+]] = alloca [[TT]],
- // TCHECK: store i{{[0-9]+}} [[A2_IN]], i{{[0-9]+}}* [[A2_ADDR]],
- // TCHECK: store [10 x float]* [[B_IN]], [10 x float]** [[B_ADDR]],
- // TCHECK: store i{{[0-9]+}} [[BN_SZ]], i{{[0-9]+}}* [[VLA_ADDR]],
- // TCHECK: store float* [[BN_IN]], float** [[BN_ADDR]],
- // TCHECK: store [5 x [10 x double]]* [[C_IN]], [5 x [10 x double]]** [[C_ADDR]],
- // TCHECK: store i{{[0-9]+}} [[CN_SZ1]], i{{[0-9]+}}* [[VLA_ADDR2]],
- // TCHECK: store i{{[0-9]+}} [[CN_SZ2]], i{{[0-9]+}}* [[VLA_ADDR4]],
- // TCHECK: store double* [[CN_IN]], double** [[CN_ADDR]],
- // TCHECK: store [[TT]]* [[D_IN]], [[TT]]** [[D_ADDR]],
- // TCHECK: [[CONV_A2ADDR:%.+]] = bitcast i{{[0-9]+}}* [[A2_ADDR]] to i{{[0-9]+}}*
- // TCHECK: [[B_ADDR_REF:%.+]] = load [10 x float]*, [10 x float]** [[B_ADDR]],
- // TCHECK: [[BN_SZ_VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[VLA_ADDR]],
- // TCHECK: [[BN_ADDR_REF:%.+]] = load float*, float** [[BN_ADDR]],
- // TCHECK: [[C_ADDR_REF:%.+]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]],
- // TCHECK: [[CN_SZ1_VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[VLA_ADDR2]],
- // TCHECK: [[CN_SZ2_VAL:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[VLA_ADDR4]],
- // TCHECK: [[CN_ADDR_REF:%.+]] = load double*, double** [[CN_ADDR]],
- // TCHECK: [[D_ADDR_REF:%.+]] = load [[TT]]*, [[TT]]** [[D_ADDR]],
// firstprivate(aa): a_priv = a_in
- // TCHECK-NOT: store i{{[0-9]+}} %
// firstprivate(b): memcpy(b_priv,b_in)
- // TCHECK: [[B_PRIV_BCAST:%.+]] = bitcast [10 x float]* [[B_PRIV]] to i8*
- // TCHECK: [[B_ADDR_REF_BCAST:%.+]] = bitcast [10 x float]* [[B_ADDR_REF]] to i8*
- // TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[B_PRIV_BCAST]], i8* align {{[0-9]+}} [[B_ADDR_REF_BCAST]], {{.+}})
- // TCHECK: [[RET_STACK:%.+]] = call i8* @llvm.stacksave()
- // TCHECK: store i8* [[RET_STACK]], i8** [[SSTACK]],
// firstprivate(bn)
- // TCHECK: [[BN_PRIV:%.+]] = alloca float, i{{[0-9]+}} [[BN_SZ_VAL]],
- // TCHECK: [[BN_COPY_SZ:%.+]] = mul{{.+}} i{{[0-9]+}} [[BN_SZ_VAL]], 4
- // TCHECK: [[BN_PRIV__BCAST:%.+]] = bitcast float* [[BN_PRIV]] to i8*
- // TCHECK: [[BN_REF_IN_BCAST:%.+]] = bitcast float* [[BN_ADDR_REF]] to i8*
- // TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[BN_PRIV__BCAST]], i8* align {{[0-9]+}} [[BN_REF_IN_BCAST]], i{{[0-9]+}} [[BN_COPY_SZ]],{{.+}})
// firstprivate(c)
- // TCHECK: [[C_PRIV_BCAST:%.+]] = bitcast [5 x [10 x double]]* [[C_PRIV]] to i8*
- // TCHECK: [[C_IN_BCAST:%.+]] = bitcast [5 x [10 x double]]* [[C_ADDR_REF]] to i8*
- // TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[C_PRIV_BCAST]], i8* align {{[0-9]+}} [[C_IN_BCAST]],{{.+}})
// firstprivate(cn)
- // TCHECK: [[CN_SZ:%.+]] = mul{{.+}} i{{[0-9]+}} [[CN_SZ1_VAL]], [[CN_SZ2_VAL]]
- // TCHECK: [[CN_PRIV:%.+]] = alloca double, i{{[0-9]+}} [[CN_SZ]],
- // TCHECK: [[CN_SZ2:%.+]] = mul{{.+}} i{{[0-9]+}} [[CN_SZ1_VAL]], [[CN_SZ2_VAL]]
- // TCHECK: [[CN_SZ2_CPY:%.+]] = mul{{.+}} i{{[0-9]+}} [[CN_SZ2]], 8
- // TCHECK: [[CN_PRIV_BCAST:%.+]] = bitcast double* [[CN_PRIV]] to i8*
- // TCHECK: [[CN_IN_BCAST:%.+]] = bitcast double* [[CN_ADDR_REF]] to i8*
- // TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[CN_PRIV_BCAST]], i8* align {{[0-9]+}} [[CN_IN_BCAST]], i{{[0-9]+}} [[CN_SZ2_CPY]],{{.+}})
// firstprivate(d)
- // TCHECK: [[D_PRIV_BCAST:%.+]] = bitcast [[TT]]* [[D_PRIV]] to i8*
- // TCHECK: [[D_IN_BCAST:%.+]] = bitcast [[TT]]* [[D_ADDR_REF]] to i8*
- // TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[D_PRIV_BCAST]], i8* align {{[0-9]+}} [[D_IN_BCAST]],{{.+}})
#pragma omp target firstprivate(ptr, e)
{
ptr[0] = e.X;
ptr[0]++;
}
- // CHECK: [[PTR_ADDR_REF:%.+]] = load double*, double** [[PTR_ADDR]],
-
- // CHECK: [[BASE_PTR_GEP3_0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BASE_PTR_ARR3]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP3_0]] to double**
- // CHECK: store double* [[PTR_ADDR_REF]], double** [[BCAST_TOPTR]],
- // CHECK: [[PTR_GEP3_0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[PTR_ARR3]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTR_GEP3_0]] to double**
- // CHECK: store double* [[PTR_ADDR_REF]], double** [[BCAST_TOPTR]],
- // CHECK: [[BASE_PTR_GEP3_1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BASE_PTR_ARR3]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTR_GEP3_1]] to [[TTII]]**
- // CHECK: store [[TTII]]* [[FP_E]], [[TTII]]** [[BCAST_TOPTR]],
- // CHECK: [[PTR_GEP3_1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[PTR_ARR3]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTR_GEP3_1]] to [[TTII]]**
- // CHECK: store [[TTII]]* [[FP_E]], [[TTII]]** [[BCAST_TOPTR]],
-
- // CHECK: [[BASE_PTR_GEP_ARG3:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BASE_PTR_ARR3]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[PTR_GEP_ARG3:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[PTR_ARR3]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: {{.+}} = call i32 @__tgt_target_kernel(%struct.ident_t* @{{.+}}, i64 -1, i32 -1, i32 0, i8* @.{{.+}}.region_id, %struct.__tgt_kernel_arguments* [[ARGS:%.+]])
-
- // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(double* noundef [[PTR_IN:%.+]], [[TTII]]* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[E:%.+]])
- // TCHECK: [[PTR_ADDR:%.+]] = alloca double*,
- // TCHECK-NOT: alloca [[TTII]],
- // TCHECK-NOT: alloca double*,
- // TCHECK: store double* [[PTR_IN]], double** [[PTR_ADDR]],
- // TCHECK-NOT: store double* %
+
+
+
return a;
}
@@ -391,30 +149,13 @@ static int fstatic(int n) {
return a;
}
-// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], i{{[0-9]+}} noundef [[A3_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]])
-// TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}},
-// TCHECK: [[A3_ADDR:%.+]] = alloca i{{[0-9]+}},
-// TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*,
-// TCHECK-NOT: alloca i{{[0-9]+}},
-// TCHECK: [[B_PRIV:%.+]] = alloca [10 x i{{[0-9]+}}],
-// TCHECK: store i{{[0-9]+}} [[A_IN]], i{{[0-9]+}}* [[A_ADDR]],
-// TCHECK: store i{{[0-9]+}} [[A3_IN]], i{{[0-9]+}}* [[A3_ADDR]],
-// TCHECK: store [10 x i{{[0-9]+}}]* [[B_IN]], [10 x i{{[0-9]+}}]** [[B_ADDR]],
-// TCHECK-64: [[A_CONV:%.+]] = bitcast i{{[0-9]+}}* [[A_ADDR]] to i{{[0-9]+}}*
-// TCHECK: [[A3_CONV:%.+]] = bitcast i{{[0-9]+}}* [[A3_ADDR]] to i8*
-// TCHECK: [[B_ADDR_REF:%.+]] = load [10 x i{{[0-9]+}}]*, [10 x i{{[0-9]+}}]** [[B_ADDR]],
// firstprivate(a): a_priv = a_in
// firstprivate(aaa)
-// TCHECK-NOT: store i{{[0-9]+}} %
// firstprivate(b)
-// TCHECK: [[B_PRIV_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_PRIV]] to i8*
-// TCHECK: [[B_IN_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_ADDR_REF]] to i8*
-// TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[B_PRIV_BCAST]], i8* align {{[0-9]+}} [[B_IN_BCAST]],{{.+}})
-// TCHECK: ret void
struct S1 {
double a;
@@ -433,123 +174,33 @@ struct S1 {
}
// on the host side, we first generate r1, then the static function and the template above
- // CHECK: define{{.+}} i32 {{.+}}([[S1]]* {{.+}}, i{{[0-9]+}} {{.+}})
- // CHECK: [[BASE_PTRS4:%.+]] = alloca [5 x i8*],
- // CHECK: [[PTRS4:%.+]] = alloca [5 x i8*],
- // CHECK: [[SIZET4:%.+]] = alloca [5 x i{{[0-9]+}}],
// map(this: this ptr is implicitly captured (not firstprivate matter)
- // CHECK: [[BP0:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BASE_PTRS4]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[CBP0:%.+]] = bitcast i8** [[BP0]] to %struct.S1**
- // CHECK: store %struct.S1* [[THIS:%.+]], %struct.S1** [[CBP0]],
- // CHECK: [[P0:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[PTRS4]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[CP0:%.+]] = bitcast i8** [[P0]] to double**
- // CHECK: store double* [[A:%.+]], double** [[CP0]],
// firstprivate(b): base_ptr = b, ptr = b, size = 4 (pass by-value)
- // CHECK: [[BASE_PTRS_GEP4_1:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BASE_PTRS4]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTRS_GEP4_1]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[B_CAST:%.+]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[PTRS_GEP4_1:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[PTRS4]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTRS_GEP4_1]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[B_CAST]], i{{[0-9]+}}* [[BCAST_TOPTR]],
// firstprivate(c), 3 entries: 2, n, c
- // CHECK: [[BASE_PTRS_GEP4_2:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BASE_PTRS4]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTRS_GEP4_2]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} 2, i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[PTRS_GEP4_2:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[PTRS4]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTRS_GEP4_2]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} 2, i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[BASE_PTRS_GEP4_3:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BASE_PTRS4]], i{{[0-9]+}} 0, i{{[0-9]+}} 3
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTRS_GEP4_3]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[N:%.+]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[PTRS_GEP4_3:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[PTRS4]], i{{[0-9]+}} 0, i{{[0-9]+}} 3
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTRS_GEP4_3]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[N]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[BASE_PTRS_GEP4_4:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BASE_PTRS4]], i{{[0-9]+}} 0, i{{[0-9]+}} 4
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTRS_GEP4_4]] to i{{[0-9]+}}**
- // CHECK: store i{{[0-9]+}}* [[B:%.+]], i{{[0-9]+}}** [[BCAST_TOPTR]],
- // CHECK: [[PTRS_GEP4_4:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[PTRS4]], i{{[0-9]+}} 0, i{{[0-9]+}} 4
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTRS_GEP4_4]] to i{{[0-9]+}}**
- // CHECK: store i{{[0-9]+}}* [[B]], i{{[0-9]+}}** [[BCAST_TOPTR]],
- // CHECK: [[SIZES_GEP4_4:%.+]] = getelementptr inbounds [5 x i{{[0-9]+}}], [5 x i{{[0-9]+}}]* [[SIZET4]], i{{[0-9]+}} 0, i{{[0-9]+}} 4
- // CHECK: store i{{[0-9]+}} [[B_SIZE:%.+]], i{{[0-9]+}}* [[SIZES_GEP4_4]],
// only check that we use the map types stored in the global variable
- // CHECK: {{.+}} = call i32 @__tgt_target_kernel(%struct.ident_t* @{{.+}}, i64 -1, i32 -1, i32 0, i8* @.{{.+}}.region_id, %struct.__tgt_kernel_arguments* [[ARGS:%.+]])
-
- // TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}([[S1]]* noundef [[TH:%.+]], i{{[0-9]+}} noundef [[B_IN:%.+]], i{{[0-9]+}} noundef [[VLA:%.+]], i{{[0-9]+}} noundef [[VLA1:%.+]], i{{[0-9]+}}{{.+}} [[C_IN:%.+]])
- // TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*,
- // TCHECK: [[B_ADDR:%.+]] = alloca i{{[0-9]+}},
- // TCHECK: [[VLA_ADDR:%.+]] = alloca i{{[0-9]+}},
- // TCHECK: [[VLA_ADDR2:%.+]] = alloca i{{[0-9]+}},
- // TCHECK: [[C_ADDR:%.+]] = alloca i{{[0-9]+}}*,
- // TCHECK-NOT: alloca i{{[0-9]+}},
- // TCHECK: [[SSTACK:%.+]] = alloca i8*,
-
- // TCHECK: store [[S1]]* [[TH]], [[S1]]** [[TH_ADDR]],
- // TCHECK: store i{{[0-9]+}} [[B_IN]], i{{[0-9]+}}* [[B_ADDR]],
- // TCHECK: store i{{[0-9]+}} [[VLA]], i{{[0-9]+}}* [[VLA_ADDR]],
- // TCHECK: store i{{[0-9]+}} [[VLA1]], i{{[0-9]+}}* [[VLA_ADDR2]],
- // TCHECK: store i{{[0-9]+}}* [[C_IN]], i{{[0-9]+}}** [[C_ADDR]],
- // TCHECK: [[TH_ADDR_REF:%.+]] = load [[S1]]*, [[S1]]** [[TH_ADDR]],
- // TCHECK-64: [[B_ADDR_CONV:%.+]] = bitcast i{{[0-9]+}}* [[B_ADDR]] to i{{[0-9]+}}*
- // TCHECK: [[VLA_ADDR_REF:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[VLA_ADDR]],
- // TCHECK: [[VLA_ADDR_REF2:%.+]] = load i{{[0-9]+}}, i{{[0-9]+}}* [[VLA_ADDR2]],
- // TCHECK: [[C_ADDR_REF:%.+]] = load i{{[0-9]+}}*, i{{[0-9]+}}** [[C_ADDR]],
+
+
// firstprivate(b)
- // TCHECK-NOT: store i{{[0-9]+}} %
- // TCHECK: [[RET_STACK:%.+]] = call i8* @llvm.stacksave()
- // TCHECK: store i8* [[RET_STACK:%.+]], i8** [[SSTACK]],
// firstprivate(c)
- // TCHECK: [[C_SZ:%.+]] = mul{{.+}} i{{[0-9]+}} [[VLA_ADDR_REF]], [[VLA_ADDR_REF2]]
- // TCHECK: [[C_PRIV:%.+]] = alloca i{{[0-9]+}}, i{{[0-9]+}} [[C_SZ]],
- // TCHECK: [[C_SZ2:%.+]] = mul{{.+}} i{{[0-9]+}} [[VLA_ADDR_REF]], [[VLA_ADDR_REF2]]
- // TCHECK: [[C_SZ_CPY:%.+]] = mul{{.+}} i{{[0-9]+}} [[C_SZ2]], 2
- // TCHECK: [[C_PRIV_BCAST:%.+]] = bitcast i{{[0-9]+}}* [[C_PRIV]] to i8*
- // TCHECK: [[C_IN_BCAST:%.+]] = bitcast i{{[0-9]+}}* [[C_ADDR_REF]] to i8*
- // TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[C_PRIV_BCAST]], i8* align {{[0-9]+}} [[C_IN_BCAST]],{{.+}})
// finish
- // TCHECK: [[RELOAD_SSTACK:%.+]] = load i8*, i8** [[SSTACK]],
- // TCHECK: call void @llvm.stackrestore(i8* [[RELOAD_SSTACK]])
- // TCHECK: ret void
// static host function
- // CHECK: define{{.+}} i32 {{.+}}(i{{[0-9]+}} {{.+}})
- // CHECK: [[BASE_PTRS5:%.+]] = alloca [3 x i8*],
- // CHECK: [[PTRS5:%.+]] = alloca [3 x i8*],
// firstprivate(a): by value
- // CHECK: [[BASE_PTRS_GEP5_0:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BASE_PTRS5]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTRS_GEP5_0]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[A_CAST:%.+]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[PTRS_GEP5_0:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[PTRS5]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTRS_GEP5_0]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[A_CAST]], i{{[0-9]+}}* [[BCAST_TOPTR]],
// firstprivate(aaa): by value
- // CHECK: [[BASE_PTRS_GEP5_1:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BASE_PTRS5]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTRS_GEP5_1]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[A3_CAST:%.+]], i{{[0-9]+}}* [[BCAST_TOPTR]],
- // CHECK: [[PTRS_GEP5_1:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[PTRS5]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTRS_GEP5_1]] to i{{[0-9]+}}*
- // CHECK: store i{{[0-9]+}} [[A3_CAST]], i{{[0-9]+}}* [[BCAST_TOPTR]],
// firstprivate(b): base_ptr = &b[0], ptr= &b[0]
- // CHECK: [[BASE_PTRS_GEP5_2:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BASE_PTRS5]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTRS_GEP5_2]] to [10 x i{{[0-9]+}}]**
- // CHECK: store [10 x i{{[0-9]+}}]* [[B:%.+]], [10 x i{{[0-9]+}}]** [[BCAST_TOPTR]],
- // CHECK: [[PTRS_GEP5_2:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[PTRS5]], i{{[0-9]+}} 0, i{{[0-9]+}} 2
- // CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTRS_GEP5_2]] to [10 x i{{[0-9]+}}]**
- // CHECK: store [10 x i{{[0-9]+}}]* [[B]], [10 x i{{[0-9]+}}]** [[BCAST_TOPTR]],
// only check that the right sizes and map types are used
- // CHECK: {{.+}} = call i32 @__tgt_target_kernel(%struct.ident_t* @{{.+}}, i64 -1, i32 -1, i32 0, i8* @.{{.+}}.region_id, %struct.__tgt_kernel_arguments* [[ARGS:%.+]])
};
int bar(int n, double *ptr) {
@@ -565,46 +216,11786 @@ int bar(int n, double *ptr) {
// template host and device
-// CHECK: define{{.+}} i32 {{.+}}(i{{[0-9]+}} {{.+}})
-// CHECK: [[BASE_PTRS6:%.+]] = alloca [2 x i8*],
-// CHECK: [[PTRS6:%.+]] = alloca [2 x i8*],
// firstprivate(a): by value
-// CHECK: [[BASE_PTRS_GEP6_0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BASE_PTRS6]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTRS_GEP6_0]] to i{{[0-9]+}}*
-// CHECK: store i{{[0-9]+}} [[AT_CAST:%.+]], i{{[0-9]+}}* [[BCAST_TOPTR]],
-// CHECK: [[PTRS_GEP6_0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[PTRS6]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
-// CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTRS_GEP6_0]] to i{{[0-9]+}}*
-// CHECK: store i{{[0-9]+}} [[AT_CAST]], i{{[0-9]+}}* [[BCAST_TOPTR]],
// firstprivate(b): pointer
-// CHECK: [[BASE_PTRS_GEP6_1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BASE_PTRS6]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
-// CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[BASE_PTRS_GEP6_1]] to [10 x i{{[0-9]+}}]**
-// CHECK: store [10 x i{{[0-9]+}}]* [[B:%.+]], [10 x i{{[0-9]+}}]** [[BCAST_TOPTR]],
-// CHECK: [[PTRS_GEP6_1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[PTRS6]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
-// CHECK: [[BCAST_TOPTR:%.+]] = bitcast i8** [[PTRS_GEP6_1]] to [10 x i{{[0-9]+}}]**
-// CHECK: store [10 x i{{[0-9]+}}]* [[B]], [10 x i{{[0-9]+}}]** [[BCAST_TOPTR]],
-
-// CHECK: {{.+}} = call i32 @__tgt_target_kernel(%struct.ident_t* @{{.+}}, i64 -1, i32 -1, i32 0, i8* @.{{.+}}.region_id, %struct.__tgt_kernel_arguments* [[ARGS:%.+]])
-
-// TCHECK: define weak_odr protected void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]])
-// TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}},
-// TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*,
-// TCHECK-NOT: alloca i{{[0-9]+}},
-// TCHECK: [[B_PRIV:%.+]] = alloca [10 x i{{[0-9]+}}],
-// TCHECK: store i{{[0-9]+}} [[A_IN]], i{{[0-9]+}}* [[A_ADDR]],
-// TCHECK: store [10 x i{{[0-9]+}}]* [[B_IN]], [10 x i{{[0-9]+}}]** [[B_ADDR]],
-// TCHECK-64: [[A_ADDR_CONV:%.+]] = bitcast i{{[0-9]+}}* [[A_ADDR]] to i{{[0-9]+}}*
-// TCHECK: [[B_ADDR_REF:%.+]] = load [10 x i{{[0-9]+}}]*, [10 x i{{[0-9]+}}]** [[B_ADDR]],
+
+
// firstprivate(a)
-// TCHECK-NOT: store i{{[0-9]+}} %
// firstprivate(b)
-// TCHECK: [[B_PRIV_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_PRIV]] to i8*
-// TCHECK: [[B_IN_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_ADDR_REF]] to i8*
-// TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[B_PRIV_BCAST]], i8* align {{[0-9]+}} [[B_IN_BCAST]],{{.+}})
-// TCHECK: ret void
#endif
+// CHECK-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CHECK-SAME: () #[[ATTR5:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: call void @__tgt_register_requires(i64 1)
+// CHECK-NEXT: ret void
+// CHECK-64-LABEL: define {{[^@]+}}@_Z3fooiPd
+// CHECK-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[AA:%.*]] = alloca i16, align 2
+// CHECK-64-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// CHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// CHECK-64-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK-64-NEXT: [[P:%.*]] = alloca i32*, align 64
+// CHECK-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
+// CHECK-64-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [9 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [9 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [9 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
+// CHECK-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK-64-NEXT: store i16 0, i16* [[AA]], align 2
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK-64-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// CHECK-64-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
+// CHECK-64-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
+// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// CHECK-64-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
+// CHECK-64-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
+// CHECK-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// CHECK-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: store i32 [[TMP6]], i32* [[X]], align 4
+// CHECK-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4
+// CHECK-64-NEXT: store i32* [[A]], i32** [[P]], align 64
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK-64-NEXT: store i32 [[TMP8]], i32* [[CONV]], align 4
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32*, i32** [[P]], align 64
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, i32* @ga, align 4
+// CHECK-64-NEXT: [[CONV2:%.*]] = bitcast i64* [[GA_CASTED]] to i32*
+// CHECK-64-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4
+// CHECK-64-NEXT: [[TMP12:%.*]] = load i64, i64* [[GA_CASTED]], align 8
+// CHECK-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP9]], i64* [[TMP14]], align 8
+// CHECK-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP9]], i64* [[TMP16]], align 8
+// CHECK-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK-64-NEXT: store i8* null, i8** [[TMP17]], align 8
+// CHECK-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
+// CHECK-64-NEXT: store i32* [[TMP10]], i32** [[TMP19]], align 8
+// CHECK-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**
+// CHECK-64-NEXT: store i32* [[TMP10]], i32** [[TMP21]], align 8
+// CHECK-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK-64-NEXT: store i8* null, i8** [[TMP22]], align 8
+// CHECK-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK-64-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP12]], i64* [[TMP24]], align 8
+// CHECK-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP12]], i64* [[TMP26]], align 8
+// CHECK-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK-64-NEXT: store i8* null, i8** [[TMP27]], align 8
+// CHECK-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK-64-NEXT: store i32 2, i32* [[TMP30]], align 4
+// CHECK-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK-64-NEXT: store i32 3, i32* [[TMP31]], align 4
+// CHECK-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK-64-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8
+// CHECK-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK-64-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 8
+// CHECK-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP34]], align 8
+// CHECK-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP35]], align 8
+// CHECK-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP36]], align 8
+// CHECK-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP37]], align 8
+// CHECK-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK-64-NEXT: store i64 0, i64* [[TMP38]], align 8
+// CHECK-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK-64-NEXT: store i64 0, i64* [[TMP39]], align 8
+// CHECK-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP40]], align 4
+// CHECK-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP41]], align 4
+// CHECK-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK-64-NEXT: store i32 0, i32* [[TMP42]], align 4
+// CHECK-64-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK-64-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
+// CHECK-64-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK-64: omp_offload.failed:
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], i32* [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]]
+// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK-64: omp_offload.cont:
+// CHECK-64-NEXT: [[TMP45:%.*]] = load i16, i16* [[AA]], align 2
+// CHECK-64-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
+// CHECK-64-NEXT: store i16 [[TMP45]], i16* [[CONV3]], align 2
+// CHECK-64-NEXT: [[TMP46:%.*]] = load i64, i64* [[AA_CASTED]], align 8
+// CHECK-64-NEXT: [[TMP47:%.*]] = mul nuw i64 [[TMP1]], 4
+// CHECK-64-NEXT: [[TMP48:%.*]] = mul nuw i64 5, [[TMP4]]
+// CHECK-64-NEXT: [[TMP49:%.*]] = mul nuw i64 [[TMP48]], 8
+// CHECK-64-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i64 72, i1 false)
+// CHECK-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP46]], i64* [[TMP52]], align 8
+// CHECK-64-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP46]], i64* [[TMP54]], align 8
+// CHECK-64-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
+// CHECK-64-NEXT: store i8* null, i8** [[TMP55]], align 8
+// CHECK-64-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**
+// CHECK-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 8
+// CHECK-64-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**
+// CHECK-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 8
+// CHECK-64-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
+// CHECK-64-NEXT: store i8* null, i8** [[TMP60]], align 8
+// CHECK-64-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2
+// CHECK-64-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP62]], align 8
+// CHECK-64-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2
+// CHECK-64-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP64]], align 8
+// CHECK-64-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2
+// CHECK-64-NEXT: store i8* null, i8** [[TMP65]], align 8
+// CHECK-64-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3
+// CHECK-64-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**
+// CHECK-64-NEXT: store float* [[VLA]], float** [[TMP67]], align 8
+// CHECK-64-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3
+// CHECK-64-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**
+// CHECK-64-NEXT: store float* [[VLA]], float** [[TMP69]], align 8
+// CHECK-64-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
+// CHECK-64-NEXT: store i64 [[TMP47]], i64* [[TMP70]], align 8
+// CHECK-64-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 3
+// CHECK-64-NEXT: store i8* null, i8** [[TMP71]], align 8
+// CHECK-64-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 4
+// CHECK-64-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**
+// CHECK-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 8
+// CHECK-64-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 4
+// CHECK-64-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**
+// CHECK-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 8
+// CHECK-64-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 4
+// CHECK-64-NEXT: store i8* null, i8** [[TMP76]], align 8
+// CHECK-64-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 5
+// CHECK-64-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
+// CHECK-64-NEXT: store i64 5, i64* [[TMP78]], align 8
+// CHECK-64-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 5
+// CHECK-64-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*
+// CHECK-64-NEXT: store i64 5, i64* [[TMP80]], align 8
+// CHECK-64-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 5
+// CHECK-64-NEXT: store i8* null, i8** [[TMP81]], align 8
+// CHECK-64-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 6
+// CHECK-64-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP4]], i64* [[TMP83]], align 8
+// CHECK-64-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 6
+// CHECK-64-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP4]], i64* [[TMP85]], align 8
+// CHECK-64-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 6
+// CHECK-64-NEXT: store i8* null, i8** [[TMP86]], align 8
+// CHECK-64-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 7
+// CHECK-64-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**
+// CHECK-64-NEXT: store double* [[VLA1]], double** [[TMP88]], align 8
+// CHECK-64-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 7
+// CHECK-64-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**
+// CHECK-64-NEXT: store double* [[VLA1]], double** [[TMP90]], align 8
+// CHECK-64-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
+// CHECK-64-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 8
+// CHECK-64-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 7
+// CHECK-64-NEXT: store i8* null, i8** [[TMP92]], align 8
+// CHECK-64-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 8
+// CHECK-64-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**
+// CHECK-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 8
+// CHECK-64-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 8
+// CHECK-64-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**
+// CHECK-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 8
+// CHECK-64-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 8
+// CHECK-64-NEXT: store i8* null, i8** [[TMP97]], align 8
+// CHECK-64-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK-64-NEXT: [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK-64-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 0
+// CHECK-64-NEXT: store i32 2, i32* [[TMP101]], align 4
+// CHECK-64-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 1
+// CHECK-64-NEXT: store i32 9, i32* [[TMP102]], align 4
+// CHECK-64-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 2
+// CHECK-64-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 8
+// CHECK-64-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 3
+// CHECK-64-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 8
+// CHECK-64-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 4
+// CHECK-64-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 8
+// CHECK-64-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 5
+// CHECK-64-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 8
+// CHECK-64-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 6
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP107]], align 8
+// CHECK-64-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 7
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP108]], align 8
+// CHECK-64-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 8
+// CHECK-64-NEXT: store i64 0, i64* [[TMP109]], align 8
+// CHECK-64-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 9
+// CHECK-64-NEXT: store i64 0, i64* [[TMP110]], align 8
+// CHECK-64-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 10
+// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4
+// CHECK-64-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 11
+// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4
+// CHECK-64-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 12
+// CHECK-64-NEXT: store i32 0, i32* [[TMP113]], align 4
+// CHECK-64-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]])
+// CHECK-64-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0
+// CHECK-64-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
+// CHECK-64: omp_offload.failed8:
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP46]], [10 x float]* [[B]], i64 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP4]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
+// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT9]]
+// CHECK-64: omp_offload.cont9:
+// CHECK-64-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**
+// CHECK-64-NEXT: store double* [[TMP116]], double** [[TMP118]], align 8
+// CHECK-64-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**
+// CHECK-64-NEXT: store double* [[TMP116]], double** [[TMP120]], align 8
+// CHECK-64-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
+// CHECK-64-NEXT: store i8* null, i8** [[TMP121]], align 8
+// CHECK-64-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**
+// CHECK-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 8
+// CHECK-64-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**
+// CHECK-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 8
+// CHECK-64-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
+// CHECK-64-NEXT: store i8* null, i8** [[TMP126]], align 8
+// CHECK-64-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CHECK-64-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK-64-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0
+// CHECK-64-NEXT: store i32 2, i32* [[TMP129]], align 4
+// CHECK-64-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1
+// CHECK-64-NEXT: store i32 2, i32* [[TMP130]], align 4
+// CHECK-64-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2
+// CHECK-64-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 8
+// CHECK-64-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3
+// CHECK-64-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 8
+// CHECK-64-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4
+// CHECK-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 8
+// CHECK-64-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5
+// CHECK-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 8
+// CHECK-64-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP135]], align 8
+// CHECK-64-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP136]], align 8
+// CHECK-64-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8
+// CHECK-64-NEXT: store i64 0, i64* [[TMP137]], align 8
+// CHECK-64-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 9
+// CHECK-64-NEXT: store i64 0, i64* [[TMP138]], align 8
+// CHECK-64-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 10
+// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4
+// CHECK-64-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 11
+// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4
+// CHECK-64-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 12
+// CHECK-64-NEXT: store i32 0, i32* [[TMP141]], align 4
+// CHECK-64-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]])
+// CHECK-64-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0
+// CHECK-64-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
+// CHECK-64: omp_offload.failed14:
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]
+// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT15]]
+// CHECK-64: omp_offload.cont15:
+// CHECK-64-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-64-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])
+// CHECK-64-NEXT: ret i32 [[TMP144]]
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// CHECK-64-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8
+// CHECK-64-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK-64-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8
+// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*
+// CHECK-64-NEXT: ret void
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// CHECK-64-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
+// CHECK-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
+// CHECK-64-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
+// CHECK-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
+// CHECK-64-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
+// CHECK-64-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// CHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// CHECK-64-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
+// CHECK-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// CHECK-64-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
+// CHECK-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// CHECK-64-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
+// CHECK-64-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
+// CHECK-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
+// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
+// CHECK-64-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// CHECK-64-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)
+// CHECK-64-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// CHECK-64-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8
+// CHECK-64-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
+// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK-64-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4
+// CHECK-64-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// CHECK-64-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)
+// CHECK-64-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// CHECK-64-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)
+// CHECK-64-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// CHECK-64-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8
+// CHECK-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// CHECK-64-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8
+// CHECK-64-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// CHECK-64-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8
+// CHECK-64-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// CHECK-64-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)
+// CHECK-64-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// CHECK-64-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)
+// CHECK-64-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// CHECK-64-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// CHECK-64-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK-64-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2
+// CHECK-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// CHECK-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3
+// CHECK-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// CHECK-64-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1
+// CHECK-64-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2
+// CHECK-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// CHECK-64-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]
+// CHECK-64-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]
+// CHECK-64-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
+// CHECK-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// CHECK-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// CHECK-64-NEXT: store i64 1, i64* [[X]], align 8
+// CHECK-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// CHECK-64-NEXT: store i8 1, i8* [[Y]], align 8
+// CHECK-64-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// CHECK-64-NEXT: ret void
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// CHECK-64-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK-64-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8
+// CHECK-64-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*
+// CHECK-64-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*
+// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 8, i1 false)
+// CHECK-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double
+// CHECK-64-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i64 0
+// CHECK-64-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8
+// CHECK-64-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 0
+// CHECK-64-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 8
+// CHECK-64-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// CHECK-64-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 8
+// CHECK-64-NEXT: ret void
+// CHECK-64-LABEL: define {{[^@]+}}@_Z3bariPd
+// CHECK-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
+// CHECK-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK-64-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// CHECK-64-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// CHECK-64-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// CHECK-64-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// CHECK-64-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-64-NEXT: ret i32 [[TMP9]]
+// CHECK-64-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// CHECK-64-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// CHECK-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[B:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
+// CHECK-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// CHECK-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// CHECK-64-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+// CHECK-64-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
+// CHECK-64-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
+// CHECK-64-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
+// CHECK-64-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
+// CHECK-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
+// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
+// CHECK-64-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
+// CHECK-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 2
+// CHECK-64-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP9]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i64 40, i1 false)
+// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
+// CHECK-64-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
+// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
+// CHECK-64-NEXT: store double* [[A]], double** [[TMP13]], align 8
+// CHECK-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK-64-NEXT: store i8* null, i8** [[TMP14]], align 8
+// CHECK-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP6]], i64* [[TMP16]], align 8
+// CHECK-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP6]], i64* [[TMP18]], align 8
+// CHECK-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK-64-NEXT: store i8* null, i8** [[TMP19]], align 8
+// CHECK-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
+// CHECK-64-NEXT: store i64 2, i64* [[TMP21]], align 8
+// CHECK-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK-64-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
+// CHECK-64-NEXT: store i64 2, i64* [[TMP23]], align 8
+// CHECK-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK-64-NEXT: store i8* null, i8** [[TMP24]], align 8
+// CHECK-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP2]], i64* [[TMP26]], align 8
+// CHECK-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK-64-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP2]], i64* [[TMP28]], align 8
+// CHECK-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
+// CHECK-64-NEXT: store i8* null, i8** [[TMP29]], align 8
+// CHECK-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
+// CHECK-64-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**
+// CHECK-64-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 8
+// CHECK-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
+// CHECK-64-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**
+// CHECK-64-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 8
+// CHECK-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
+// CHECK-64-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 8
+// CHECK-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
+// CHECK-64-NEXT: store i8* null, i8** [[TMP35]], align 8
+// CHECK-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK-64-NEXT: store i32 2, i32* [[TMP39]], align 4
+// CHECK-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK-64-NEXT: store i32 5, i32* [[TMP40]], align 4
+// CHECK-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK-64-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 8
+// CHECK-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK-64-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8
+// CHECK-64-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK-64-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 8
+// CHECK-64-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK-64-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 8
+// CHECK-64-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP45]], align 8
+// CHECK-64-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP46]], align 8
+// CHECK-64-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK-64-NEXT: store i64 0, i64* [[TMP47]], align 8
+// CHECK-64-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK-64-NEXT: store i64 0, i64* [[TMP48]], align 8
+// CHECK-64-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4
+// CHECK-64-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4
+// CHECK-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK-64-NEXT: store i32 0, i32* [[TMP51]], align 4
+// CHECK-64-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK-64-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0
+// CHECK-64-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK-64: omp_offload.failed:
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
+// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK-64: omp_offload.cont:
+// CHECK-64-NEXT: [[TMP54:%.*]] = mul nsw i64 1, [[TMP2]]
+// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP54]]
+// CHECK-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// CHECK-64-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
+// CHECK-64-NEXT: [[CONV3:%.*]] = sext i16 [[TMP55]] to i32
+// CHECK-64-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4
+// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP56]]
+// CHECK-64-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])
+// CHECK-64-NEXT: ret i32 [[ADD4]]
+// CHECK-64-LABEL: define {{[^@]+}}@_ZL7fstatici
+// CHECK-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// CHECK-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
+// CHECK-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK-64-NEXT: store i8 0, i8* [[AAA]], align 1
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
+// CHECK-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
+// CHECK-64-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK-64-NEXT: store i8* null, i8** [[TMP8]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
+// CHECK-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
+// CHECK-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK-64-NEXT: store i8* null, i8** [[TMP13]], align 8
+// CHECK-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK-64-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**
+// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 8
+// CHECK-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK-64-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**
+// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 8
+// CHECK-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK-64-NEXT: store i8* null, i8** [[TMP18]], align 8
+// CHECK-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK-64-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK-64-NEXT: store i32 3, i32* [[TMP22]], align 4
+// CHECK-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK-64-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 8
+// CHECK-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK-64-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8
+// CHECK-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 8
+// CHECK-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 8
+// CHECK-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP27]], align 8
+// CHECK-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP28]], align 8
+// CHECK-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK-64-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK-64-NEXT: store i64 0, i64* [[TMP30]], align 8
+// CHECK-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4
+// CHECK-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4
+// CHECK-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK-64-NEXT: store i32 0, i32* [[TMP33]], align 4
+// CHECK-64-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK-64-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
+// CHECK-64-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK-64: omp_offload.failed:
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK-64: omp_offload.cont:
+// CHECK-64-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-64-NEXT: ret i32 [[TMP36]]
+// CHECK-64-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// CHECK-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
+// CHECK-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
+// CHECK-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
+// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK-64-NEXT: store i8* null, i8** [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**
+// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
+// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 8
+// CHECK-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK-64-NEXT: store i8* null, i8** [[TMP11]], align 8
+// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK-64-NEXT: store i32 2, i32* [[TMP14]], align 4
+// CHECK-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK-64-NEXT: store i32 2, i32* [[TMP15]], align 4
+// CHECK-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK-64-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 8
+// CHECK-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK-64-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 8
+// CHECK-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 8
+// CHECK-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 8
+// CHECK-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP20]], align 8
+// CHECK-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK-64-NEXT: store i8** null, i8*** [[TMP21]], align 8
+// CHECK-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK-64-NEXT: store i64 0, i64* [[TMP22]], align 8
+// CHECK-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK-64-NEXT: store i64 0, i64* [[TMP23]], align 8
+// CHECK-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4
+// CHECK-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4
+// CHECK-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK-64-NEXT: store i32 0, i32* [[TMP26]], align 4
+// CHECK-64-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK-64-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
+// CHECK-64-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK-64: omp_offload.failed:
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK-64: omp_offload.cont:
+// CHECK-64-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-64-NEXT: ret i32 [[TMP29]]
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// CHECK-64-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// CHECK-64-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
+// CHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// CHECK-64-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
+// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// CHECK-64-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
+// CHECK-64-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// CHECK-64-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
+// CHECK-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
+// CHECK-64-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// CHECK-64-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK-64-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double
+// CHECK-64-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
+// CHECK-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK-64-NEXT: store double [[ADD]], double* [[A]], align 8
+// CHECK-64-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK-64-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8
+// CHECK-64-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// CHECK-64-NEXT: store double [[INC]], double* [[A5]], align 8
+// CHECK-64-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
+// CHECK-64-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]
+// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]
+// CHECK-64-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// CHECK-64-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
+// CHECK-64-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// CHECK-64-NEXT: ret void
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// CHECK-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// CHECK-64-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
+// CHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
+// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
+// CHECK-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*
+// CHECK-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
+// CHECK-64-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32
+// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
+// CHECK-64-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
+// CHECK-64-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1
+// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1
+// CHECK-64-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
+// CHECK-64-NEXT: ret void
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// CHECK-64-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// CHECK-64-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// CHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK-64-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// CHECK-64-NEXT: ret void
+// CHECK-64-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CHECK-64-SAME: () #[[ATTR5:[0-9]+]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: call void @__tgt_register_requires(i64 1)
+// CHECK-64-NEXT: ret void
+// CHECK-32-LABEL: define {{[^@]+}}@_Z3fooiPd
+// CHECK-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[AA:%.*]] = alloca i16, align 2
+// CHECK-32-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// CHECK-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// CHECK-32-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK-32-NEXT: [[P:%.*]] = alloca i32*, align 64
+// CHECK-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
+// CHECK-32-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 4
+// CHECK-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK-32-NEXT: store i16 0, i16* [[AA]], align 2
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
+// CHECK-32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
+// CHECK-32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
+// CHECK-32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
+// CHECK-32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
+// CHECK-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// CHECK-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[TMP4]], i32* [[X]], align 4
+// CHECK-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4
+// CHECK-32-NEXT: store i32* [[A]], i32** [[P]], align 64
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-32-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32*, i32** [[P]], align 64
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, i32* @ga, align 4
+// CHECK-32-NEXT: store i32 [[TMP9]], i32* [[GA_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[GA_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP7]], i32* [[TMP12]], align 4
+// CHECK-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP7]], i32* [[TMP14]], align 4
+// CHECK-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK-32-NEXT: store i8* null, i8** [[TMP15]], align 4
+// CHECK-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32**
+// CHECK-32-NEXT: store i32* [[TMP8]], i32** [[TMP17]], align 4
+// CHECK-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
+// CHECK-32-NEXT: store i32* [[TMP8]], i32** [[TMP19]], align 4
+// CHECK-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK-32-NEXT: store i8* null, i8** [[TMP20]], align 4
+// CHECK-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP10]], i32* [[TMP22]], align 4
+// CHECK-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP10]], i32* [[TMP24]], align 4
+// CHECK-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK-32-NEXT: store i8* null, i8** [[TMP25]], align 4
+// CHECK-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK-32-NEXT: store i32 2, i32* [[TMP28]], align 4
+// CHECK-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK-32-NEXT: store i32 3, i32* [[TMP29]], align 4
+// CHECK-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK-32-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 4
+// CHECK-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK-32-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4
+// CHECK-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP32]], align 4
+// CHECK-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP33]], align 4
+// CHECK-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP34]], align 4
+// CHECK-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP35]], align 4
+// CHECK-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK-32-NEXT: store i64 0, i64* [[TMP36]], align 8
+// CHECK-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK-32-NEXT: store i64 0, i64* [[TMP37]], align 8
+// CHECK-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP38]], align 4
+// CHECK-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP39]], align 4
+// CHECK-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK-32-NEXT: store i32 0, i32* [[TMP40]], align 4
+// CHECK-32-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK-32-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0
+// CHECK-32-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK-32: omp_offload.failed:
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], i32* [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]]
+// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK-32: omp_offload.cont:
+// CHECK-32-NEXT: [[TMP43:%.*]] = load i16, i16* [[AA]], align 2
+// CHECK-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
+// CHECK-32-NEXT: store i16 [[TMP43]], i16* [[CONV]], align 2
+// CHECK-32-NEXT: [[TMP44:%.*]] = load i32, i32* [[AA_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP45:%.*]] = mul nuw i32 [[TMP0]], 4
+// CHECK-32-NEXT: [[TMP46:%.*]] = sext i32 [[TMP45]] to i64
+// CHECK-32-NEXT: [[TMP47:%.*]] = mul nuw i32 5, [[TMP2]]
+// CHECK-32-NEXT: [[TMP48:%.*]] = mul nuw i32 [[TMP47]], 8
+// CHECK-32-NEXT: [[TMP49:%.*]] = sext i32 [[TMP48]] to i64
+// CHECK-32-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i32 72, i1 false)
+// CHECK-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP44]], i32* [[TMP52]], align 4
+// CHECK-32-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP44]], i32* [[TMP54]], align 4
+// CHECK-32-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
+// CHECK-32-NEXT: store i8* null, i8** [[TMP55]], align 4
+// CHECK-32-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**
+// CHECK-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 4
+// CHECK-32-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**
+// CHECK-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 4
+// CHECK-32-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
+// CHECK-32-NEXT: store i8* null, i8** [[TMP60]], align 4
+// CHECK-32-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP0]], i32* [[TMP62]], align 4
+// CHECK-32-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP0]], i32* [[TMP64]], align 4
+// CHECK-32-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2
+// CHECK-32-NEXT: store i8* null, i8** [[TMP65]], align 4
+// CHECK-32-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 3
+// CHECK-32-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**
+// CHECK-32-NEXT: store float* [[VLA]], float** [[TMP67]], align 4
+// CHECK-32-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 3
+// CHECK-32-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**
+// CHECK-32-NEXT: store float* [[VLA]], float** [[TMP69]], align 4
+// CHECK-32-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
+// CHECK-32-NEXT: store i64 [[TMP46]], i64* [[TMP70]], align 4
+// CHECK-32-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 3
+// CHECK-32-NEXT: store i8* null, i8** [[TMP71]], align 4
+// CHECK-32-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 4
+// CHECK-32-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**
+// CHECK-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 4
+// CHECK-32-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 4
+// CHECK-32-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**
+// CHECK-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 4
+// CHECK-32-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 4
+// CHECK-32-NEXT: store i8* null, i8** [[TMP76]], align 4
+// CHECK-32-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 5
+// CHECK-32-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32*
+// CHECK-32-NEXT: store i32 5, i32* [[TMP78]], align 4
+// CHECK-32-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 5
+// CHECK-32-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*
+// CHECK-32-NEXT: store i32 5, i32* [[TMP80]], align 4
+// CHECK-32-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 5
+// CHECK-32-NEXT: store i8* null, i8** [[TMP81]], align 4
+// CHECK-32-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 6
+// CHECK-32-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP2]], i32* [[TMP83]], align 4
+// CHECK-32-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 6
+// CHECK-32-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP2]], i32* [[TMP85]], align 4
+// CHECK-32-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 6
+// CHECK-32-NEXT: store i8* null, i8** [[TMP86]], align 4
+// CHECK-32-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 7
+// CHECK-32-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**
+// CHECK-32-NEXT: store double* [[VLA1]], double** [[TMP88]], align 4
+// CHECK-32-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 7
+// CHECK-32-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**
+// CHECK-32-NEXT: store double* [[VLA1]], double** [[TMP90]], align 4
+// CHECK-32-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
+// CHECK-32-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 4
+// CHECK-32-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 7
+// CHECK-32-NEXT: store i8* null, i8** [[TMP92]], align 4
+// CHECK-32-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 8
+// CHECK-32-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**
+// CHECK-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 4
+// CHECK-32-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 8
+// CHECK-32-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**
+// CHECK-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 4
+// CHECK-32-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 8
+// CHECK-32-NEXT: store i8* null, i8** [[TMP97]], align 4
+// CHECK-32-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK-32-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK-32-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 0
+// CHECK-32-NEXT: store i32 2, i32* [[TMP101]], align 4
+// CHECK-32-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 1
+// CHECK-32-NEXT: store i32 9, i32* [[TMP102]], align 4
+// CHECK-32-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 2
+// CHECK-32-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 4
+// CHECK-32-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 3
+// CHECK-32-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 4
+// CHECK-32-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 4
+// CHECK-32-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 4
+// CHECK-32-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 5
+// CHECK-32-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 4
+// CHECK-32-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 6
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP107]], align 4
+// CHECK-32-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 7
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP108]], align 4
+// CHECK-32-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 8
+// CHECK-32-NEXT: store i64 0, i64* [[TMP109]], align 8
+// CHECK-32-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 9
+// CHECK-32-NEXT: store i64 0, i64* [[TMP110]], align 8
+// CHECK-32-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 10
+// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4
+// CHECK-32-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 11
+// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4
+// CHECK-32-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 12
+// CHECK-32-NEXT: store i32 0, i32* [[TMP113]], align 4
+// CHECK-32-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]])
+// CHECK-32-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0
+// CHECK-32-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CHECK-32: omp_offload.failed6:
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP44]], [10 x float]* [[B]], i32 [[TMP0]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP2]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
+// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CHECK-32: omp_offload.cont7:
+// CHECK-32-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**
+// CHECK-32-NEXT: store double* [[TMP116]], double** [[TMP118]], align 4
+// CHECK-32-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**
+// CHECK-32-NEXT: store double* [[TMP116]], double** [[TMP120]], align 4
+// CHECK-32-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0
+// CHECK-32-NEXT: store i8* null, i8** [[TMP121]], align 4
+// CHECK-32-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**
+// CHECK-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 4
+// CHECK-32-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**
+// CHECK-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 4
+// CHECK-32-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1
+// CHECK-32-NEXT: store i8* null, i8** [[TMP126]], align 4
+// CHECK-32-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
+// CHECK-32-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK-32-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 0
+// CHECK-32-NEXT: store i32 2, i32* [[TMP129]], align 4
+// CHECK-32-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 1
+// CHECK-32-NEXT: store i32 2, i32* [[TMP130]], align 4
+// CHECK-32-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 2
+// CHECK-32-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 4
+// CHECK-32-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 3
+// CHECK-32-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 4
+// CHECK-32-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 4
+// CHECK-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 4
+// CHECK-32-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 5
+// CHECK-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 4
+// CHECK-32-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 6
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP135]], align 4
+// CHECK-32-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 7
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP136]], align 4
+// CHECK-32-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 8
+// CHECK-32-NEXT: store i64 0, i64* [[TMP137]], align 8
+// CHECK-32-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 9
+// CHECK-32-NEXT: store i64 0, i64* [[TMP138]], align 8
+// CHECK-32-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 10
+// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4
+// CHECK-32-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 11
+// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4
+// CHECK-32-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 12
+// CHECK-32-NEXT: store i32 0, i32* [[TMP141]], align 4
+// CHECK-32-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]])
+// CHECK-32-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0
+// CHECK-32-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]
+// CHECK-32: omp_offload.failed12:
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]
+// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT13]]
+// CHECK-32: omp_offload.cont13:
+// CHECK-32-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-32-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK-32-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])
+// CHECK-32-NEXT: ret i32 [[TMP144]]
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// CHECK-32-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4
+// CHECK-32-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK-32-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4
+// CHECK-32-NEXT: ret void
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// CHECK-32-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
+// CHECK-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
+// CHECK-32-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
+// CHECK-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
+// CHECK-32-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
+// CHECK-32-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// CHECK-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// CHECK-32-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
+// CHECK-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// CHECK-32-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
+// CHECK-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// CHECK-32-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
+// CHECK-32-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
+// CHECK-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
+// CHECK-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
+// CHECK-32-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// CHECK-32-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)
+// CHECK-32-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// CHECK-32-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4
+// CHECK-32-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
+// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK-32-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4
+// CHECK-32-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// CHECK-32-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)
+// CHECK-32-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// CHECK-32-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)
+// CHECK-32-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// CHECK-32-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8
+// CHECK-32-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4
+// CHECK-32-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4
+// CHECK-32-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// CHECK-32-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
+// CHECK-32-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// CHECK-32-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)
+// CHECK-32-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// CHECK-32-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)
+// CHECK-32-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// CHECK-32-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// CHECK-32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK-32-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2
+// CHECK-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// CHECK-32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3
+// CHECK-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// CHECK-32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1
+// CHECK-32-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
+// CHECK-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// CHECK-32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]
+// CHECK-32-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]
+// CHECK-32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3
+// CHECK-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// CHECK-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// CHECK-32-NEXT: store i64 1, i64* [[X]], align 4
+// CHECK-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// CHECK-32-NEXT: store i8 1, i8* [[Y]], align 4
+// CHECK-32-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK-32-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// CHECK-32-NEXT: ret void
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// CHECK-32-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK-32-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4
+// CHECK-32-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*
+// CHECK-32-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*
+// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 8, i1 false)
+// CHECK-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double
+// CHECK-32-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i32 0
+// CHECK-32-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4
+// CHECK-32-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 0
+// CHECK-32-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 4
+// CHECK-32-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// CHECK-32-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 4
+// CHECK-32-NEXT: ret void
+// CHECK-32-LABEL: define {{[^@]+}}@_Z3bariPd
+// CHECK-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
+// CHECK-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK-32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// CHECK-32-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// CHECK-32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// CHECK-32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// CHECK-32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-32-NEXT: ret i32 [[TMP9]]
+// CHECK-32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// CHECK-32-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// CHECK-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[B:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
+// CHECK-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// CHECK-32-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// CHECK-32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
+// CHECK-32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
+// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
+// CHECK-32-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
+// CHECK-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// CHECK-32-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i64
+// CHECK-32-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i32 40, i1 false)
+// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
+// CHECK-32-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
+// CHECK-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
+// CHECK-32-NEXT: store double* [[A]], double** [[TMP13]], align 4
+// CHECK-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK-32-NEXT: store i8* null, i8** [[TMP14]], align 4
+// CHECK-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP5]], i32* [[TMP16]], align 4
+// CHECK-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
+// CHECK-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK-32-NEXT: store i8* null, i8** [[TMP19]], align 4
+// CHECK-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
+// CHECK-32-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
+// CHECK-32-NEXT: store i32 2, i32* [[TMP23]], align 4
+// CHECK-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK-32-NEXT: store i8* null, i8** [[TMP24]], align 4
+// CHECK-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK-32-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP26]], align 4
+// CHECK-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK-32-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4
+// CHECK-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
+// CHECK-32-NEXT: store i8* null, i8** [[TMP29]], align 4
+// CHECK-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
+// CHECK-32-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**
+// CHECK-32-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 4
+// CHECK-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
+// CHECK-32-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**
+// CHECK-32-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 4
+// CHECK-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
+// CHECK-32-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 4
+// CHECK-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
+// CHECK-32-NEXT: store i8* null, i8** [[TMP35]], align 4
+// CHECK-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK-32-NEXT: store i32 2, i32* [[TMP39]], align 4
+// CHECK-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK-32-NEXT: store i32 5, i32* [[TMP40]], align 4
+// CHECK-32-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK-32-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 4
+// CHECK-32-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK-32-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4
+// CHECK-32-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK-32-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 4
+// CHECK-32-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK-32-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 4
+// CHECK-32-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP45]], align 4
+// CHECK-32-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP46]], align 4
+// CHECK-32-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK-32-NEXT: store i64 0, i64* [[TMP47]], align 8
+// CHECK-32-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK-32-NEXT: store i64 0, i64* [[TMP48]], align 8
+// CHECK-32-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4
+// CHECK-32-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4
+// CHECK-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK-32-NEXT: store i32 0, i32* [[TMP51]], align 4
+// CHECK-32-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK-32-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0
+// CHECK-32-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK-32: omp_offload.failed:
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
+// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK-32: omp_offload.cont:
+// CHECK-32-NEXT: [[TMP54:%.*]] = mul nsw i32 1, [[TMP1]]
+// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP54]]
+// CHECK-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// CHECK-32-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
+// CHECK-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP55]] to i32
+// CHECK-32-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4
+// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP56]]
+// CHECK-32-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK-32-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])
+// CHECK-32-NEXT: ret i32 [[ADD3]]
+// CHECK-32-LABEL: define {{[^@]+}}@_ZL7fstatici
+// CHECK-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// CHECK-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
+// CHECK-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK-32-NEXT: store i8 0, i8* [[AAA]], align 1
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
+// CHECK-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
+// CHECK-32-NEXT: store i8 [[TMP2]], i8* [[CONV]], align 1
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
+// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK-32-NEXT: store i8* null, i8** [[TMP8]], align 4
+// CHECK-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
+// CHECK-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
+// CHECK-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK-32-NEXT: store i8* null, i8** [[TMP13]], align 4
+// CHECK-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**
+// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 4
+// CHECK-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**
+// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 4
+// CHECK-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK-32-NEXT: store i8* null, i8** [[TMP18]], align 4
+// CHECK-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK-32-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK-32-NEXT: store i32 3, i32* [[TMP22]], align 4
+// CHECK-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK-32-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 4
+// CHECK-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK-32-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4
+// CHECK-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 4
+// CHECK-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 4
+// CHECK-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP27]], align 4
+// CHECK-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP28]], align 4
+// CHECK-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK-32-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK-32-NEXT: store i64 0, i64* [[TMP30]], align 8
+// CHECK-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4
+// CHECK-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4
+// CHECK-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK-32-NEXT: store i32 0, i32* [[TMP33]], align 4
+// CHECK-32-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK-32-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
+// CHECK-32-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK-32: omp_offload.failed:
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK-32: omp_offload.cont:
+// CHECK-32-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-32-NEXT: ret i32 [[TMP36]]
+// CHECK-32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// CHECK-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
+// CHECK-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
+// CHECK-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
+// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK-32-NEXT: store i8* null, i8** [[TMP6]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**
+// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 4
+// CHECK-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
+// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 4
+// CHECK-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK-32-NEXT: store i8* null, i8** [[TMP11]], align 4
+// CHECK-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK-32-NEXT: store i32 2, i32* [[TMP14]], align 4
+// CHECK-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK-32-NEXT: store i32 2, i32* [[TMP15]], align 4
+// CHECK-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK-32-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 4
+// CHECK-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK-32-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 4
+// CHECK-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 4
+// CHECK-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 4
+// CHECK-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP20]], align 4
+// CHECK-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK-32-NEXT: store i8** null, i8*** [[TMP21]], align 4
+// CHECK-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK-32-NEXT: store i64 0, i64* [[TMP22]], align 8
+// CHECK-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK-32-NEXT: store i64 0, i64* [[TMP23]], align 8
+// CHECK-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4
+// CHECK-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4
+// CHECK-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK-32-NEXT: store i32 0, i32* [[TMP26]], align 4
+// CHECK-32-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK-32-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
+// CHECK-32-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK-32: omp_offload.failed:
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK-32: omp_offload.cont:
+// CHECK-32-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4
+// CHECK-32-NEXT: ret i32 [[TMP29]]
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// CHECK-32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// CHECK-32-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
+// CHECK-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// CHECK-32-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// CHECK-32-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4
+// CHECK-32-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// CHECK-32-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
+// CHECK-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// CHECK-32-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// CHECK-32-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// CHECK-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
+// CHECK-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
+// CHECK-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK-32-NEXT: store double [[ADD]], double* [[A]], align 4
+// CHECK-32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4
+// CHECK-32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// CHECK-32-NEXT: store double [[INC]], double* [[A4]], align 4
+// CHECK-32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
+// CHECK-32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
+// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]
+// CHECK-32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// CHECK-32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK-32-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// CHECK-32-NEXT: ret void
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// CHECK-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// CHECK-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
+// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// CHECK-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
+// CHECK-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
+// CHECK-32-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32
+// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
+// CHECK-32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
+// CHECK-32-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1
+// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1
+// CHECK-32-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
+// CHECK-32-NEXT: ret void
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// CHECK-32-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// CHECK-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK-32-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// CHECK-32-NEXT: ret void
+// CHECK-32-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CHECK-32-SAME: () #[[ATTR5:[0-9]+]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: call void @__tgt_register_requires(i64 1)
+// CHECK-32-NEXT: ret void
+// CHECK0-64-LABEL: define {{[^@]+}}@_Z3fooiPd
+// CHECK0-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK0-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK0-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK0-64-NEXT: [[AA:%.*]] = alloca i16, align 2
+// CHECK0-64-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// CHECK0-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK0-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK0-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// CHECK0-64-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK0-64-NEXT: [[P:%.*]] = alloca i32*, align 64
+// CHECK0-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-64-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [9 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [9 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [9 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK0-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK0-64-NEXT: store i16 0, i16* [[AA]], align 2
+// CHECK0-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK0-64-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// CHECK0-64-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
+// CHECK0-64-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
+// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK0-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// CHECK0-64-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
+// CHECK0-64-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
+// CHECK0-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// CHECK0-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: store i32 [[TMP6]], i32* [[X]], align 4
+// CHECK0-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4
+// CHECK0-64-NEXT: store i32* [[A]], i32** [[P]], align 64
+// CHECK0-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK0-64-NEXT: store i32 [[TMP8]], i32* [[CONV]], align 4
+// CHECK0-64-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK0-64-NEXT: [[TMP10:%.*]] = load i32*, i32** [[P]], align 64
+// CHECK0-64-NEXT: [[TMP11:%.*]] = load i32, i32* @ga, align 4
+// CHECK0-64-NEXT: [[CONV2:%.*]] = bitcast i64* [[GA_CASTED]] to i32*
+// CHECK0-64-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4
+// CHECK0-64-NEXT: [[TMP12:%.*]] = load i64, i64* [[GA_CASTED]], align 8
+// CHECK0-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP9]], i64* [[TMP14]], align 8
+// CHECK0-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP9]], i64* [[TMP16]], align 8
+// CHECK0-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP17]], align 8
+// CHECK0-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
+// CHECK0-64-NEXT: store i32* [[TMP10]], i32** [[TMP19]], align 8
+// CHECK0-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**
+// CHECK0-64-NEXT: store i32* [[TMP10]], i32** [[TMP21]], align 8
+// CHECK0-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP22]], align 8
+// CHECK0-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK0-64-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP12]], i64* [[TMP24]], align 8
+// CHECK0-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK0-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP12]], i64* [[TMP26]], align 8
+// CHECK0-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP27]], align 8
+// CHECK0-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK0-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK0-64-NEXT: store i32 2, i32* [[TMP30]], align 4
+// CHECK0-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK0-64-NEXT: store i32 3, i32* [[TMP31]], align 4
+// CHECK0-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK0-64-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8
+// CHECK0-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK0-64-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 8
+// CHECK0-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK0-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP34]], align 8
+// CHECK0-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK0-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP35]], align 8
+// CHECK0-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP36]], align 8
+// CHECK0-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP37]], align 8
+// CHECK0-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP38]], align 8
+// CHECK0-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP39]], align 8
+// CHECK0-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP40]], align 4
+// CHECK0-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP41]], align 4
+// CHECK0-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK0-64-NEXT: store i32 0, i32* [[TMP42]], align 4
+// CHECK0-64-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK0-64-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
+// CHECK0-64-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK0-64: omp_offload.failed:
+// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], i32* [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]]
+// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK0-64: omp_offload.cont:
+// CHECK0-64-NEXT: [[TMP45:%.*]] = load i16, i16* [[AA]], align 2
+// CHECK0-64-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
+// CHECK0-64-NEXT: store i16 [[TMP45]], i16* [[CONV3]], align 2
+// CHECK0-64-NEXT: [[TMP46:%.*]] = load i64, i64* [[AA_CASTED]], align 8
+// CHECK0-64-NEXT: [[TMP47:%.*]] = mul nuw i64 [[TMP1]], 4
+// CHECK0-64-NEXT: [[TMP48:%.*]] = mul nuw i64 5, [[TMP4]]
+// CHECK0-64-NEXT: [[TMP49:%.*]] = mul nuw i64 [[TMP48]], 8
+// CHECK0-64-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i64 72, i1 false)
+// CHECK0-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP46]], i64* [[TMP52]], align 8
+// CHECK0-64-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP46]], i64* [[TMP54]], align 8
+// CHECK0-64-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP55]], align 8
+// CHECK0-64-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**
+// CHECK0-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 8
+// CHECK0-64-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**
+// CHECK0-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 8
+// CHECK0-64-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP60]], align 8
+// CHECK0-64-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2
+// CHECK0-64-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP62]], align 8
+// CHECK0-64-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2
+// CHECK0-64-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP64]], align 8
+// CHECK0-64-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP65]], align 8
+// CHECK0-64-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3
+// CHECK0-64-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**
+// CHECK0-64-NEXT: store float* [[VLA]], float** [[TMP67]], align 8
+// CHECK0-64-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3
+// CHECK0-64-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**
+// CHECK0-64-NEXT: store float* [[VLA]], float** [[TMP69]], align 8
+// CHECK0-64-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
+// CHECK0-64-NEXT: store i64 [[TMP47]], i64* [[TMP70]], align 8
+// CHECK0-64-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 3
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP71]], align 8
+// CHECK0-64-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 4
+// CHECK0-64-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**
+// CHECK0-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 8
+// CHECK0-64-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 4
+// CHECK0-64-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**
+// CHECK0-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 8
+// CHECK0-64-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 4
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP76]], align 8
+// CHECK0-64-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 5
+// CHECK0-64-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
+// CHECK0-64-NEXT: store i64 5, i64* [[TMP78]], align 8
+// CHECK0-64-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 5
+// CHECK0-64-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*
+// CHECK0-64-NEXT: store i64 5, i64* [[TMP80]], align 8
+// CHECK0-64-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 5
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP81]], align 8
+// CHECK0-64-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 6
+// CHECK0-64-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP4]], i64* [[TMP83]], align 8
+// CHECK0-64-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 6
+// CHECK0-64-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP4]], i64* [[TMP85]], align 8
+// CHECK0-64-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 6
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP86]], align 8
+// CHECK0-64-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 7
+// CHECK0-64-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**
+// CHECK0-64-NEXT: store double* [[VLA1]], double** [[TMP88]], align 8
+// CHECK0-64-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 7
+// CHECK0-64-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**
+// CHECK0-64-NEXT: store double* [[VLA1]], double** [[TMP90]], align 8
+// CHECK0-64-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
+// CHECK0-64-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 8
+// CHECK0-64-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 7
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP92]], align 8
+// CHECK0-64-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 8
+// CHECK0-64-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**
+// CHECK0-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 8
+// CHECK0-64-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 8
+// CHECK0-64-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**
+// CHECK0-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 8
+// CHECK0-64-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 8
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP97]], align 8
+// CHECK0-64-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK0-64-NEXT: [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK0-64-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 0
+// CHECK0-64-NEXT: store i32 2, i32* [[TMP101]], align 4
+// CHECK0-64-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 1
+// CHECK0-64-NEXT: store i32 9, i32* [[TMP102]], align 4
+// CHECK0-64-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 2
+// CHECK0-64-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 8
+// CHECK0-64-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 3
+// CHECK0-64-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 8
+// CHECK0-64-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 4
+// CHECK0-64-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 8
+// CHECK0-64-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 5
+// CHECK0-64-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 8
+// CHECK0-64-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 6
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP107]], align 8
+// CHECK0-64-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 7
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP108]], align 8
+// CHECK0-64-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 8
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP109]], align 8
+// CHECK0-64-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 9
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP110]], align 8
+// CHECK0-64-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 10
+// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4
+// CHECK0-64-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 11
+// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4
+// CHECK0-64-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 12
+// CHECK0-64-NEXT: store i32 0, i32* [[TMP113]], align 4
+// CHECK0-64-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]])
+// CHECK0-64-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0
+// CHECK0-64-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
+// CHECK0-64: omp_offload.failed8:
+// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP46]], [10 x float]* [[B]], i64 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP4]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
+// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT9]]
+// CHECK0-64: omp_offload.cont9:
+// CHECK0-64-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**
+// CHECK0-64-NEXT: store double* [[TMP116]], double** [[TMP118]], align 8
+// CHECK0-64-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**
+// CHECK0-64-NEXT: store double* [[TMP116]], double** [[TMP120]], align 8
+// CHECK0-64-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP121]], align 8
+// CHECK0-64-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**
+// CHECK0-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 8
+// CHECK0-64-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**
+// CHECK0-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 8
+// CHECK0-64-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP126]], align 8
+// CHECK0-64-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CHECK0-64-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK0-64-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0
+// CHECK0-64-NEXT: store i32 2, i32* [[TMP129]], align 4
+// CHECK0-64-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1
+// CHECK0-64-NEXT: store i32 2, i32* [[TMP130]], align 4
+// CHECK0-64-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2
+// CHECK0-64-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 8
+// CHECK0-64-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3
+// CHECK0-64-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 8
+// CHECK0-64-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4
+// CHECK0-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 8
+// CHECK0-64-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5
+// CHECK0-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 8
+// CHECK0-64-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP135]], align 8
+// CHECK0-64-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP136]], align 8
+// CHECK0-64-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP137]], align 8
+// CHECK0-64-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 9
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP138]], align 8
+// CHECK0-64-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 10
+// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4
+// CHECK0-64-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 11
+// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4
+// CHECK0-64-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 12
+// CHECK0-64-NEXT: store i32 0, i32* [[TMP141]], align 4
+// CHECK0-64-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]])
+// CHECK0-64-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0
+// CHECK0-64-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
+// CHECK0-64: omp_offload.failed14:
+// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]
+// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT15]]
+// CHECK0-64: omp_offload.cont15:
+// CHECK0-64-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-64-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK0-64-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])
+// CHECK0-64-NEXT: ret i32 [[TMP144]]
+// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// CHECK0-64-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8
+// CHECK0-64-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK0-64-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8
+// CHECK0-64-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8
+// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK0-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*
+// CHECK0-64-NEXT: ret void
+// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// CHECK0-64-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
+// CHECK0-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
+// CHECK0-64-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
+// CHECK0-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
+// CHECK0-64-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
+// CHECK0-64-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// CHECK0-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK0-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK0-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// CHECK0-64-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
+// CHECK0-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
+// CHECK0-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// CHECK0-64-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
+// CHECK0-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
+// CHECK0-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// CHECK0-64-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
+// CHECK0-64-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
+// CHECK0-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
+// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
+// CHECK0-64-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// CHECK0-64-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
+// CHECK0-64-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// CHECK0-64-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)
+// CHECK0-64-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// CHECK0-64-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8
+// CHECK0-64-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
+// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK0-64-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4
+// CHECK0-64-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// CHECK0-64-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)
+// CHECK0-64-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// CHECK0-64-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)
+// CHECK0-64-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// CHECK0-64-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8
+// CHECK0-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// CHECK0-64-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8
+// CHECK0-64-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// CHECK0-64-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8
+// CHECK0-64-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// CHECK0-64-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)
+// CHECK0-64-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// CHECK0-64-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)
+// CHECK0-64-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// CHECK0-64-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// CHECK0-64-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// CHECK0-64-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK0-64-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2
+// CHECK0-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// CHECK0-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3
+// CHECK0-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// CHECK0-64-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1
+// CHECK0-64-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2
+// CHECK0-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// CHECK0-64-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]
+// CHECK0-64-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]
+// CHECK0-64-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
+// CHECK0-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// CHECK0-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// CHECK0-64-NEXT: store i64 1, i64* [[X]], align 8
+// CHECK0-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// CHECK0-64-NEXT: store i8 1, i8* [[Y]], align 8
+// CHECK0-64-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK0-64-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// CHECK0-64-NEXT: ret void
+// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// CHECK0-64-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK0-64-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8
+// CHECK0-64-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK0-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK0-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*
+// CHECK0-64-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*
+// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 8, i1 false)
+// CHECK0-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK0-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double
+// CHECK0-64-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i64 0
+// CHECK0-64-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8
+// CHECK0-64-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK0-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 0
+// CHECK0-64-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 8
+// CHECK0-64-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// CHECK0-64-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 8
+// CHECK0-64-NEXT: ret void
+// CHECK0-64-LABEL: define {{[^@]+}}@_Z3bariPd
+// CHECK0-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK0-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK0-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK0-64-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
+// CHECK0-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK0-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK0-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK0-64-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])
+// CHECK0-64-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// CHECK0-64-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// CHECK0-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])
+// CHECK0-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// CHECK0-64-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// CHECK0-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])
+// CHECK0-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// CHECK0-64-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// CHECK0-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])
+// CHECK0-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// CHECK0-64-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// CHECK0-64-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-64-NEXT: ret i32 [[TMP9]]
+// CHECK0-64-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// CHECK0-64-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// CHECK0-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK0-64-NEXT: [[B:%.*]] = alloca i32, align 4
+// CHECK0-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK0-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
+// CHECK0-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// CHECK0-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// CHECK0-64-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// CHECK0-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+// CHECK0-64-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
+// CHECK0-64-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
+// CHECK0-64-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
+// CHECK0-64-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
+// CHECK0-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
+// CHECK0-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
+// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
+// CHECK0-64-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
+// CHECK0-64-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
+// CHECK0-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]]
+// CHECK0-64-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 2
+// CHECK0-64-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP9]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i64 40, i1 false)
+// CHECK0-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
+// CHECK0-64-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
+// CHECK0-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
+// CHECK0-64-NEXT: store double* [[A]], double** [[TMP13]], align 8
+// CHECK0-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP14]], align 8
+// CHECK0-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP6]], i64* [[TMP16]], align 8
+// CHECK0-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP6]], i64* [[TMP18]], align 8
+// CHECK0-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP19]], align 8
+// CHECK0-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK0-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
+// CHECK0-64-NEXT: store i64 2, i64* [[TMP21]], align 8
+// CHECK0-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK0-64-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
+// CHECK0-64-NEXT: store i64 2, i64* [[TMP23]], align 8
+// CHECK0-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP24]], align 8
+// CHECK0-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK0-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP2]], i64* [[TMP26]], align 8
+// CHECK0-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK0-64-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP2]], i64* [[TMP28]], align 8
+// CHECK0-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP29]], align 8
+// CHECK0-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
+// CHECK0-64-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**
+// CHECK0-64-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 8
+// CHECK0-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
+// CHECK0-64-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**
+// CHECK0-64-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 8
+// CHECK0-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
+// CHECK0-64-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 8
+// CHECK0-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP35]], align 8
+// CHECK0-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK0-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK0-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK0-64-NEXT: store i32 2, i32* [[TMP39]], align 4
+// CHECK0-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK0-64-NEXT: store i32 5, i32* [[TMP40]], align 4
+// CHECK0-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK0-64-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 8
+// CHECK0-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK0-64-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8
+// CHECK0-64-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK0-64-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 8
+// CHECK0-64-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK0-64-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 8
+// CHECK0-64-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP45]], align 8
+// CHECK0-64-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP46]], align 8
+// CHECK0-64-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP47]], align 8
+// CHECK0-64-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP48]], align 8
+// CHECK0-64-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4
+// CHECK0-64-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4
+// CHECK0-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK0-64-NEXT: store i32 0, i32* [[TMP51]], align 4
+// CHECK0-64-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK0-64-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0
+// CHECK0-64-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK0-64: omp_offload.failed:
+// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
+// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK0-64: omp_offload.cont:
+// CHECK0-64-NEXT: [[TMP54:%.*]] = mul nsw i64 1, [[TMP2]]
+// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP54]]
+// CHECK0-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// CHECK0-64-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
+// CHECK0-64-NEXT: [[CONV3:%.*]] = sext i16 [[TMP55]] to i32
+// CHECK0-64-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4
+// CHECK0-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP56]]
+// CHECK0-64-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK0-64-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])
+// CHECK0-64-NEXT: ret i32 [[ADD4]]
+// CHECK0-64-LABEL: define {{[^@]+}}@_ZL7fstatici
+// CHECK0-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK0-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK0-64-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// CHECK0-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK0-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK0-64-NEXT: store i8 0, i8* [[AAA]], align 1
+// CHECK0-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK0-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
+// CHECK0-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK0-64-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
+// CHECK0-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
+// CHECK0-64-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
+// CHECK0-64-NEXT: [[TMP3:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
+// CHECK0-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
+// CHECK0-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
+// CHECK0-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP8]], align 8
+// CHECK0-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
+// CHECK0-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
+// CHECK0-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP13]], align 8
+// CHECK0-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK0-64-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**
+// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 8
+// CHECK0-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK0-64-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**
+// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 8
+// CHECK0-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP18]], align 8
+// CHECK0-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK0-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK0-64-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK0-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK0-64-NEXT: store i32 3, i32* [[TMP22]], align 4
+// CHECK0-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK0-64-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 8
+// CHECK0-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK0-64-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8
+// CHECK0-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK0-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 8
+// CHECK0-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK0-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 8
+// CHECK0-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP27]], align 8
+// CHECK0-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP28]], align 8
+// CHECK0-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK0-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP30]], align 8
+// CHECK0-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4
+// CHECK0-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4
+// CHECK0-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK0-64-NEXT: store i32 0, i32* [[TMP33]], align 4
+// CHECK0-64-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK0-64-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
+// CHECK0-64-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK0-64: omp_offload.failed:
+// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK0-64: omp_offload.cont:
+// CHECK0-64-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-64-NEXT: ret i32 [[TMP36]]
+// CHECK0-64-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// CHECK0-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK0-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK0-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK0-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK0-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK0-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK0-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
+// CHECK0-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK0-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
+// CHECK0-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
+// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
+// CHECK0-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP6]], align 8
+// CHECK0-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**
+// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 8
+// CHECK0-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK0-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
+// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 8
+// CHECK0-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK0-64-NEXT: store i8* null, i8** [[TMP11]], align 8
+// CHECK0-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK0-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK0-64-NEXT: store i32 2, i32* [[TMP14]], align 4
+// CHECK0-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK0-64-NEXT: store i32 2, i32* [[TMP15]], align 4
+// CHECK0-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK0-64-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 8
+// CHECK0-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK0-64-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 8
+// CHECK0-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK0-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 8
+// CHECK0-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK0-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 8
+// CHECK0-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP20]], align 8
+// CHECK0-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK0-64-NEXT: store i8** null, i8*** [[TMP21]], align 8
+// CHECK0-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP22]], align 8
+// CHECK0-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK0-64-NEXT: store i64 0, i64* [[TMP23]], align 8
+// CHECK0-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK0-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4
+// CHECK0-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK0-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4
+// CHECK0-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK0-64-NEXT: store i32 0, i32* [[TMP26]], align 4
+// CHECK0-64-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK0-64-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
+// CHECK0-64-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK0-64: omp_offload.failed:
+// CHECK0-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK0-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK0-64: omp_offload.cont:
+// CHECK0-64-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-64-NEXT: ret i32 [[TMP29]]
+// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// CHECK0-64-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// CHECK0-64-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
+// CHECK0-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK0-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// CHECK0-64-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
+// CHECK0-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// CHECK0-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// CHECK0-64-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
+// CHECK0-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// CHECK0-64-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// CHECK0-64-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
+// CHECK0-64-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// CHECK0-64-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
+// CHECK0-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK0-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8
+// CHECK0-64-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// CHECK0-64-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
+// CHECK0-64-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// CHECK0-64-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)
+// CHECK0-64-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK0-64-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double
+// CHECK0-64-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
+// CHECK0-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK0-64-NEXT: store double [[ADD]], double* [[A]], align 8
+// CHECK0-64-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK0-64-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8
+// CHECK0-64-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// CHECK0-64-NEXT: store double [[INC]], double* [[A5]], align 8
+// CHECK0-64-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
+// CHECK0-64-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]
+// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]
+// CHECK0-64-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// CHECK0-64-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
+// CHECK0-64-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK0-64-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// CHECK0-64-NEXT: ret void
+// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// CHECK0-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// CHECK0-64-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
+// CHECK0-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK0-64-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
+// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK0-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
+// CHECK0-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*
+// CHECK0-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// CHECK0-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK0-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK0-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK0-64-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
+// CHECK0-64-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32
+// CHECK0-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
+// CHECK0-64-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
+// CHECK0-64-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1
+// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2
+// CHECK0-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK0-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1
+// CHECK0-64-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
+// CHECK0-64-NEXT: ret void
+// CHECK0-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// CHECK0-64-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// CHECK0-64-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK0-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK0-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// CHECK0-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK0-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// CHECK0-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK0-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK0-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// CHECK0-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK0-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK0-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK0-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2
+// CHECK0-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK0-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK0-64-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// CHECK0-64-NEXT: ret void
+// CHECK0-64-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CHECK0-64-SAME: () #[[ATTR5:[0-9]+]] {
+// CHECK0-64-NEXT: entry:
+// CHECK0-64-NEXT: call void @__tgt_register_requires(i64 1)
+// CHECK0-64-NEXT: ret void
+// CHECK1-64-LABEL: define {{[^@]+}}@_Z3fooiPd
+// CHECK1-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK1-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK1-64-NEXT: [[AA:%.*]] = alloca i16, align 2
+// CHECK1-64-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// CHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK1-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// CHECK1-64-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK1-64-NEXT: [[P:%.*]] = alloca i32*, align 64
+// CHECK1-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-64-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [9 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [9 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [9 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK1-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK1-64-NEXT: store i16 0, i16* [[AA]], align 2
+// CHECK1-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK1-64-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// CHECK1-64-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
+// CHECK1-64-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
+// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// CHECK1-64-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
+// CHECK1-64-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
+// CHECK1-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// CHECK1-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: store i32 [[TMP6]], i32* [[X]], align 4
+// CHECK1-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4
+// CHECK1-64-NEXT: store i32* [[A]], i32** [[P]], align 64
+// CHECK1-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK1-64-NEXT: store i32 [[TMP8]], i32* [[CONV]], align 4
+// CHECK1-64-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK1-64-NEXT: [[TMP10:%.*]] = load i32*, i32** [[P]], align 64
+// CHECK1-64-NEXT: [[TMP11:%.*]] = load i32, i32* @ga, align 4
+// CHECK1-64-NEXT: [[CONV2:%.*]] = bitcast i64* [[GA_CASTED]] to i32*
+// CHECK1-64-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4
+// CHECK1-64-NEXT: [[TMP12:%.*]] = load i64, i64* [[GA_CASTED]], align 8
+// CHECK1-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP9]], i64* [[TMP14]], align 8
+// CHECK1-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP9]], i64* [[TMP16]], align 8
+// CHECK1-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP17]], align 8
+// CHECK1-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
+// CHECK1-64-NEXT: store i32* [[TMP10]], i32** [[TMP19]], align 8
+// CHECK1-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**
+// CHECK1-64-NEXT: store i32* [[TMP10]], i32** [[TMP21]], align 8
+// CHECK1-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP22]], align 8
+// CHECK1-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK1-64-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP12]], i64* [[TMP24]], align 8
+// CHECK1-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK1-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP12]], i64* [[TMP26]], align 8
+// CHECK1-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP27]], align 8
+// CHECK1-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK1-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK1-64-NEXT: store i32 2, i32* [[TMP30]], align 4
+// CHECK1-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK1-64-NEXT: store i32 3, i32* [[TMP31]], align 4
+// CHECK1-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK1-64-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8
+// CHECK1-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK1-64-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 8
+// CHECK1-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK1-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP34]], align 8
+// CHECK1-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK1-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP35]], align 8
+// CHECK1-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP36]], align 8
+// CHECK1-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP37]], align 8
+// CHECK1-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP38]], align 8
+// CHECK1-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP39]], align 8
+// CHECK1-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP40]], align 4
+// CHECK1-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP41]], align 4
+// CHECK1-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK1-64-NEXT: store i32 0, i32* [[TMP42]], align 4
+// CHECK1-64-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK1-64-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
+// CHECK1-64-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK1-64: omp_offload.failed:
+// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], i32* [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]]
+// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK1-64: omp_offload.cont:
+// CHECK1-64-NEXT: [[TMP45:%.*]] = load i16, i16* [[AA]], align 2
+// CHECK1-64-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
+// CHECK1-64-NEXT: store i16 [[TMP45]], i16* [[CONV3]], align 2
+// CHECK1-64-NEXT: [[TMP46:%.*]] = load i64, i64* [[AA_CASTED]], align 8
+// CHECK1-64-NEXT: [[TMP47:%.*]] = mul nuw i64 [[TMP1]], 4
+// CHECK1-64-NEXT: [[TMP48:%.*]] = mul nuw i64 5, [[TMP4]]
+// CHECK1-64-NEXT: [[TMP49:%.*]] = mul nuw i64 [[TMP48]], 8
+// CHECK1-64-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i64 72, i1 false)
+// CHECK1-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP46]], i64* [[TMP52]], align 8
+// CHECK1-64-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP46]], i64* [[TMP54]], align 8
+// CHECK1-64-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP55]], align 8
+// CHECK1-64-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**
+// CHECK1-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 8
+// CHECK1-64-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**
+// CHECK1-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 8
+// CHECK1-64-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP60]], align 8
+// CHECK1-64-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2
+// CHECK1-64-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP62]], align 8
+// CHECK1-64-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2
+// CHECK1-64-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP64]], align 8
+// CHECK1-64-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP65]], align 8
+// CHECK1-64-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3
+// CHECK1-64-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**
+// CHECK1-64-NEXT: store float* [[VLA]], float** [[TMP67]], align 8
+// CHECK1-64-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3
+// CHECK1-64-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**
+// CHECK1-64-NEXT: store float* [[VLA]], float** [[TMP69]], align 8
+// CHECK1-64-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
+// CHECK1-64-NEXT: store i64 [[TMP47]], i64* [[TMP70]], align 8
+// CHECK1-64-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 3
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP71]], align 8
+// CHECK1-64-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 4
+// CHECK1-64-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**
+// CHECK1-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 8
+// CHECK1-64-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 4
+// CHECK1-64-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**
+// CHECK1-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 8
+// CHECK1-64-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 4
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP76]], align 8
+// CHECK1-64-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 5
+// CHECK1-64-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
+// CHECK1-64-NEXT: store i64 5, i64* [[TMP78]], align 8
+// CHECK1-64-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 5
+// CHECK1-64-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*
+// CHECK1-64-NEXT: store i64 5, i64* [[TMP80]], align 8
+// CHECK1-64-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 5
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP81]], align 8
+// CHECK1-64-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 6
+// CHECK1-64-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP4]], i64* [[TMP83]], align 8
+// CHECK1-64-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 6
+// CHECK1-64-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP4]], i64* [[TMP85]], align 8
+// CHECK1-64-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 6
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP86]], align 8
+// CHECK1-64-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 7
+// CHECK1-64-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**
+// CHECK1-64-NEXT: store double* [[VLA1]], double** [[TMP88]], align 8
+// CHECK1-64-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 7
+// CHECK1-64-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**
+// CHECK1-64-NEXT: store double* [[VLA1]], double** [[TMP90]], align 8
+// CHECK1-64-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
+// CHECK1-64-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 8
+// CHECK1-64-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 7
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP92]], align 8
+// CHECK1-64-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 8
+// CHECK1-64-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**
+// CHECK1-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 8
+// CHECK1-64-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 8
+// CHECK1-64-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**
+// CHECK1-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 8
+// CHECK1-64-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 8
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP97]], align 8
+// CHECK1-64-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK1-64-NEXT: [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK1-64-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 0
+// CHECK1-64-NEXT: store i32 2, i32* [[TMP101]], align 4
+// CHECK1-64-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 1
+// CHECK1-64-NEXT: store i32 9, i32* [[TMP102]], align 4
+// CHECK1-64-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 2
+// CHECK1-64-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 8
+// CHECK1-64-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 3
+// CHECK1-64-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 8
+// CHECK1-64-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 4
+// CHECK1-64-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 8
+// CHECK1-64-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 5
+// CHECK1-64-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 8
+// CHECK1-64-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 6
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP107]], align 8
+// CHECK1-64-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 7
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP108]], align 8
+// CHECK1-64-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 8
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP109]], align 8
+// CHECK1-64-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 9
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP110]], align 8
+// CHECK1-64-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 10
+// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4
+// CHECK1-64-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 11
+// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4
+// CHECK1-64-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 12
+// CHECK1-64-NEXT: store i32 0, i32* [[TMP113]], align 4
+// CHECK1-64-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]])
+// CHECK1-64-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0
+// CHECK1-64-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
+// CHECK1-64: omp_offload.failed8:
+// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP46]], [10 x float]* [[B]], i64 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP4]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
+// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT9]]
+// CHECK1-64: omp_offload.cont9:
+// CHECK1-64-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**
+// CHECK1-64-NEXT: store double* [[TMP116]], double** [[TMP118]], align 8
+// CHECK1-64-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**
+// CHECK1-64-NEXT: store double* [[TMP116]], double** [[TMP120]], align 8
+// CHECK1-64-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP121]], align 8
+// CHECK1-64-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**
+// CHECK1-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 8
+// CHECK1-64-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**
+// CHECK1-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 8
+// CHECK1-64-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP126]], align 8
+// CHECK1-64-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CHECK1-64-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK1-64-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0
+// CHECK1-64-NEXT: store i32 2, i32* [[TMP129]], align 4
+// CHECK1-64-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1
+// CHECK1-64-NEXT: store i32 2, i32* [[TMP130]], align 4
+// CHECK1-64-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2
+// CHECK1-64-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 8
+// CHECK1-64-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3
+// CHECK1-64-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 8
+// CHECK1-64-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4
+// CHECK1-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 8
+// CHECK1-64-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5
+// CHECK1-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 8
+// CHECK1-64-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP135]], align 8
+// CHECK1-64-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP136]], align 8
+// CHECK1-64-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP137]], align 8
+// CHECK1-64-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 9
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP138]], align 8
+// CHECK1-64-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 10
+// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4
+// CHECK1-64-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 11
+// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4
+// CHECK1-64-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 12
+// CHECK1-64-NEXT: store i32 0, i32* [[TMP141]], align 4
+// CHECK1-64-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]])
+// CHECK1-64-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0
+// CHECK1-64-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
+// CHECK1-64: omp_offload.failed14:
+// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]
+// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT15]]
+// CHECK1-64: omp_offload.cont15:
+// CHECK1-64-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-64-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])
+// CHECK1-64-NEXT: ret i32 [[TMP144]]
+// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// CHECK1-64-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8
+// CHECK1-64-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK1-64-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8
+// CHECK1-64-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8
+// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK1-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*
+// CHECK1-64-NEXT: ret void
+// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// CHECK1-64-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
+// CHECK1-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
+// CHECK1-64-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
+// CHECK1-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
+// CHECK1-64-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
+// CHECK1-64-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// CHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK1-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// CHECK1-64-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
+// CHECK1-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
+// CHECK1-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// CHECK1-64-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
+// CHECK1-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
+// CHECK1-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// CHECK1-64-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
+// CHECK1-64-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
+// CHECK1-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
+// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
+// CHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// CHECK1-64-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
+// CHECK1-64-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// CHECK1-64-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)
+// CHECK1-64-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// CHECK1-64-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8
+// CHECK1-64-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
+// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK1-64-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4
+// CHECK1-64-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// CHECK1-64-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)
+// CHECK1-64-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// CHECK1-64-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)
+// CHECK1-64-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// CHECK1-64-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8
+// CHECK1-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// CHECK1-64-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8
+// CHECK1-64-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// CHECK1-64-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8
+// CHECK1-64-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// CHECK1-64-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)
+// CHECK1-64-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// CHECK1-64-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)
+// CHECK1-64-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// CHECK1-64-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// CHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// CHECK1-64-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK1-64-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2
+// CHECK1-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// CHECK1-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3
+// CHECK1-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// CHECK1-64-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1
+// CHECK1-64-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2
+// CHECK1-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// CHECK1-64-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]
+// CHECK1-64-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]
+// CHECK1-64-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
+// CHECK1-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// CHECK1-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// CHECK1-64-NEXT: store i64 1, i64* [[X]], align 8
+// CHECK1-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// CHECK1-64-NEXT: store i8 1, i8* [[Y]], align 8
+// CHECK1-64-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// CHECK1-64-NEXT: ret void
+// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// CHECK1-64-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK1-64-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8
+// CHECK1-64-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK1-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK1-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*
+// CHECK1-64-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*
+// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 8, i1 false)
+// CHECK1-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK1-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double
+// CHECK1-64-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i64 0
+// CHECK1-64-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8
+// CHECK1-64-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK1-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 0
+// CHECK1-64-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 8
+// CHECK1-64-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// CHECK1-64-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 8
+// CHECK1-64-NEXT: ret void
+// CHECK1-64-LABEL: define {{[^@]+}}@_Z3bariPd
+// CHECK1-64-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK1-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK1-64-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
+// CHECK1-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK1-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK1-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK1-64-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])
+// CHECK1-64-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// CHECK1-64-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// CHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])
+// CHECK1-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// CHECK1-64-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// CHECK1-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])
+// CHECK1-64-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// CHECK1-64-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// CHECK1-64-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])
+// CHECK1-64-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// CHECK1-64-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// CHECK1-64-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-64-NEXT: ret i32 [[TMP9]]
+// CHECK1-64-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// CHECK1-64-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// CHECK1-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-64-NEXT: [[B:%.*]] = alloca i32, align 4
+// CHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
+// CHECK1-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// CHECK1-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// CHECK1-64-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// CHECK1-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+// CHECK1-64-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
+// CHECK1-64-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
+// CHECK1-64-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
+// CHECK1-64-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
+// CHECK1-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
+// CHECK1-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
+// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
+// CHECK1-64-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
+// CHECK1-64-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
+// CHECK1-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]]
+// CHECK1-64-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 2
+// CHECK1-64-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP9]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i64 40, i1 false)
+// CHECK1-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
+// CHECK1-64-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
+// CHECK1-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
+// CHECK1-64-NEXT: store double* [[A]], double** [[TMP13]], align 8
+// CHECK1-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP14]], align 8
+// CHECK1-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP6]], i64* [[TMP16]], align 8
+// CHECK1-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP6]], i64* [[TMP18]], align 8
+// CHECK1-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP19]], align 8
+// CHECK1-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK1-64-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
+// CHECK1-64-NEXT: store i64 2, i64* [[TMP21]], align 8
+// CHECK1-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK1-64-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
+// CHECK1-64-NEXT: store i64 2, i64* [[TMP23]], align 8
+// CHECK1-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP24]], align 8
+// CHECK1-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK1-64-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP2]], i64* [[TMP26]], align 8
+// CHECK1-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK1-64-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP2]], i64* [[TMP28]], align 8
+// CHECK1-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP29]], align 8
+// CHECK1-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
+// CHECK1-64-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**
+// CHECK1-64-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 8
+// CHECK1-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
+// CHECK1-64-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**
+// CHECK1-64-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 8
+// CHECK1-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
+// CHECK1-64-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 8
+// CHECK1-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP35]], align 8
+// CHECK1-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK1-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK1-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK1-64-NEXT: store i32 2, i32* [[TMP39]], align 4
+// CHECK1-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK1-64-NEXT: store i32 5, i32* [[TMP40]], align 4
+// CHECK1-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK1-64-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 8
+// CHECK1-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK1-64-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8
+// CHECK1-64-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK1-64-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 8
+// CHECK1-64-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK1-64-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 8
+// CHECK1-64-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP45]], align 8
+// CHECK1-64-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP46]], align 8
+// CHECK1-64-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP47]], align 8
+// CHECK1-64-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP48]], align 8
+// CHECK1-64-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4
+// CHECK1-64-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4
+// CHECK1-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK1-64-NEXT: store i32 0, i32* [[TMP51]], align 4
+// CHECK1-64-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK1-64-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0
+// CHECK1-64-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK1-64: omp_offload.failed:
+// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
+// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK1-64: omp_offload.cont:
+// CHECK1-64-NEXT: [[TMP54:%.*]] = mul nsw i64 1, [[TMP2]]
+// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP54]]
+// CHECK1-64-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// CHECK1-64-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
+// CHECK1-64-NEXT: [[CONV3:%.*]] = sext i16 [[TMP55]] to i32
+// CHECK1-64-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4
+// CHECK1-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP56]]
+// CHECK1-64-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])
+// CHECK1-64-NEXT: ret i32 [[ADD4]]
+// CHECK1-64-LABEL: define {{[^@]+}}@_ZL7fstatici
+// CHECK1-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK1-64-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// CHECK1-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK1-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK1-64-NEXT: store i8 0, i8* [[AAA]], align 1
+// CHECK1-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK1-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
+// CHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK1-64-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
+// CHECK1-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
+// CHECK1-64-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
+// CHECK1-64-NEXT: [[TMP3:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
+// CHECK1-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
+// CHECK1-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
+// CHECK1-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP8]], align 8
+// CHECK1-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
+// CHECK1-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
+// CHECK1-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP13]], align 8
+// CHECK1-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK1-64-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**
+// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 8
+// CHECK1-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK1-64-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**
+// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 8
+// CHECK1-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP18]], align 8
+// CHECK1-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK1-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK1-64-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK1-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK1-64-NEXT: store i32 3, i32* [[TMP22]], align 4
+// CHECK1-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK1-64-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 8
+// CHECK1-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK1-64-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8
+// CHECK1-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK1-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 8
+// CHECK1-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK1-64-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 8
+// CHECK1-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP27]], align 8
+// CHECK1-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP28]], align 8
+// CHECK1-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK1-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP30]], align 8
+// CHECK1-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4
+// CHECK1-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4
+// CHECK1-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK1-64-NEXT: store i32 0, i32* [[TMP33]], align 4
+// CHECK1-64-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK1-64-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
+// CHECK1-64-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK1-64: omp_offload.failed:
+// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK1-64: omp_offload.cont:
+// CHECK1-64-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-64-NEXT: ret i32 [[TMP36]]
+// CHECK1-64-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// CHECK1-64-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-64-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK1-64-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK1-64-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-64-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK1-64-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK1-64-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK1-64-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
+// CHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK1-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
+// CHECK1-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
+// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
+// CHECK1-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP6]], align 8
+// CHECK1-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**
+// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 8
+// CHECK1-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK1-64-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
+// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 8
+// CHECK1-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK1-64-NEXT: store i8* null, i8** [[TMP11]], align 8
+// CHECK1-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK1-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK1-64-NEXT: store i32 2, i32* [[TMP14]], align 4
+// CHECK1-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK1-64-NEXT: store i32 2, i32* [[TMP15]], align 4
+// CHECK1-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK1-64-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 8
+// CHECK1-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK1-64-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 8
+// CHECK1-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK1-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 8
+// CHECK1-64-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK1-64-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 8
+// CHECK1-64-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP20]], align 8
+// CHECK1-64-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK1-64-NEXT: store i8** null, i8*** [[TMP21]], align 8
+// CHECK1-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP22]], align 8
+// CHECK1-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK1-64-NEXT: store i64 0, i64* [[TMP23]], align 8
+// CHECK1-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4
+// CHECK1-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK1-64-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4
+// CHECK1-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK1-64-NEXT: store i32 0, i32* [[TMP26]], align 4
+// CHECK1-64-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK1-64-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
+// CHECK1-64-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK1-64: omp_offload.failed:
+// CHECK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK1-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK1-64: omp_offload.cont:
+// CHECK1-64-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-64-NEXT: ret i32 [[TMP29]]
+// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// CHECK1-64-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// CHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
+// CHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// CHECK1-64-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
+// CHECK1-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// CHECK1-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// CHECK1-64-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
+// CHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// CHECK1-64-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// CHECK1-64-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
+// CHECK1-64-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// CHECK1-64-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
+// CHECK1-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK1-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8
+// CHECK1-64-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// CHECK1-64-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
+// CHECK1-64-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// CHECK1-64-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)
+// CHECK1-64-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-64-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double
+// CHECK1-64-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
+// CHECK1-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK1-64-NEXT: store double [[ADD]], double* [[A]], align 8
+// CHECK1-64-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK1-64-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8
+// CHECK1-64-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// CHECK1-64-NEXT: store double [[INC]], double* [[A5]], align 8
+// CHECK1-64-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
+// CHECK1-64-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]
+// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]
+// CHECK1-64-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// CHECK1-64-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
+// CHECK1-64-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// CHECK1-64-NEXT: ret void
+// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// CHECK1-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// CHECK1-64-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
+// CHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK1-64-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
+// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK1-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
+// CHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*
+// CHECK1-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// CHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK1-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-64-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
+// CHECK1-64-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32
+// CHECK1-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
+// CHECK1-64-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
+// CHECK1-64-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1
+// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2
+// CHECK1-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK1-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1
+// CHECK1-64-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
+// CHECK1-64-NEXT: ret void
+// CHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// CHECK1-64-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// CHECK1-64-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// CHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// CHECK1-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK1-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// CHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK1-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2
+// CHECK1-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK1-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK1-64-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// CHECK1-64-NEXT: ret void
+// CHECK1-64-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CHECK1-64-SAME: () #[[ATTR5:[0-9]+]] {
+// CHECK1-64-NEXT: entry:
+// CHECK1-64-NEXT: call void @__tgt_register_requires(i64 1)
+// CHECK1-64-NEXT: ret void
+// CHECK2-32-LABEL: define {{[^@]+}}@_Z3fooiPd
+// CHECK2-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK2-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[AA:%.*]] = alloca i16, align 2
+// CHECK2-32-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// CHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK2-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// CHECK2-32-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK2-32-NEXT: [[P:%.*]] = alloca i32*, align 64
+// CHECK2-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-32-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK2-32-NEXT: store i16 0, i16* [[AA]], align 2
+// CHECK2-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
+// CHECK2-32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
+// CHECK2-32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
+// CHECK2-32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
+// CHECK2-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
+// CHECK2-32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
+// CHECK2-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// CHECK2-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 [[TMP4]], i32* [[X]], align 4
+// CHECK2-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4
+// CHECK2-32-NEXT: store i32* [[A]], i32** [[P]], align 64
+// CHECK2-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-32-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 4
+// CHECK2-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK2-32-NEXT: [[TMP8:%.*]] = load i32*, i32** [[P]], align 64
+// CHECK2-32-NEXT: [[TMP9:%.*]] = load i32, i32* @ga, align 4
+// CHECK2-32-NEXT: store i32 [[TMP9]], i32* [[GA_CASTED]], align 4
+// CHECK2-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[GA_CASTED]], align 4
+// CHECK2-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP7]], i32* [[TMP12]], align 4
+// CHECK2-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP7]], i32* [[TMP14]], align 4
+// CHECK2-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP15]], align 4
+// CHECK2-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32**
+// CHECK2-32-NEXT: store i32* [[TMP8]], i32** [[TMP17]], align 4
+// CHECK2-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
+// CHECK2-32-NEXT: store i32* [[TMP8]], i32** [[TMP19]], align 4
+// CHECK2-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP20]], align 4
+// CHECK2-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK2-32-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP10]], i32* [[TMP22]], align 4
+// CHECK2-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK2-32-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP10]], i32* [[TMP24]], align 4
+// CHECK2-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP25]], align 4
+// CHECK2-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK2-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK2-32-NEXT: store i32 2, i32* [[TMP28]], align 4
+// CHECK2-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK2-32-NEXT: store i32 3, i32* [[TMP29]], align 4
+// CHECK2-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK2-32-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 4
+// CHECK2-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK2-32-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4
+// CHECK2-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK2-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP32]], align 4
+// CHECK2-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK2-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP33]], align 4
+// CHECK2-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP34]], align 4
+// CHECK2-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP35]], align 4
+// CHECK2-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP36]], align 8
+// CHECK2-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP37]], align 8
+// CHECK2-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP38]], align 4
+// CHECK2-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP39]], align 4
+// CHECK2-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK2-32-NEXT: store i32 0, i32* [[TMP40]], align 4
+// CHECK2-32-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK2-32-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0
+// CHECK2-32-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK2-32: omp_offload.failed:
+// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], i32* [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]]
+// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK2-32: omp_offload.cont:
+// CHECK2-32-NEXT: [[TMP43:%.*]] = load i16, i16* [[AA]], align 2
+// CHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
+// CHECK2-32-NEXT: store i16 [[TMP43]], i16* [[CONV]], align 2
+// CHECK2-32-NEXT: [[TMP44:%.*]] = load i32, i32* [[AA_CASTED]], align 4
+// CHECK2-32-NEXT: [[TMP45:%.*]] = mul nuw i32 [[TMP0]], 4
+// CHECK2-32-NEXT: [[TMP46:%.*]] = sext i32 [[TMP45]] to i64
+// CHECK2-32-NEXT: [[TMP47:%.*]] = mul nuw i32 5, [[TMP2]]
+// CHECK2-32-NEXT: [[TMP48:%.*]] = mul nuw i32 [[TMP47]], 8
+// CHECK2-32-NEXT: [[TMP49:%.*]] = sext i32 [[TMP48]] to i64
+// CHECK2-32-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i32 72, i1 false)
+// CHECK2-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP44]], i32* [[TMP52]], align 4
+// CHECK2-32-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP44]], i32* [[TMP54]], align 4
+// CHECK2-32-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP55]], align 4
+// CHECK2-32-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**
+// CHECK2-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 4
+// CHECK2-32-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**
+// CHECK2-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 4
+// CHECK2-32-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP60]], align 4
+// CHECK2-32-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2
+// CHECK2-32-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP0]], i32* [[TMP62]], align 4
+// CHECK2-32-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2
+// CHECK2-32-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP0]], i32* [[TMP64]], align 4
+// CHECK2-32-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP65]], align 4
+// CHECK2-32-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 3
+// CHECK2-32-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**
+// CHECK2-32-NEXT: store float* [[VLA]], float** [[TMP67]], align 4
+// CHECK2-32-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 3
+// CHECK2-32-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**
+// CHECK2-32-NEXT: store float* [[VLA]], float** [[TMP69]], align 4
+// CHECK2-32-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
+// CHECK2-32-NEXT: store i64 [[TMP46]], i64* [[TMP70]], align 4
+// CHECK2-32-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 3
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP71]], align 4
+// CHECK2-32-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 4
+// CHECK2-32-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**
+// CHECK2-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 4
+// CHECK2-32-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 4
+// CHECK2-32-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**
+// CHECK2-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 4
+// CHECK2-32-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 4
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP76]], align 4
+// CHECK2-32-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 5
+// CHECK2-32-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32*
+// CHECK2-32-NEXT: store i32 5, i32* [[TMP78]], align 4
+// CHECK2-32-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 5
+// CHECK2-32-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*
+// CHECK2-32-NEXT: store i32 5, i32* [[TMP80]], align 4
+// CHECK2-32-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 5
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP81]], align 4
+// CHECK2-32-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 6
+// CHECK2-32-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP2]], i32* [[TMP83]], align 4
+// CHECK2-32-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 6
+// CHECK2-32-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP2]], i32* [[TMP85]], align 4
+// CHECK2-32-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 6
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP86]], align 4
+// CHECK2-32-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 7
+// CHECK2-32-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**
+// CHECK2-32-NEXT: store double* [[VLA1]], double** [[TMP88]], align 4
+// CHECK2-32-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 7
+// CHECK2-32-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**
+// CHECK2-32-NEXT: store double* [[VLA1]], double** [[TMP90]], align 4
+// CHECK2-32-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
+// CHECK2-32-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 4
+// CHECK2-32-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 7
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP92]], align 4
+// CHECK2-32-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 8
+// CHECK2-32-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**
+// CHECK2-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 4
+// CHECK2-32-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 8
+// CHECK2-32-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**
+// CHECK2-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 4
+// CHECK2-32-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 8
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP97]], align 4
+// CHECK2-32-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK2-32-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK2-32-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 0
+// CHECK2-32-NEXT: store i32 2, i32* [[TMP101]], align 4
+// CHECK2-32-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 1
+// CHECK2-32-NEXT: store i32 9, i32* [[TMP102]], align 4
+// CHECK2-32-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 2
+// CHECK2-32-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 4
+// CHECK2-32-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 3
+// CHECK2-32-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 4
+// CHECK2-32-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 4
+// CHECK2-32-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 4
+// CHECK2-32-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 5
+// CHECK2-32-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 4
+// CHECK2-32-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 6
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP107]], align 4
+// CHECK2-32-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 7
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP108]], align 4
+// CHECK2-32-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 8
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP109]], align 8
+// CHECK2-32-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 9
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP110]], align 8
+// CHECK2-32-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 10
+// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4
+// CHECK2-32-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 11
+// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4
+// CHECK2-32-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 12
+// CHECK2-32-NEXT: store i32 0, i32* [[TMP113]], align 4
+// CHECK2-32-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]])
+// CHECK2-32-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0
+// CHECK2-32-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CHECK2-32: omp_offload.failed6:
+// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP44]], [10 x float]* [[B]], i32 [[TMP0]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP2]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
+// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CHECK2-32: omp_offload.cont7:
+// CHECK2-32-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**
+// CHECK2-32-NEXT: store double* [[TMP116]], double** [[TMP118]], align 4
+// CHECK2-32-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**
+// CHECK2-32-NEXT: store double* [[TMP116]], double** [[TMP120]], align 4
+// CHECK2-32-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP121]], align 4
+// CHECK2-32-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**
+// CHECK2-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 4
+// CHECK2-32-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**
+// CHECK2-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 4
+// CHECK2-32-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP126]], align 4
+// CHECK2-32-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
+// CHECK2-32-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK2-32-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 0
+// CHECK2-32-NEXT: store i32 2, i32* [[TMP129]], align 4
+// CHECK2-32-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 1
+// CHECK2-32-NEXT: store i32 2, i32* [[TMP130]], align 4
+// CHECK2-32-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 2
+// CHECK2-32-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 4
+// CHECK2-32-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 3
+// CHECK2-32-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 4
+// CHECK2-32-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 4
+// CHECK2-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 4
+// CHECK2-32-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 5
+// CHECK2-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 4
+// CHECK2-32-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 6
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP135]], align 4
+// CHECK2-32-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 7
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP136]], align 4
+// CHECK2-32-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 8
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP137]], align 8
+// CHECK2-32-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 9
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP138]], align 8
+// CHECK2-32-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 10
+// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4
+// CHECK2-32-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 11
+// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4
+// CHECK2-32-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 12
+// CHECK2-32-NEXT: store i32 0, i32* [[TMP141]], align 4
+// CHECK2-32-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]])
+// CHECK2-32-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0
+// CHECK2-32-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]
+// CHECK2-32: omp_offload.failed12:
+// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]
+// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT13]]
+// CHECK2-32: omp_offload.cont13:
+// CHECK2-32-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-32-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])
+// CHECK2-32-NEXT: ret i32 [[TMP144]]
+// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// CHECK2-32-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4
+// CHECK2-32-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK2-32-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4
+// CHECK2-32-NEXT: ret void
+// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// CHECK2-32-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
+// CHECK2-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
+// CHECK2-32-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
+// CHECK2-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
+// CHECK2-32-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
+// CHECK2-32-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// CHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK2-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// CHECK2-32-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
+// CHECK2-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// CHECK2-32-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
+// CHECK2-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// CHECK2-32-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
+// CHECK2-32-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
+// CHECK2-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
+// CHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
+// CHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// CHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
+// CHECK2-32-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// CHECK2-32-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)
+// CHECK2-32-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// CHECK2-32-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4
+// CHECK2-32-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
+// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK2-32-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4
+// CHECK2-32-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// CHECK2-32-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)
+// CHECK2-32-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// CHECK2-32-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)
+// CHECK2-32-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// CHECK2-32-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8
+// CHECK2-32-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4
+// CHECK2-32-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4
+// CHECK2-32-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// CHECK2-32-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
+// CHECK2-32-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// CHECK2-32-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)
+// CHECK2-32-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// CHECK2-32-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)
+// CHECK2-32-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// CHECK2-32-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// CHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// CHECK2-32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK2-32-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2
+// CHECK2-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// CHECK2-32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3
+// CHECK2-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// CHECK2-32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1
+// CHECK2-32-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
+// CHECK2-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// CHECK2-32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]
+// CHECK2-32-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]
+// CHECK2-32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3
+// CHECK2-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// CHECK2-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// CHECK2-32-NEXT: store i64 1, i64* [[X]], align 4
+// CHECK2-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// CHECK2-32-NEXT: store i8 1, i8* [[Y]], align 4
+// CHECK2-32-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// CHECK2-32-NEXT: ret void
+// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// CHECK2-32-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK2-32-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4
+// CHECK2-32-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK2-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK2-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*
+// CHECK2-32-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*
+// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 8, i1 false)
+// CHECK2-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK2-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double
+// CHECK2-32-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i32 0
+// CHECK2-32-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4
+// CHECK2-32-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK2-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 0
+// CHECK2-32-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 4
+// CHECK2-32-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// CHECK2-32-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 4
+// CHECK2-32-NEXT: ret void
+// CHECK2-32-LABEL: define {{[^@]+}}@_Z3bariPd
+// CHECK2-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK2-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
+// CHECK2-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK2-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK2-32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])
+// CHECK2-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// CHECK2-32-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// CHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])
+// CHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// CHECK2-32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// CHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])
+// CHECK2-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// CHECK2-32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// CHECK2-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])
+// CHECK2-32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// CHECK2-32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// CHECK2-32-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-32-NEXT: ret i32 [[TMP9]]
+// CHECK2-32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// CHECK2-32-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// CHECK2-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[B:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
+// CHECK2-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// CHECK2-32-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// CHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// CHECK2-32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
+// CHECK2-32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
+// CHECK2-32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
+// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
+// CHECK2-32-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
+// CHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
+// CHECK2-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]]
+// CHECK2-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// CHECK2-32-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i64
+// CHECK2-32-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i32 40, i1 false)
+// CHECK2-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
+// CHECK2-32-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
+// CHECK2-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
+// CHECK2-32-NEXT: store double* [[A]], double** [[TMP13]], align 4
+// CHECK2-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP14]], align 4
+// CHECK2-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP5]], i32* [[TMP16]], align 4
+// CHECK2-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
+// CHECK2-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP19]], align 4
+// CHECK2-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK2-32-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
+// CHECK2-32-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK2-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK2-32-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
+// CHECK2-32-NEXT: store i32 2, i32* [[TMP23]], align 4
+// CHECK2-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP24]], align 4
+// CHECK2-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK2-32-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP26]], align 4
+// CHECK2-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK2-32-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4
+// CHECK2-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP29]], align 4
+// CHECK2-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
+// CHECK2-32-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**
+// CHECK2-32-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 4
+// CHECK2-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
+// CHECK2-32-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**
+// CHECK2-32-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 4
+// CHECK2-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
+// CHECK2-32-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 4
+// CHECK2-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP35]], align 4
+// CHECK2-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK2-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK2-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK2-32-NEXT: store i32 2, i32* [[TMP39]], align 4
+// CHECK2-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK2-32-NEXT: store i32 5, i32* [[TMP40]], align 4
+// CHECK2-32-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK2-32-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 4
+// CHECK2-32-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK2-32-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4
+// CHECK2-32-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK2-32-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 4
+// CHECK2-32-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK2-32-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 4
+// CHECK2-32-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP45]], align 4
+// CHECK2-32-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP46]], align 4
+// CHECK2-32-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP47]], align 8
+// CHECK2-32-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP48]], align 8
+// CHECK2-32-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4
+// CHECK2-32-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4
+// CHECK2-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK2-32-NEXT: store i32 0, i32* [[TMP51]], align 4
+// CHECK2-32-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK2-32-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0
+// CHECK2-32-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK2-32: omp_offload.failed:
+// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
+// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK2-32: omp_offload.cont:
+// CHECK2-32-NEXT: [[TMP54:%.*]] = mul nsw i32 1, [[TMP1]]
+// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP54]]
+// CHECK2-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// CHECK2-32-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
+// CHECK2-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP55]] to i32
+// CHECK2-32-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4
+// CHECK2-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP56]]
+// CHECK2-32-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])
+// CHECK2-32-NEXT: ret i32 [[ADD3]]
+// CHECK2-32-LABEL: define {{[^@]+}}@_ZL7fstatici
+// CHECK2-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// CHECK2-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK2-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK2-32-NEXT: store i8 0, i8* [[AAA]], align 1
+// CHECK2-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
+// CHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK2-32-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
+// CHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
+// CHECK2-32-NEXT: store i8 [[TMP2]], i8* [[CONV]], align 1
+// CHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
+// CHECK2-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
+// CHECK2-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
+// CHECK2-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP8]], align 4
+// CHECK2-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
+// CHECK2-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
+// CHECK2-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP13]], align 4
+// CHECK2-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK2-32-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**
+// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 4
+// CHECK2-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK2-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**
+// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 4
+// CHECK2-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP18]], align 4
+// CHECK2-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK2-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK2-32-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK2-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK2-32-NEXT: store i32 3, i32* [[TMP22]], align 4
+// CHECK2-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK2-32-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 4
+// CHECK2-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK2-32-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4
+// CHECK2-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK2-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 4
+// CHECK2-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK2-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 4
+// CHECK2-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP27]], align 4
+// CHECK2-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP28]], align 4
+// CHECK2-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK2-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP30]], align 8
+// CHECK2-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4
+// CHECK2-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4
+// CHECK2-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK2-32-NEXT: store i32 0, i32* [[TMP33]], align 4
+// CHECK2-32-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK2-32-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
+// CHECK2-32-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK2-32: omp_offload.failed:
+// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK2-32: omp_offload.cont:
+// CHECK2-32-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-32-NEXT: ret i32 [[TMP36]]
+// CHECK2-32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// CHECK2-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK2-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK2-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
+// CHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK2-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
+// CHECK2-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
+// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
+// CHECK2-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP6]], align 4
+// CHECK2-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**
+// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 4
+// CHECK2-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK2-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
+// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 4
+// CHECK2-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK2-32-NEXT: store i8* null, i8** [[TMP11]], align 4
+// CHECK2-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK2-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK2-32-NEXT: store i32 2, i32* [[TMP14]], align 4
+// CHECK2-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK2-32-NEXT: store i32 2, i32* [[TMP15]], align 4
+// CHECK2-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK2-32-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 4
+// CHECK2-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK2-32-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 4
+// CHECK2-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK2-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 4
+// CHECK2-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK2-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 4
+// CHECK2-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP20]], align 4
+// CHECK2-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK2-32-NEXT: store i8** null, i8*** [[TMP21]], align 4
+// CHECK2-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP22]], align 8
+// CHECK2-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK2-32-NEXT: store i64 0, i64* [[TMP23]], align 8
+// CHECK2-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4
+// CHECK2-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK2-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4
+// CHECK2-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK2-32-NEXT: store i32 0, i32* [[TMP26]], align 4
+// CHECK2-32-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK2-32-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
+// CHECK2-32-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK2-32: omp_offload.failed:
+// CHECK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK2-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK2-32: omp_offload.cont:
+// CHECK2-32-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-32-NEXT: ret i32 [[TMP29]]
+// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// CHECK2-32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// CHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
+// CHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// CHECK2-32-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// CHECK2-32-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// CHECK2-32-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4
+// CHECK2-32-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// CHECK2-32-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
+// CHECK2-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK2-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// CHECK2-32-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// CHECK2-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// CHECK2-32-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// CHECK2-32-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)
+// CHECK2-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// CHECK2-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
+// CHECK2-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
+// CHECK2-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK2-32-NEXT: store double [[ADD]], double* [[A]], align 4
+// CHECK2-32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK2-32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4
+// CHECK2-32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// CHECK2-32-NEXT: store double [[INC]], double* [[A4]], align 4
+// CHECK2-32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
+// CHECK2-32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
+// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]
+// CHECK2-32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// CHECK2-32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
+// CHECK2-32-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// CHECK2-32-NEXT: ret void
+// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// CHECK2-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// CHECK2-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK2-32-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
+// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// CHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
+// CHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK2-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// CHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK2-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
+// CHECK2-32-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32
+// CHECK2-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
+// CHECK2-32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
+// CHECK2-32-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1
+// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// CHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK2-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1
+// CHECK2-32-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
+// CHECK2-32-NEXT: ret void
+// CHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// CHECK2-32-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// CHECK2-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// CHECK2-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK2-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// CHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK2-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// CHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// CHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK2-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK2-32-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// CHECK2-32-NEXT: ret void
+// CHECK2-32-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CHECK2-32-SAME: () #[[ATTR5:[0-9]+]] {
+// CHECK2-32-NEXT: entry:
+// CHECK2-32-NEXT: call void @__tgt_register_requires(i64 1)
+// CHECK2-32-NEXT: ret void
+// CHECK3-32-LABEL: define {{[^@]+}}@_Z3fooiPd
+// CHECK3-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK3-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[AA:%.*]] = alloca i16, align 2
+// CHECK3-32-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// CHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK3-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// CHECK3-32-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK3-32-NEXT: [[P:%.*]] = alloca i32*, align 64
+// CHECK3-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-32-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK3-32-NEXT: store i16 0, i16* [[AA]], align 2
+// CHECK3-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
+// CHECK3-32-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
+// CHECK3-32-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
+// CHECK3-32-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
+// CHECK3-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
+// CHECK3-32-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
+// CHECK3-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// CHECK3-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 [[TMP4]], i32* [[X]], align 4
+// CHECK3-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4
+// CHECK3-32-NEXT: store i32* [[A]], i32** [[P]], align 64
+// CHECK3-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-32-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 4
+// CHECK3-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK3-32-NEXT: [[TMP8:%.*]] = load i32*, i32** [[P]], align 64
+// CHECK3-32-NEXT: [[TMP9:%.*]] = load i32, i32* @ga, align 4
+// CHECK3-32-NEXT: store i32 [[TMP9]], i32* [[GA_CASTED]], align 4
+// CHECK3-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[GA_CASTED]], align 4
+// CHECK3-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP7]], i32* [[TMP12]], align 4
+// CHECK3-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP7]], i32* [[TMP14]], align 4
+// CHECK3-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP15]], align 4
+// CHECK3-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32**
+// CHECK3-32-NEXT: store i32* [[TMP8]], i32** [[TMP17]], align 4
+// CHECK3-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
+// CHECK3-32-NEXT: store i32* [[TMP8]], i32** [[TMP19]], align 4
+// CHECK3-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP20]], align 4
+// CHECK3-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK3-32-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP10]], i32* [[TMP22]], align 4
+// CHECK3-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK3-32-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP10]], i32* [[TMP24]], align 4
+// CHECK3-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP25]], align 4
+// CHECK3-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK3-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK3-32-NEXT: store i32 2, i32* [[TMP28]], align 4
+// CHECK3-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK3-32-NEXT: store i32 3, i32* [[TMP29]], align 4
+// CHECK3-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK3-32-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 4
+// CHECK3-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK3-32-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4
+// CHECK3-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK3-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP32]], align 4
+// CHECK3-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK3-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP33]], align 4
+// CHECK3-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP34]], align 4
+// CHECK3-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP35]], align 4
+// CHECK3-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP36]], align 8
+// CHECK3-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP37]], align 8
+// CHECK3-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP38]], align 4
+// CHECK3-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP39]], align 4
+// CHECK3-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK3-32-NEXT: store i32 0, i32* [[TMP40]], align 4
+// CHECK3-32-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK3-32-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0
+// CHECK3-32-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK3-32: omp_offload.failed:
+// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], i32* [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]]
+// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK3-32: omp_offload.cont:
+// CHECK3-32-NEXT: [[TMP43:%.*]] = load i16, i16* [[AA]], align 2
+// CHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
+// CHECK3-32-NEXT: store i16 [[TMP43]], i16* [[CONV]], align 2
+// CHECK3-32-NEXT: [[TMP44:%.*]] = load i32, i32* [[AA_CASTED]], align 4
+// CHECK3-32-NEXT: [[TMP45:%.*]] = mul nuw i32 [[TMP0]], 4
+// CHECK3-32-NEXT: [[TMP46:%.*]] = sext i32 [[TMP45]] to i64
+// CHECK3-32-NEXT: [[TMP47:%.*]] = mul nuw i32 5, [[TMP2]]
+// CHECK3-32-NEXT: [[TMP48:%.*]] = mul nuw i32 [[TMP47]], 8
+// CHECK3-32-NEXT: [[TMP49:%.*]] = sext i32 [[TMP48]] to i64
+// CHECK3-32-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i32 72, i1 false)
+// CHECK3-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP44]], i32* [[TMP52]], align 4
+// CHECK3-32-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP44]], i32* [[TMP54]], align 4
+// CHECK3-32-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP55]], align 4
+// CHECK3-32-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**
+// CHECK3-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 4
+// CHECK3-32-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**
+// CHECK3-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 4
+// CHECK3-32-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP60]], align 4
+// CHECK3-32-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2
+// CHECK3-32-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP0]], i32* [[TMP62]], align 4
+// CHECK3-32-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2
+// CHECK3-32-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP0]], i32* [[TMP64]], align 4
+// CHECK3-32-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP65]], align 4
+// CHECK3-32-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 3
+// CHECK3-32-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**
+// CHECK3-32-NEXT: store float* [[VLA]], float** [[TMP67]], align 4
+// CHECK3-32-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 3
+// CHECK3-32-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**
+// CHECK3-32-NEXT: store float* [[VLA]], float** [[TMP69]], align 4
+// CHECK3-32-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
+// CHECK3-32-NEXT: store i64 [[TMP46]], i64* [[TMP70]], align 4
+// CHECK3-32-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 3
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP71]], align 4
+// CHECK3-32-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 4
+// CHECK3-32-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**
+// CHECK3-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 4
+// CHECK3-32-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 4
+// CHECK3-32-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**
+// CHECK3-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 4
+// CHECK3-32-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 4
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP76]], align 4
+// CHECK3-32-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 5
+// CHECK3-32-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32*
+// CHECK3-32-NEXT: store i32 5, i32* [[TMP78]], align 4
+// CHECK3-32-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 5
+// CHECK3-32-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*
+// CHECK3-32-NEXT: store i32 5, i32* [[TMP80]], align 4
+// CHECK3-32-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 5
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP81]], align 4
+// CHECK3-32-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 6
+// CHECK3-32-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP2]], i32* [[TMP83]], align 4
+// CHECK3-32-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 6
+// CHECK3-32-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP2]], i32* [[TMP85]], align 4
+// CHECK3-32-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 6
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP86]], align 4
+// CHECK3-32-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 7
+// CHECK3-32-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**
+// CHECK3-32-NEXT: store double* [[VLA1]], double** [[TMP88]], align 4
+// CHECK3-32-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 7
+// CHECK3-32-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**
+// CHECK3-32-NEXT: store double* [[VLA1]], double** [[TMP90]], align 4
+// CHECK3-32-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
+// CHECK3-32-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 4
+// CHECK3-32-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 7
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP92]], align 4
+// CHECK3-32-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 8
+// CHECK3-32-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**
+// CHECK3-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 4
+// CHECK3-32-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 8
+// CHECK3-32-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**
+// CHECK3-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 4
+// CHECK3-32-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 8
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP97]], align 4
+// CHECK3-32-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK3-32-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK3-32-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 0
+// CHECK3-32-NEXT: store i32 2, i32* [[TMP101]], align 4
+// CHECK3-32-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 1
+// CHECK3-32-NEXT: store i32 9, i32* [[TMP102]], align 4
+// CHECK3-32-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 2
+// CHECK3-32-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 4
+// CHECK3-32-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 3
+// CHECK3-32-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 4
+// CHECK3-32-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 4
+// CHECK3-32-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 4
+// CHECK3-32-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 5
+// CHECK3-32-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 4
+// CHECK3-32-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 6
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP107]], align 4
+// CHECK3-32-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 7
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP108]], align 4
+// CHECK3-32-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 8
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP109]], align 8
+// CHECK3-32-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 9
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP110]], align 8
+// CHECK3-32-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 10
+// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4
+// CHECK3-32-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 11
+// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4
+// CHECK3-32-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 12
+// CHECK3-32-NEXT: store i32 0, i32* [[TMP113]], align 4
+// CHECK3-32-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]])
+// CHECK3-32-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0
+// CHECK3-32-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CHECK3-32: omp_offload.failed6:
+// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP44]], [10 x float]* [[B]], i32 [[TMP0]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP2]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
+// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CHECK3-32: omp_offload.cont7:
+// CHECK3-32-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**
+// CHECK3-32-NEXT: store double* [[TMP116]], double** [[TMP118]], align 4
+// CHECK3-32-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**
+// CHECK3-32-NEXT: store double* [[TMP116]], double** [[TMP120]], align 4
+// CHECK3-32-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP121]], align 4
+// CHECK3-32-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**
+// CHECK3-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 4
+// CHECK3-32-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**
+// CHECK3-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 4
+// CHECK3-32-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP126]], align 4
+// CHECK3-32-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
+// CHECK3-32-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK3-32-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 0
+// CHECK3-32-NEXT: store i32 2, i32* [[TMP129]], align 4
+// CHECK3-32-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 1
+// CHECK3-32-NEXT: store i32 2, i32* [[TMP130]], align 4
+// CHECK3-32-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 2
+// CHECK3-32-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 4
+// CHECK3-32-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 3
+// CHECK3-32-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 4
+// CHECK3-32-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 4
+// CHECK3-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 4
+// CHECK3-32-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 5
+// CHECK3-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 4
+// CHECK3-32-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 6
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP135]], align 4
+// CHECK3-32-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 7
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP136]], align 4
+// CHECK3-32-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 8
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP137]], align 8
+// CHECK3-32-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 9
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP138]], align 8
+// CHECK3-32-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 10
+// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4
+// CHECK3-32-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 11
+// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4
+// CHECK3-32-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 12
+// CHECK3-32-NEXT: store i32 0, i32* [[TMP141]], align 4
+// CHECK3-32-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]])
+// CHECK3-32-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0
+// CHECK3-32-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]
+// CHECK3-32: omp_offload.failed12:
+// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]
+// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT13]]
+// CHECK3-32: omp_offload.cont13:
+// CHECK3-32-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-32-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])
+// CHECK3-32-NEXT: ret i32 [[TMP144]]
+// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// CHECK3-32-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4
+// CHECK3-32-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK3-32-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4
+// CHECK3-32-NEXT: ret void
+// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// CHECK3-32-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
+// CHECK3-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
+// CHECK3-32-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
+// CHECK3-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
+// CHECK3-32-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
+// CHECK3-32-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// CHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK3-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// CHECK3-32-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
+// CHECK3-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// CHECK3-32-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
+// CHECK3-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// CHECK3-32-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
+// CHECK3-32-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
+// CHECK3-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
+// CHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
+// CHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// CHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
+// CHECK3-32-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// CHECK3-32-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)
+// CHECK3-32-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// CHECK3-32-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4
+// CHECK3-32-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
+// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK3-32-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4
+// CHECK3-32-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// CHECK3-32-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)
+// CHECK3-32-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// CHECK3-32-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)
+// CHECK3-32-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// CHECK3-32-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8
+// CHECK3-32-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4
+// CHECK3-32-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4
+// CHECK3-32-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// CHECK3-32-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
+// CHECK3-32-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// CHECK3-32-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)
+// CHECK3-32-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// CHECK3-32-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)
+// CHECK3-32-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// CHECK3-32-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// CHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// CHECK3-32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK3-32-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2
+// CHECK3-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// CHECK3-32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3
+// CHECK3-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// CHECK3-32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1
+// CHECK3-32-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
+// CHECK3-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// CHECK3-32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]
+// CHECK3-32-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]
+// CHECK3-32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3
+// CHECK3-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// CHECK3-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// CHECK3-32-NEXT: store i64 1, i64* [[X]], align 4
+// CHECK3-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// CHECK3-32-NEXT: store i8 1, i8* [[Y]], align 4
+// CHECK3-32-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// CHECK3-32-NEXT: ret void
+// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// CHECK3-32-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK3-32-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4
+// CHECK3-32-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK3-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK3-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*
+// CHECK3-32-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*
+// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 8, i1 false)
+// CHECK3-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK3-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double
+// CHECK3-32-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i32 0
+// CHECK3-32-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4
+// CHECK3-32-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK3-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 0
+// CHECK3-32-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 4
+// CHECK3-32-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// CHECK3-32-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 4
+// CHECK3-32-NEXT: ret void
+// CHECK3-32-LABEL: define {{[^@]+}}@_Z3bariPd
+// CHECK3-32-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK3-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
+// CHECK3-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK3-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK3-32-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])
+// CHECK3-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// CHECK3-32-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// CHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])
+// CHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// CHECK3-32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// CHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])
+// CHECK3-32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// CHECK3-32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// CHECK3-32-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])
+// CHECK3-32-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-32-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// CHECK3-32-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// CHECK3-32-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-32-NEXT: ret i32 [[TMP9]]
+// CHECK3-32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// CHECK3-32-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// CHECK3-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[B:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
+// CHECK3-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// CHECK3-32-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// CHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// CHECK3-32-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
+// CHECK3-32-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
+// CHECK3-32-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
+// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
+// CHECK3-32-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
+// CHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
+// CHECK3-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]]
+// CHECK3-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// CHECK3-32-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i64
+// CHECK3-32-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i32 40, i1 false)
+// CHECK3-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
+// CHECK3-32-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
+// CHECK3-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
+// CHECK3-32-NEXT: store double* [[A]], double** [[TMP13]], align 4
+// CHECK3-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP14]], align 4
+// CHECK3-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP5]], i32* [[TMP16]], align 4
+// CHECK3-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
+// CHECK3-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP19]], align 4
+// CHECK3-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK3-32-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
+// CHECK3-32-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK3-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK3-32-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
+// CHECK3-32-NEXT: store i32 2, i32* [[TMP23]], align 4
+// CHECK3-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP24]], align 4
+// CHECK3-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK3-32-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP26]], align 4
+// CHECK3-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK3-32-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4
+// CHECK3-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP29]], align 4
+// CHECK3-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
+// CHECK3-32-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**
+// CHECK3-32-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 4
+// CHECK3-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
+// CHECK3-32-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**
+// CHECK3-32-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 4
+// CHECK3-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
+// CHECK3-32-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 4
+// CHECK3-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP35]], align 4
+// CHECK3-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK3-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK3-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK3-32-NEXT: store i32 2, i32* [[TMP39]], align 4
+// CHECK3-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK3-32-NEXT: store i32 5, i32* [[TMP40]], align 4
+// CHECK3-32-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK3-32-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 4
+// CHECK3-32-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK3-32-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4
+// CHECK3-32-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK3-32-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 4
+// CHECK3-32-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK3-32-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 4
+// CHECK3-32-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP45]], align 4
+// CHECK3-32-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP46]], align 4
+// CHECK3-32-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP47]], align 8
+// CHECK3-32-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP48]], align 8
+// CHECK3-32-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4
+// CHECK3-32-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4
+// CHECK3-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK3-32-NEXT: store i32 0, i32* [[TMP51]], align 4
+// CHECK3-32-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK3-32-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0
+// CHECK3-32-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK3-32: omp_offload.failed:
+// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
+// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK3-32: omp_offload.cont:
+// CHECK3-32-NEXT: [[TMP54:%.*]] = mul nsw i32 1, [[TMP1]]
+// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP54]]
+// CHECK3-32-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// CHECK3-32-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
+// CHECK3-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP55]] to i32
+// CHECK3-32-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4
+// CHECK3-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP56]]
+// CHECK3-32-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])
+// CHECK3-32-NEXT: ret i32 [[ADD3]]
+// CHECK3-32-LABEL: define {{[^@]+}}@_ZL7fstatici
+// CHECK3-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// CHECK3-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK3-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK3-32-NEXT: store i8 0, i8* [[AAA]], align 1
+// CHECK3-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
+// CHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK3-32-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
+// CHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
+// CHECK3-32-NEXT: store i8 [[TMP2]], i8* [[CONV]], align 1
+// CHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
+// CHECK3-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
+// CHECK3-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
+// CHECK3-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP8]], align 4
+// CHECK3-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
+// CHECK3-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
+// CHECK3-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP13]], align 4
+// CHECK3-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK3-32-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**
+// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 4
+// CHECK3-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK3-32-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**
+// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 4
+// CHECK3-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP18]], align 4
+// CHECK3-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK3-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK3-32-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK3-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK3-32-NEXT: store i32 3, i32* [[TMP22]], align 4
+// CHECK3-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK3-32-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 4
+// CHECK3-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK3-32-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4
+// CHECK3-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK3-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 4
+// CHECK3-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK3-32-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 4
+// CHECK3-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP27]], align 4
+// CHECK3-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP28]], align 4
+// CHECK3-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK3-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP30]], align 8
+// CHECK3-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4
+// CHECK3-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4
+// CHECK3-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK3-32-NEXT: store i32 0, i32* [[TMP33]], align 4
+// CHECK3-32-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK3-32-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
+// CHECK3-32-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK3-32: omp_offload.failed:
+// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK3-32: omp_offload.cont:
+// CHECK3-32-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-32-NEXT: ret i32 [[TMP36]]
+// CHECK3-32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// CHECK3-32-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK3-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK3-32-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-32-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
+// CHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK3-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
+// CHECK3-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
+// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
+// CHECK3-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP6]], align 4
+// CHECK3-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**
+// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 4
+// CHECK3-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK3-32-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
+// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 4
+// CHECK3-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK3-32-NEXT: store i8* null, i8** [[TMP11]], align 4
+// CHECK3-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK3-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK3-32-NEXT: store i32 2, i32* [[TMP14]], align 4
+// CHECK3-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK3-32-NEXT: store i32 2, i32* [[TMP15]], align 4
+// CHECK3-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK3-32-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 4
+// CHECK3-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK3-32-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 4
+// CHECK3-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK3-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 4
+// CHECK3-32-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK3-32-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 4
+// CHECK3-32-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP20]], align 4
+// CHECK3-32-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK3-32-NEXT: store i8** null, i8*** [[TMP21]], align 4
+// CHECK3-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP22]], align 8
+// CHECK3-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK3-32-NEXT: store i64 0, i64* [[TMP23]], align 8
+// CHECK3-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4
+// CHECK3-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK3-32-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4
+// CHECK3-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK3-32-NEXT: store i32 0, i32* [[TMP26]], align 4
+// CHECK3-32-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK3-32-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
+// CHECK3-32-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK3-32: omp_offload.failed:
+// CHECK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK3-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK3-32: omp_offload.cont:
+// CHECK3-32-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-32-NEXT: ret i32 [[TMP29]]
+// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// CHECK3-32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// CHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
+// CHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// CHECK3-32-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// CHECK3-32-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// CHECK3-32-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4
+// CHECK3-32-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// CHECK3-32-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
+// CHECK3-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK3-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// CHECK3-32-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// CHECK3-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// CHECK3-32-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// CHECK3-32-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)
+// CHECK3-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// CHECK3-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
+// CHECK3-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
+// CHECK3-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK3-32-NEXT: store double [[ADD]], double* [[A]], align 4
+// CHECK3-32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK3-32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4
+// CHECK3-32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// CHECK3-32-NEXT: store double [[INC]], double* [[A4]], align 4
+// CHECK3-32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
+// CHECK3-32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
+// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]
+// CHECK3-32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// CHECK3-32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
+// CHECK3-32-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// CHECK3-32-NEXT: ret void
+// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// CHECK3-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// CHECK3-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK3-32-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
+// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// CHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
+// CHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK3-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// CHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK3-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
+// CHECK3-32-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32
+// CHECK3-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
+// CHECK3-32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
+// CHECK3-32-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1
+// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// CHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK3-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1
+// CHECK3-32-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
+// CHECK3-32-NEXT: ret void
+// CHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// CHECK3-32-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// CHECK3-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// CHECK3-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK3-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// CHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK3-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// CHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// CHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK3-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK3-32-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// CHECK3-32-NEXT: ret void
+// CHECK3-32-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CHECK3-32-SAME: () #[[ATTR5:[0-9]+]] {
+// CHECK3-32-NEXT: entry:
+// CHECK3-32-NEXT: call void @__tgt_register_requires(i64 1)
+// CHECK3-32-NEXT: ret void
+// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// TCHECK-64-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {
+// TCHECK-64-NEXT: entry:
+// TCHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8
+// TCHECK-64-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK-64-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8
+// TCHECK-64-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8
+// TCHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*
+// TCHECK-64-NEXT: ret void
+// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// TCHECK-64-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
+// TCHECK-64-NEXT: entry:
+// TCHECK-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
+// TCHECK-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
+// TCHECK-64-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
+// TCHECK-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
+// TCHECK-64-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
+// TCHECK-64-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// TCHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// TCHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// TCHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// TCHECK-64-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
+// TCHECK-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
+// TCHECK-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// TCHECK-64-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
+// TCHECK-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
+// TCHECK-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// TCHECK-64-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
+// TCHECK-64-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
+// TCHECK-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
+// TCHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
+// TCHECK-64-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// TCHECK-64-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
+// TCHECK-64-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// TCHECK-64-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)
+// TCHECK-64-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// TCHECK-64-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8
+// TCHECK-64-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
+// TCHECK-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// TCHECK-64-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4
+// TCHECK-64-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// TCHECK-64-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)
+// TCHECK-64-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// TCHECK-64-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)
+// TCHECK-64-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// TCHECK-64-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8
+// TCHECK-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// TCHECK-64-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8
+// TCHECK-64-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// TCHECK-64-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8
+// TCHECK-64-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// TCHECK-64-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)
+// TCHECK-64-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// TCHECK-64-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)
+// TCHECK-64-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// TCHECK-64-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// TCHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// TCHECK-64-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// TCHECK-64-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2
+// TCHECK-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// TCHECK-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3
+// TCHECK-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// TCHECK-64-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1
+// TCHECK-64-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2
+// TCHECK-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// TCHECK-64-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]
+// TCHECK-64-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]
+// TCHECK-64-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
+// TCHECK-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// TCHECK-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// TCHECK-64-NEXT: store i64 1, i64* [[X]], align 8
+// TCHECK-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// TCHECK-64-NEXT: store i8 1, i8* [[Y]], align 8
+// TCHECK-64-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// TCHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// TCHECK-64-NEXT: ret void
+// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// TCHECK-64-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
+// TCHECK-64-NEXT: entry:
+// TCHECK-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// TCHECK-64-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8
+// TCHECK-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// TCHECK-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8
+// TCHECK-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0
+// TCHECK-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4
+// TCHECK-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
+// TCHECK-64-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 0
+// TCHECK-64-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8
+// TCHECK-64-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// TCHECK-64-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i64 0
+// TCHECK-64-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 8
+// TCHECK-64-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00
+// TCHECK-64-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 8
+// TCHECK-64-NEXT: ret void
+// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// TCHECK-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK-64-NEXT: entry:
+// TCHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// TCHECK-64-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
+// TCHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK-64-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
+// TCHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// TCHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
+// TCHECK-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*
+// TCHECK-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// TCHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// TCHECK-64-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
+// TCHECK-64-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32
+// TCHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
+// TCHECK-64-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
+// TCHECK-64-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1
+// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2
+// TCHECK-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK-64-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
+// TCHECK-64-NEXT: ret void
+// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// TCHECK-64-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
+// TCHECK-64-NEXT: entry:
+// TCHECK-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// TCHECK-64-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
+// TCHECK-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// TCHECK-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// TCHECK-64-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
+// TCHECK-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// TCHECK-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// TCHECK-64-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// TCHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
+// TCHECK-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// TCHECK-64-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// TCHECK-64-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
+// TCHECK-64-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// TCHECK-64-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
+// TCHECK-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// TCHECK-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8
+// TCHECK-64-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// TCHECK-64-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
+// TCHECK-64-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// TCHECK-64-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)
+// TCHECK-64-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK-64-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double
+// TCHECK-64-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
+// TCHECK-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK-64-NEXT: store double [[ADD]], double* [[A]], align 8
+// TCHECK-64-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK-64-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8
+// TCHECK-64-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// TCHECK-64-NEXT: store double [[INC]], double* [[A5]], align 8
+// TCHECK-64-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
+// TCHECK-64-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]
+// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]
+// TCHECK-64-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// TCHECK-64-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
+// TCHECK-64-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// TCHECK-64-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// TCHECK-64-NEXT: ret void
+// TCHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// TCHECK-64-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK-64-NEXT: entry:
+// TCHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// TCHECK-64-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// TCHECK-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// TCHECK-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// TCHECK-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// TCHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2
+// TCHECK-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK-64-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// TCHECK-64-NEXT: ret void
+// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// TCHECK1-64-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {
+// TCHECK1-64-NEXT: entry:
+// TCHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8
+// TCHECK1-64-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK1-64-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8
+// TCHECK1-64-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8
+// TCHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK1-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*
+// TCHECK1-64-NEXT: ret void
+// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// TCHECK1-64-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
+// TCHECK1-64-NEXT: entry:
+// TCHECK1-64-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
+// TCHECK1-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
+// TCHECK1-64-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
+// TCHECK1-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
+// TCHECK1-64-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
+// TCHECK1-64-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// TCHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// TCHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// TCHECK1-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// TCHECK1-64-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
+// TCHECK1-64-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
+// TCHECK1-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// TCHECK1-64-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
+// TCHECK1-64-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
+// TCHECK1-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// TCHECK1-64-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
+// TCHECK1-64-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
+// TCHECK1-64-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
+// TCHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
+// TCHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// TCHECK1-64-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
+// TCHECK1-64-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// TCHECK1-64-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)
+// TCHECK1-64-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// TCHECK1-64-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8
+// TCHECK1-64-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
+// TCHECK1-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// TCHECK1-64-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4
+// TCHECK1-64-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// TCHECK1-64-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)
+// TCHECK1-64-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// TCHECK1-64-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)
+// TCHECK1-64-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// TCHECK1-64-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8
+// TCHECK1-64-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// TCHECK1-64-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8
+// TCHECK1-64-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// TCHECK1-64-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8
+// TCHECK1-64-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// TCHECK1-64-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)
+// TCHECK1-64-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// TCHECK1-64-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)
+// TCHECK1-64-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// TCHECK1-64-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// TCHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// TCHECK1-64-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// TCHECK1-64-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// TCHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2
+// TCHECK1-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// TCHECK1-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3
+// TCHECK1-64-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// TCHECK1-64-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1
+// TCHECK1-64-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2
+// TCHECK1-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// TCHECK1-64-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]
+// TCHECK1-64-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]
+// TCHECK1-64-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
+// TCHECK1-64-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// TCHECK1-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// TCHECK1-64-NEXT: store i64 1, i64* [[X]], align 8
+// TCHECK1-64-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// TCHECK1-64-NEXT: store i8 1, i8* [[Y]], align 8
+// TCHECK1-64-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// TCHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// TCHECK1-64-NEXT: ret void
+// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// TCHECK1-64-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
+// TCHECK1-64-NEXT: entry:
+// TCHECK1-64-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// TCHECK1-64-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8
+// TCHECK1-64-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// TCHECK1-64-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8
+// TCHECK1-64-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0
+// TCHECK1-64-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4
+// TCHECK1-64-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
+// TCHECK1-64-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// TCHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 0
+// TCHECK1-64-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8
+// TCHECK1-64-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// TCHECK1-64-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i64 0
+// TCHECK1-64-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 8
+// TCHECK1-64-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00
+// TCHECK1-64-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 8
+// TCHECK1-64-NEXT: ret void
+// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// TCHECK1-64-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK1-64-NEXT: entry:
+// TCHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// TCHECK1-64-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
+// TCHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK1-64-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
+// TCHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// TCHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK1-64-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
+// TCHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*
+// TCHECK1-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// TCHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK1-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// TCHECK1-64-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
+// TCHECK1-64-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32
+// TCHECK1-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
+// TCHECK1-64-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
+// TCHECK1-64-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1
+// TCHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2
+// TCHECK1-64-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK1-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK1-64-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
+// TCHECK1-64-NEXT: ret void
+// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// TCHECK1-64-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
+// TCHECK1-64-NEXT: entry:
+// TCHECK1-64-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// TCHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
+// TCHECK1-64-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// TCHECK1-64-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// TCHECK1-64-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
+// TCHECK1-64-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// TCHECK1-64-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// TCHECK1-64-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// TCHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
+// TCHECK1-64-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// TCHECK1-64-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// TCHECK1-64-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
+// TCHECK1-64-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// TCHECK1-64-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
+// TCHECK1-64-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// TCHECK1-64-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8
+// TCHECK1-64-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// TCHECK1-64-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
+// TCHECK1-64-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// TCHECK1-64-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)
+// TCHECK1-64-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK1-64-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double
+// TCHECK1-64-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
+// TCHECK1-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK1-64-NEXT: store double [[ADD]], double* [[A]], align 8
+// TCHECK1-64-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK1-64-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8
+// TCHECK1-64-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// TCHECK1-64-NEXT: store double [[INC]], double* [[A5]], align 8
+// TCHECK1-64-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
+// TCHECK1-64-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]
+// TCHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]
+// TCHECK1-64-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// TCHECK1-64-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
+// TCHECK1-64-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// TCHECK1-64-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// TCHECK1-64-NEXT: ret void
+// TCHECK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// TCHECK1-64-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK1-64-NEXT: entry:
+// TCHECK1-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-64-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// TCHECK1-64-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK1-64-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK1-64-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// TCHECK1-64-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK1-64-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// TCHECK1-64-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK1-64-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK1-64-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// TCHECK1-64-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK1-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK1-64-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// TCHECK1-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2
+// TCHECK1-64-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK1-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK1-64-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// TCHECK1-64-NEXT: ret void
+// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// TCHECK2-32-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {
+// TCHECK2-32-NEXT: entry:
+// TCHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4
+// TCHECK2-32-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK2-32-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4
+// TCHECK2-32-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4
+// TCHECK2-32-NEXT: ret void
+// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// TCHECK2-32-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
+// TCHECK2-32-NEXT: entry:
+// TCHECK2-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
+// TCHECK2-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
+// TCHECK2-32-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
+// TCHECK2-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
+// TCHECK2-32-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
+// TCHECK2-32-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// TCHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// TCHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// TCHECK2-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// TCHECK2-32-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
+// TCHECK2-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
+// TCHECK2-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// TCHECK2-32-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
+// TCHECK2-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
+// TCHECK2-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// TCHECK2-32-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
+// TCHECK2-32-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
+// TCHECK2-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
+// TCHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
+// TCHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// TCHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
+// TCHECK2-32-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// TCHECK2-32-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)
+// TCHECK2-32-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// TCHECK2-32-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4
+// TCHECK2-32-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
+// TCHECK2-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// TCHECK2-32-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4
+// TCHECK2-32-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// TCHECK2-32-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)
+// TCHECK2-32-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// TCHECK2-32-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)
+// TCHECK2-32-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// TCHECK2-32-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8
+// TCHECK2-32-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4
+// TCHECK2-32-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4
+// TCHECK2-32-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// TCHECK2-32-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
+// TCHECK2-32-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// TCHECK2-32-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)
+// TCHECK2-32-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// TCHECK2-32-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)
+// TCHECK2-32-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// TCHECK2-32-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// TCHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// TCHECK2-32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// TCHECK2-32-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// TCHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2
+// TCHECK2-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// TCHECK2-32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3
+// TCHECK2-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// TCHECK2-32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1
+// TCHECK2-32-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
+// TCHECK2-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// TCHECK2-32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]
+// TCHECK2-32-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]
+// TCHECK2-32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3
+// TCHECK2-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// TCHECK2-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// TCHECK2-32-NEXT: store i64 1, i64* [[X]], align 4
+// TCHECK2-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// TCHECK2-32-NEXT: store i8 1, i8* [[Y]], align 4
+// TCHECK2-32-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// TCHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// TCHECK2-32-NEXT: ret void
+// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// TCHECK2-32-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
+// TCHECK2-32-NEXT: entry:
+// TCHECK2-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// TCHECK2-32-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4
+// TCHECK2-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// TCHECK2-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4
+// TCHECK2-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0
+// TCHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4
+// TCHECK2-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
+// TCHECK2-32-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// TCHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 0
+// TCHECK2-32-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4
+// TCHECK2-32-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// TCHECK2-32-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i32 0
+// TCHECK2-32-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 4
+// TCHECK2-32-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00
+// TCHECK2-32-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 4
+// TCHECK2-32-NEXT: ret void
+// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// TCHECK2-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK2-32-NEXT: entry:
+// TCHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// TCHECK2-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK2-32-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
+// TCHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// TCHECK2-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
+// TCHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK2-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// TCHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// TCHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK2-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
+// TCHECK2-32-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32
+// TCHECK2-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
+// TCHECK2-32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
+// TCHECK2-32-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1
+// TCHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// TCHECK2-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK2-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK2-32-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
+// TCHECK2-32-NEXT: ret void
+// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// TCHECK2-32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
+// TCHECK2-32-NEXT: entry:
+// TCHECK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// TCHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
+// TCHECK2-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// TCHECK2-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// TCHECK2-32-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
+// TCHECK2-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// TCHECK2-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// TCHECK2-32-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// TCHECK2-32-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// TCHECK2-32-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4
+// TCHECK2-32-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// TCHECK2-32-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
+// TCHECK2-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// TCHECK2-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// TCHECK2-32-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// TCHECK2-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// TCHECK2-32-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// TCHECK2-32-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)
+// TCHECK2-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// TCHECK2-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
+// TCHECK2-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
+// TCHECK2-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK2-32-NEXT: store double [[ADD]], double* [[A]], align 4
+// TCHECK2-32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK2-32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4
+// TCHECK2-32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// TCHECK2-32-NEXT: store double [[INC]], double* [[A4]], align 4
+// TCHECK2-32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
+// TCHECK2-32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
+// TCHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]
+// TCHECK2-32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// TCHECK2-32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
+// TCHECK2-32-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// TCHECK2-32-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// TCHECK2-32-NEXT: ret void
+// TCHECK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// TCHECK2-32-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK2-32-NEXT: entry:
+// TCHECK2-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// TCHECK2-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK2-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK2-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// TCHECK2-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK2-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK2-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// TCHECK2-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// TCHECK2-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK2-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// TCHECK2-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// TCHECK2-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK2-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK2-32-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// TCHECK2-32-NEXT: ret void
+// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// TCHECK3-32-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {
+// TCHECK3-32-NEXT: entry:
+// TCHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4
+// TCHECK3-32-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK3-32-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4
+// TCHECK3-32-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4
+// TCHECK3-32-NEXT: ret void
+// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// TCHECK3-32-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
+// TCHECK3-32-NEXT: entry:
+// TCHECK3-32-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
+// TCHECK3-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
+// TCHECK3-32-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
+// TCHECK3-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
+// TCHECK3-32-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
+// TCHECK3-32-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// TCHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// TCHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// TCHECK3-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// TCHECK3-32-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
+// TCHECK3-32-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
+// TCHECK3-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// TCHECK3-32-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
+// TCHECK3-32-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
+// TCHECK3-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// TCHECK3-32-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
+// TCHECK3-32-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
+// TCHECK3-32-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
+// TCHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
+// TCHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// TCHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
+// TCHECK3-32-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// TCHECK3-32-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)
+// TCHECK3-32-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// TCHECK3-32-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4
+// TCHECK3-32-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
+// TCHECK3-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// TCHECK3-32-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4
+// TCHECK3-32-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// TCHECK3-32-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)
+// TCHECK3-32-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// TCHECK3-32-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)
+// TCHECK3-32-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// TCHECK3-32-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8
+// TCHECK3-32-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4
+// TCHECK3-32-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4
+// TCHECK3-32-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// TCHECK3-32-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
+// TCHECK3-32-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// TCHECK3-32-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)
+// TCHECK3-32-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// TCHECK3-32-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)
+// TCHECK3-32-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// TCHECK3-32-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// TCHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// TCHECK3-32-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// TCHECK3-32-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// TCHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2
+// TCHECK3-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// TCHECK3-32-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3
+// TCHECK3-32-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// TCHECK3-32-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1
+// TCHECK3-32-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
+// TCHECK3-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// TCHECK3-32-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]
+// TCHECK3-32-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]
+// TCHECK3-32-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3
+// TCHECK3-32-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// TCHECK3-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// TCHECK3-32-NEXT: store i64 1, i64* [[X]], align 4
+// TCHECK3-32-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// TCHECK3-32-NEXT: store i8 1, i8* [[Y]], align 4
+// TCHECK3-32-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// TCHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// TCHECK3-32-NEXT: ret void
+// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// TCHECK3-32-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
+// TCHECK3-32-NEXT: entry:
+// TCHECK3-32-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// TCHECK3-32-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4
+// TCHECK3-32-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// TCHECK3-32-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4
+// TCHECK3-32-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0
+// TCHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4
+// TCHECK3-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
+// TCHECK3-32-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// TCHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 0
+// TCHECK3-32-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4
+// TCHECK3-32-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// TCHECK3-32-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i32 0
+// TCHECK3-32-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 4
+// TCHECK3-32-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00
+// TCHECK3-32-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 4
+// TCHECK3-32-NEXT: ret void
+// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// TCHECK3-32-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK3-32-NEXT: entry:
+// TCHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// TCHECK3-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK3-32-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
+// TCHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// TCHECK3-32-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
+// TCHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK3-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// TCHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// TCHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK3-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
+// TCHECK3-32-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32
+// TCHECK3-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
+// TCHECK3-32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
+// TCHECK3-32-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1
+// TCHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// TCHECK3-32-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK3-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK3-32-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
+// TCHECK3-32-NEXT: ret void
+// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// TCHECK3-32-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
+// TCHECK3-32-NEXT: entry:
+// TCHECK3-32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// TCHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
+// TCHECK3-32-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// TCHECK3-32-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// TCHECK3-32-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
+// TCHECK3-32-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// TCHECK3-32-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// TCHECK3-32-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// TCHECK3-32-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// TCHECK3-32-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4
+// TCHECK3-32-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// TCHECK3-32-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
+// TCHECK3-32-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// TCHECK3-32-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// TCHECK3-32-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// TCHECK3-32-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// TCHECK3-32-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// TCHECK3-32-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)
+// TCHECK3-32-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// TCHECK3-32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
+// TCHECK3-32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
+// TCHECK3-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK3-32-NEXT: store double [[ADD]], double* [[A]], align 4
+// TCHECK3-32-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK3-32-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4
+// TCHECK3-32-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// TCHECK3-32-NEXT: store double [[INC]], double* [[A4]], align 4
+// TCHECK3-32-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
+// TCHECK3-32-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
+// TCHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]
+// TCHECK3-32-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// TCHECK3-32-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
+// TCHECK3-32-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// TCHECK3-32-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// TCHECK3-32-NEXT: ret void
+// TCHECK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// TCHECK3-32-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK3-32-NEXT: entry:
+// TCHECK3-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-32-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// TCHECK3-32-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK3-32-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK3-32-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// TCHECK3-32-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK3-32-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK3-32-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// TCHECK3-32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// TCHECK3-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK3-32-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// TCHECK3-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// TCHECK3-32-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK3-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK3-32-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// TCHECK3-32-NEXT: ret void
+// CHECK0-LABEL: define {{[^@]+}}@_Z3fooiPd
+// CHECK0-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK0-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK0-NEXT: [[AA:%.*]] = alloca i16, align 2
+// CHECK0-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// CHECK0-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK0-NEXT: [[P:%.*]] = alloca i32*, align 64
+// CHECK0-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK0-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [9 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [9 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [9 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
+// CHECK0-NEXT: [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK0-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK0-NEXT: store i16 0, i16* [[AA]], align 2
+// CHECK0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK0-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// CHECK0-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
+// CHECK0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
+// CHECK0-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK0-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// CHECK0-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
+// CHECK0-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
+// CHECK0-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: store i32 [[TMP6]], i32* [[X]], align 4
+// CHECK0-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4
+// CHECK0-NEXT: store i32* [[A]], i32** [[P]], align 64
+// CHECK0-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK0-NEXT: store i32 [[TMP8]], i32* [[CONV]], align 4
+// CHECK0-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK0-NEXT: [[TMP10:%.*]] = load i32*, i32** [[P]], align 64
+// CHECK0-NEXT: [[TMP11:%.*]] = load i32, i32* @ga, align 4
+// CHECK0-NEXT: [[CONV2:%.*]] = bitcast i64* [[GA_CASTED]] to i32*
+// CHECK0-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4
+// CHECK0-NEXT: [[TMP12:%.*]] = load i64, i64* [[GA_CASTED]], align 8
+// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*
+// CHECK0-NEXT: store i64 [[TMP9]], i64* [[TMP14]], align 8
+// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
+// CHECK0-NEXT: store i64 [[TMP9]], i64* [[TMP16]], align 8
+// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK0-NEXT: store i8* null, i8** [[TMP17]], align 8
+// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
+// CHECK0-NEXT: store i32* [[TMP10]], i32** [[TMP19]], align 8
+// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**
+// CHECK0-NEXT: store i32* [[TMP10]], i32** [[TMP21]], align 8
+// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK0-NEXT: store i8* null, i8** [[TMP22]], align 8
+// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK0-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
+// CHECK0-NEXT: store i64 [[TMP12]], i64* [[TMP24]], align 8
+// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK0-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
+// CHECK0-NEXT: store i64 [[TMP12]], i64* [[TMP26]], align 8
+// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK0-NEXT: store i8* null, i8** [[TMP27]], align 8
+// CHECK0-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK0-NEXT: store i32 2, i32* [[TMP30]], align 4
+// CHECK0-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK0-NEXT: store i32 3, i32* [[TMP31]], align 4
+// CHECK0-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK0-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8
+// CHECK0-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK0-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 8
+// CHECK0-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK0-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP34]], align 8
+// CHECK0-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK0-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP35]], align 8
+// CHECK0-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK0-NEXT: store i8** null, i8*** [[TMP36]], align 8
+// CHECK0-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK0-NEXT: store i8** null, i8*** [[TMP37]], align 8
+// CHECK0-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK0-NEXT: store i64 0, i64* [[TMP38]], align 8
+// CHECK0-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK0-NEXT: store i64 0, i64* [[TMP39]], align 8
+// CHECK0-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP40]], align 4
+// CHECK0-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP41]], align 4
+// CHECK0-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK0-NEXT: store i32 0, i32* [[TMP42]], align 4
+// CHECK0-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK0-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
+// CHECK0-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK0: omp_offload.failed:
+// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], i32* [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]]
+// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK0: omp_offload.cont:
+// CHECK0-NEXT: [[TMP45:%.*]] = load i16, i16* [[AA]], align 2
+// CHECK0-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
+// CHECK0-NEXT: store i16 [[TMP45]], i16* [[CONV3]], align 2
+// CHECK0-NEXT: [[TMP46:%.*]] = load i64, i64* [[AA_CASTED]], align 8
+// CHECK0-NEXT: [[TMP47:%.*]] = mul nuw i64 [[TMP1]], 4
+// CHECK0-NEXT: [[TMP48:%.*]] = mul nuw i64 5, [[TMP4]]
+// CHECK0-NEXT: [[TMP49:%.*]] = mul nuw i64 [[TMP48]], 8
+// CHECK0-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i64 72, i1 false)
+// CHECK0-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
+// CHECK0-NEXT: store i64 [[TMP46]], i64* [[TMP52]], align 8
+// CHECK0-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64*
+// CHECK0-NEXT: store i64 [[TMP46]], i64* [[TMP54]], align 8
+// CHECK0-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
+// CHECK0-NEXT: store i8* null, i8** [[TMP55]], align 8
+// CHECK0-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**
+// CHECK0-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 8
+// CHECK0-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**
+// CHECK0-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 8
+// CHECK0-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
+// CHECK0-NEXT: store i8* null, i8** [[TMP60]], align 8
+// CHECK0-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2
+// CHECK0-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
+// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP62]], align 8
+// CHECK0-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2
+// CHECK0-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
+// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP64]], align 8
+// CHECK0-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2
+// CHECK0-NEXT: store i8* null, i8** [[TMP65]], align 8
+// CHECK0-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3
+// CHECK0-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**
+// CHECK0-NEXT: store float* [[VLA]], float** [[TMP67]], align 8
+// CHECK0-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3
+// CHECK0-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**
+// CHECK0-NEXT: store float* [[VLA]], float** [[TMP69]], align 8
+// CHECK0-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
+// CHECK0-NEXT: store i64 [[TMP47]], i64* [[TMP70]], align 8
+// CHECK0-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 3
+// CHECK0-NEXT: store i8* null, i8** [[TMP71]], align 8
+// CHECK0-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 4
+// CHECK0-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**
+// CHECK0-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 8
+// CHECK0-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 4
+// CHECK0-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**
+// CHECK0-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 8
+// CHECK0-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 4
+// CHECK0-NEXT: store i8* null, i8** [[TMP76]], align 8
+// CHECK0-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 5
+// CHECK0-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
+// CHECK0-NEXT: store i64 5, i64* [[TMP78]], align 8
+// CHECK0-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 5
+// CHECK0-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*
+// CHECK0-NEXT: store i64 5, i64* [[TMP80]], align 8
+// CHECK0-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 5
+// CHECK0-NEXT: store i8* null, i8** [[TMP81]], align 8
+// CHECK0-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 6
+// CHECK0-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
+// CHECK0-NEXT: store i64 [[TMP4]], i64* [[TMP83]], align 8
+// CHECK0-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 6
+// CHECK0-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64*
+// CHECK0-NEXT: store i64 [[TMP4]], i64* [[TMP85]], align 8
+// CHECK0-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 6
+// CHECK0-NEXT: store i8* null, i8** [[TMP86]], align 8
+// CHECK0-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 7
+// CHECK0-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**
+// CHECK0-NEXT: store double* [[VLA1]], double** [[TMP88]], align 8
+// CHECK0-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 7
+// CHECK0-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**
+// CHECK0-NEXT: store double* [[VLA1]], double** [[TMP90]], align 8
+// CHECK0-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
+// CHECK0-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 8
+// CHECK0-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 7
+// CHECK0-NEXT: store i8* null, i8** [[TMP92]], align 8
+// CHECK0-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 8
+// CHECK0-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**
+// CHECK0-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 8
+// CHECK0-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 8
+// CHECK0-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**
+// CHECK0-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 8
+// CHECK0-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 8
+// CHECK0-NEXT: store i8* null, i8** [[TMP97]], align 8
+// CHECK0-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 0
+// CHECK0-NEXT: store i32 2, i32* [[TMP101]], align 4
+// CHECK0-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 1
+// CHECK0-NEXT: store i32 9, i32* [[TMP102]], align 4
+// CHECK0-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 2
+// CHECK0-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 8
+// CHECK0-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 3
+// CHECK0-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 8
+// CHECK0-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 4
+// CHECK0-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 8
+// CHECK0-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 5
+// CHECK0-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 8
+// CHECK0-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 6
+// CHECK0-NEXT: store i8** null, i8*** [[TMP107]], align 8
+// CHECK0-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 7
+// CHECK0-NEXT: store i8** null, i8*** [[TMP108]], align 8
+// CHECK0-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 8
+// CHECK0-NEXT: store i64 0, i64* [[TMP109]], align 8
+// CHECK0-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 9
+// CHECK0-NEXT: store i64 0, i64* [[TMP110]], align 8
+// CHECK0-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 10
+// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4
+// CHECK0-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 11
+// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4
+// CHECK0-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 12
+// CHECK0-NEXT: store i32 0, i32* [[TMP113]], align 4
+// CHECK0-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]])
+// CHECK0-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0
+// CHECK0-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
+// CHECK0: omp_offload.failed8:
+// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP46]], [10 x float]* [[B]], i64 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP4]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
+// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT9]]
+// CHECK0: omp_offload.cont9:
+// CHECK0-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK0-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**
+// CHECK0-NEXT: store double* [[TMP116]], double** [[TMP118]], align 8
+// CHECK0-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**
+// CHECK0-NEXT: store double* [[TMP116]], double** [[TMP120]], align 8
+// CHECK0-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
+// CHECK0-NEXT: store i8* null, i8** [[TMP121]], align 8
+// CHECK0-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**
+// CHECK0-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 8
+// CHECK0-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**
+// CHECK0-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 8
+// CHECK0-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
+// CHECK0-NEXT: store i8* null, i8** [[TMP126]], align 8
+// CHECK0-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0
+// CHECK0-NEXT: store i32 2, i32* [[TMP129]], align 4
+// CHECK0-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1
+// CHECK0-NEXT: store i32 2, i32* [[TMP130]], align 4
+// CHECK0-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2
+// CHECK0-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 8
+// CHECK0-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3
+// CHECK0-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 8
+// CHECK0-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4
+// CHECK0-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 8
+// CHECK0-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5
+// CHECK0-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 8
+// CHECK0-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6
+// CHECK0-NEXT: store i8** null, i8*** [[TMP135]], align 8
+// CHECK0-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7
+// CHECK0-NEXT: store i8** null, i8*** [[TMP136]], align 8
+// CHECK0-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8
+// CHECK0-NEXT: store i64 0, i64* [[TMP137]], align 8
+// CHECK0-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 9
+// CHECK0-NEXT: store i64 0, i64* [[TMP138]], align 8
+// CHECK0-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 10
+// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4
+// CHECK0-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 11
+// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4
+// CHECK0-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 12
+// CHECK0-NEXT: store i32 0, i32* [[TMP141]], align 4
+// CHECK0-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]])
+// CHECK0-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0
+// CHECK0-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
+// CHECK0: omp_offload.failed14:
+// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]
+// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT15]]
+// CHECK0: omp_offload.cont15:
+// CHECK0-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK0-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])
+// CHECK0-NEXT: ret i32 [[TMP144]]
+//
+//
+// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// CHECK0-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8
+// CHECK0-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK0-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8
+// CHECK0-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8
+// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK0-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*
+// CHECK0-NEXT: ret void
+//
+//
+// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// CHECK0-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
+// CHECK0-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
+// CHECK0-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
+// CHECK0-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
+// CHECK0-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
+// CHECK0-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// CHECK0-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
+// CHECK0-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
+// CHECK0-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// CHECK0-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
+// CHECK0-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
+// CHECK0-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// CHECK0-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
+// CHECK0-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
+// CHECK0-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
+// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
+// CHECK0-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
+// CHECK0-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// CHECK0-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
+// CHECK0-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
+// CHECK0-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// CHECK0-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
+// CHECK0-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
+// CHECK0-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
+// CHECK0-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// CHECK0-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)
+// CHECK0-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// CHECK0-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8
+// CHECK0-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
+// CHECK0-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK0-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4
+// CHECK0-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// CHECK0-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)
+// CHECK0-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// CHECK0-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)
+// CHECK0-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// CHECK0-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8
+// CHECK0-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// CHECK0-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8
+// CHECK0-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// CHECK0-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8
+// CHECK0-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// CHECK0-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)
+// CHECK0-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// CHECK0-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)
+// CHECK0-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// CHECK0-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// CHECK0-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK0-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2
+// CHECK0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// CHECK0-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3
+// CHECK0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// CHECK0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1
+// CHECK0-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2
+// CHECK0-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// CHECK0-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]
+// CHECK0-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]
+// CHECK0-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
+// CHECK0-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// CHECK0-NEXT: store i64 1, i64* [[X]], align 8
+// CHECK0-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// CHECK0-NEXT: store i8 1, i8* [[Y]], align 8
+// CHECK0-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK0-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// CHECK0-NEXT: ret void
+//
+//
+// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// CHECK0-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK0-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8
+// CHECK0-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK0-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK0-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8
+// CHECK0-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8
+// CHECK0-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*
+// CHECK0-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*
+// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 8, i1 false)
+// CHECK0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double
+// CHECK0-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i64 0
+// CHECK0-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8
+// CHECK0-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 0
+// CHECK0-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 8
+// CHECK0-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// CHECK0-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 8
+// CHECK0-NEXT: ret void
+//
+//
+// CHECK0-LABEL: define {{[^@]+}}@_Z3bariPd
+// CHECK0-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK0-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK0-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK0-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
+// CHECK0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK0-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK0-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])
+// CHECK0-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// CHECK0-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// CHECK0-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])
+// CHECK0-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// CHECK0-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// CHECK0-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])
+// CHECK0-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// CHECK0-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// CHECK0-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])
+// CHECK0-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// CHECK0-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// CHECK0-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-NEXT: ret i32 [[TMP9]]
+//
+//
+// CHECK0-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// CHECK0-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK0-NEXT: [[B:%.*]] = alloca i32, align 4
+// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
+// CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK0-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// CHECK0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// CHECK0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// CHECK0-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// CHECK0-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+// CHECK0-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
+// CHECK0-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
+// CHECK0-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
+// CHECK0-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
+// CHECK0-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
+// CHECK0-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
+// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
+// CHECK0-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
+// CHECK0-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
+// CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]]
+// CHECK0-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 2
+// CHECK0-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP9]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i64 40, i1 false)
+// CHECK0-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
+// CHECK0-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
+// CHECK0-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
+// CHECK0-NEXT: store double* [[A]], double** [[TMP13]], align 8
+// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK0-NEXT: store i8* null, i8** [[TMP14]], align 8
+// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
+// CHECK0-NEXT: store i64 [[TMP6]], i64* [[TMP16]], align 8
+// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
+// CHECK0-NEXT: store i64 [[TMP6]], i64* [[TMP18]], align 8
+// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK0-NEXT: store i8* null, i8** [[TMP19]], align 8
+// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK0-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
+// CHECK0-NEXT: store i64 2, i64* [[TMP21]], align 8
+// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK0-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
+// CHECK0-NEXT: store i64 2, i64* [[TMP23]], align 8
+// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK0-NEXT: store i8* null, i8** [[TMP24]], align 8
+// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK0-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
+// CHECK0-NEXT: store i64 [[TMP2]], i64* [[TMP26]], align 8
+// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK0-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
+// CHECK0-NEXT: store i64 [[TMP2]], i64* [[TMP28]], align 8
+// CHECK0-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
+// CHECK0-NEXT: store i8* null, i8** [[TMP29]], align 8
+// CHECK0-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
+// CHECK0-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**
+// CHECK0-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 8
+// CHECK0-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
+// CHECK0-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**
+// CHECK0-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 8
+// CHECK0-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
+// CHECK0-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 8
+// CHECK0-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
+// CHECK0-NEXT: store i8* null, i8** [[TMP35]], align 8
+// CHECK0-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK0-NEXT: store i32 2, i32* [[TMP39]], align 4
+// CHECK0-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK0-NEXT: store i32 5, i32* [[TMP40]], align 4
+// CHECK0-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK0-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 8
+// CHECK0-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK0-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8
+// CHECK0-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK0-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 8
+// CHECK0-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK0-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 8
+// CHECK0-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK0-NEXT: store i8** null, i8*** [[TMP45]], align 8
+// CHECK0-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK0-NEXT: store i8** null, i8*** [[TMP46]], align 8
+// CHECK0-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK0-NEXT: store i64 0, i64* [[TMP47]], align 8
+// CHECK0-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK0-NEXT: store i64 0, i64* [[TMP48]], align 8
+// CHECK0-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4
+// CHECK0-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4
+// CHECK0-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK0-NEXT: store i32 0, i32* [[TMP51]], align 4
+// CHECK0-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK0-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0
+// CHECK0-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK0: omp_offload.failed:
+// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
+// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK0: omp_offload.cont:
+// CHECK0-NEXT: [[TMP54:%.*]] = mul nsw i64 1, [[TMP2]]
+// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP54]]
+// CHECK0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// CHECK0-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
+// CHECK0-NEXT: [[CONV3:%.*]] = sext i16 [[TMP55]] to i32
+// CHECK0-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4
+// CHECK0-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP56]]
+// CHECK0-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK0-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])
+// CHECK0-NEXT: ret i32 [[ADD4]]
+//
+//
+// CHECK0-LABEL: define {{[^@]+}}@_ZL7fstatici
+// CHECK0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK0-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK0-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// CHECK0-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK0-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
+// CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK0-NEXT: store i8 0, i8* [[AAA]], align 1
+// CHECK0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK0-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
+// CHECK0-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK0-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
+// CHECK0-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
+// CHECK0-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
+// CHECK0-NEXT: [[TMP3:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
+// CHECK0-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
+// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
+// CHECK0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
+// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
+// CHECK0-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK0-NEXT: store i8* null, i8** [[TMP8]], align 8
+// CHECK0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
+// CHECK0-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
+// CHECK0-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
+// CHECK0-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
+// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK0-NEXT: store i8* null, i8** [[TMP13]], align 8
+// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK0-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**
+// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 8
+// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK0-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**
+// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 8
+// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK0-NEXT: store i8* null, i8** [[TMP18]], align 8
+// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK0-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK0-NEXT: store i32 3, i32* [[TMP22]], align 4
+// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK0-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 8
+// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK0-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8
+// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK0-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 8
+// CHECK0-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK0-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 8
+// CHECK0-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK0-NEXT: store i8** null, i8*** [[TMP27]], align 8
+// CHECK0-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK0-NEXT: store i8** null, i8*** [[TMP28]], align 8
+// CHECK0-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK0-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK0-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK0-NEXT: store i64 0, i64* [[TMP30]], align 8
+// CHECK0-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4
+// CHECK0-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4
+// CHECK0-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK0-NEXT: store i32 0, i32* [[TMP33]], align 4
+// CHECK0-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK0-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
+// CHECK0-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK0: omp_offload.failed:
+// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK0: omp_offload.cont:
+// CHECK0-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-NEXT: ret i32 [[TMP36]]
+//
+//
+// CHECK0-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// CHECK0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK0-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK0-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK0-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
+// CHECK0-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK0-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK0-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
+// CHECK0-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK0-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
+// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
+// CHECK0-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
+// CHECK0-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
+// CHECK0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK0-NEXT: store i8* null, i8** [[TMP6]], align 8
+// CHECK0-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**
+// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 8
+// CHECK0-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK0-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
+// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 8
+// CHECK0-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK0-NEXT: store i8* null, i8** [[TMP11]], align 8
+// CHECK0-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK0-NEXT: store i32 2, i32* [[TMP14]], align 4
+// CHECK0-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK0-NEXT: store i32 2, i32* [[TMP15]], align 4
+// CHECK0-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK0-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 8
+// CHECK0-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK0-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 8
+// CHECK0-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK0-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 8
+// CHECK0-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK0-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 8
+// CHECK0-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK0-NEXT: store i8** null, i8*** [[TMP20]], align 8
+// CHECK0-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK0-NEXT: store i8** null, i8*** [[TMP21]], align 8
+// CHECK0-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK0-NEXT: store i64 0, i64* [[TMP22]], align 8
+// CHECK0-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK0-NEXT: store i64 0, i64* [[TMP23]], align 8
+// CHECK0-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK0-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4
+// CHECK0-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK0-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4
+// CHECK0-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK0-NEXT: store i32 0, i32* [[TMP26]], align 4
+// CHECK0-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK0-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
+// CHECK0-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK0: omp_offload.failed:
+// CHECK0-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK0-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK0: omp_offload.cont:
+// CHECK0-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4
+// CHECK0-NEXT: ret i32 [[TMP29]]
+//
+//
+// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// CHECK0-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
+// CHECK0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// CHECK0-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
+// CHECK0-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// CHECK0-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// CHECK0-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
+// CHECK0-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
+// CHECK0-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// CHECK0-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// CHECK0-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
+// CHECK0-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// CHECK0-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
+// CHECK0-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// CHECK0-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
+// CHECK0-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK0-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8
+// CHECK0-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// CHECK0-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
+// CHECK0-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// CHECK0-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)
+// CHECK0-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK0-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double
+// CHECK0-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
+// CHECK0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK0-NEXT: store double [[ADD]], double* [[A]], align 8
+// CHECK0-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK0-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8
+// CHECK0-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// CHECK0-NEXT: store double [[INC]], double* [[A5]], align 8
+// CHECK0-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
+// CHECK0-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]
+// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]
+// CHECK0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// CHECK0-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
+// CHECK0-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK0-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// CHECK0-NEXT: ret void
+//
+//
+// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// CHECK0-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// CHECK0-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
+// CHECK0-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK0-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
+// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK0-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
+// CHECK0-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// CHECK0-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*
+// CHECK0-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// CHECK0-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK0-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK0-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
+// CHECK0-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32
+// CHECK0-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
+// CHECK0-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
+// CHECK0-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1
+// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2
+// CHECK0-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1
+// CHECK0-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
+// CHECK0-NEXT: ret void
+//
+//
+// CHECK0-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// CHECK0-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK0-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// CHECK0-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK0-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK0-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// CHECK0-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK0-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// CHECK0-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK0-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// CHECK0-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK0-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2
+// CHECK0-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK0-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK0-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// CHECK0-NEXT: ret void
+//
+//
+// CHECK0-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CHECK0-SAME: () #[[ATTR5:[0-9]+]] {
+// CHECK0-NEXT: entry:
+// CHECK0-NEXT: call void @__tgt_register_requires(i64 1)
+// CHECK0-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@_Z3fooiPd
+// CHECK1-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
+// CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// CHECK1-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK1-NEXT: [[P:%.*]] = alloca i32*, align 64
+// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[GA_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [9 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [9 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [9 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
+// CHECK1-NEXT: [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK1-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// CHECK1-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
+// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
+// CHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
+// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
+// CHECK1-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP6]], i32* [[X]], align 4
+// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4
+// CHECK1-NEXT: store i32* [[A]], i32** [[P]], align 64
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[P]], align 64
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* @ga, align 4
+// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[GA_CASTED]] to i32*
+// CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4
+// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[GA_CASTED]], align 8
+// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64*
+// CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP14]], align 8
+// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
+// CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP16]], align 8
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK1-NEXT: store i8* null, i8** [[TMP17]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
+// CHECK1-NEXT: store i32* [[TMP10]], i32** [[TMP19]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32**
+// CHECK1-NEXT: store i32* [[TMP10]], i32** [[TMP21]], align 8
+// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK1-NEXT: store i8* null, i8** [[TMP22]], align 8
+// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
+// CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP24]], align 8
+// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
+// CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP26]], align 8
+// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK1-NEXT: store i8* null, i8** [[TMP27]], align 8
+// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK1-NEXT: store i32 2, i32* [[TMP30]], align 4
+// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK1-NEXT: store i32 3, i32* [[TMP31]], align 4
+// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK1-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8
+// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK1-NEXT: store i8** [[TMP29]], i8*** [[TMP33]], align 8
+// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP34]], align 8
+// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP35]], align 8
+// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK1-NEXT: store i8** null, i8*** [[TMP36]], align 8
+// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK1-NEXT: store i8** null, i8*** [[TMP37]], align 8
+// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK1-NEXT: store i64 0, i64* [[TMP38]], align 8
+// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK1-NEXT: store i64 0, i64* [[TMP39]], align 8
+// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP40]], align 4
+// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP41]], align 4
+// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK1-NEXT: store i32 0, i32* [[TMP42]], align 4
+// CHECK1-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK1-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
+// CHECK1-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK1: omp_offload.failed:
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i64 [[TMP9]], i32* [[TMP10]], i64 [[TMP12]]) #[[ATTR3:[0-9]+]]
+// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK1: omp_offload.cont:
+// CHECK1-NEXT: [[TMP45:%.*]] = load i16, i16* [[AA]], align 2
+// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
+// CHECK1-NEXT: store i16 [[TMP45]], i16* [[CONV3]], align 2
+// CHECK1-NEXT: [[TMP46:%.*]] = load i64, i64* [[AA_CASTED]], align 8
+// CHECK1-NEXT: [[TMP47:%.*]] = mul nuw i64 [[TMP1]], 4
+// CHECK1-NEXT: [[TMP48:%.*]] = mul nuw i64 5, [[TMP4]]
+// CHECK1-NEXT: [[TMP49:%.*]] = mul nuw i64 [[TMP48]], 8
+// CHECK1-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i64 72, i1 false)
+// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
+// CHECK1-NEXT: store i64 [[TMP46]], i64* [[TMP52]], align 8
+// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i64*
+// CHECK1-NEXT: store i64 [[TMP46]], i64* [[TMP54]], align 8
+// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
+// CHECK1-NEXT: store i8* null, i8** [[TMP55]], align 8
+// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**
+// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 8
+// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**
+// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 8
+// CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
+// CHECK1-NEXT: store i8* null, i8** [[TMP60]], align 8
+// CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 2
+// CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
+// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP62]], align 8
+// CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 2
+// CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
+// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP64]], align 8
+// CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 2
+// CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8
+// CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 3
+// CHECK1-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**
+// CHECK1-NEXT: store float* [[VLA]], float** [[TMP67]], align 8
+// CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 3
+// CHECK1-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**
+// CHECK1-NEXT: store float* [[VLA]], float** [[TMP69]], align 8
+// CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
+// CHECK1-NEXT: store i64 [[TMP47]], i64* [[TMP70]], align 8
+// CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 3
+// CHECK1-NEXT: store i8* null, i8** [[TMP71]], align 8
+// CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 4
+// CHECK1-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**
+// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 8
+// CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 4
+// CHECK1-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**
+// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 8
+// CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 4
+// CHECK1-NEXT: store i8* null, i8** [[TMP76]], align 8
+// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 5
+// CHECK1-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64*
+// CHECK1-NEXT: store i64 5, i64* [[TMP78]], align 8
+// CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 5
+// CHECK1-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*
+// CHECK1-NEXT: store i64 5, i64* [[TMP80]], align 8
+// CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 5
+// CHECK1-NEXT: store i8* null, i8** [[TMP81]], align 8
+// CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 6
+// CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64*
+// CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP83]], align 8
+// CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 6
+// CHECK1-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64*
+// CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP85]], align 8
+// CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 6
+// CHECK1-NEXT: store i8* null, i8** [[TMP86]], align 8
+// CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 7
+// CHECK1-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**
+// CHECK1-NEXT: store double* [[VLA1]], double** [[TMP88]], align 8
+// CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 7
+// CHECK1-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**
+// CHECK1-NEXT: store double* [[VLA1]], double** [[TMP90]], align 8
+// CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
+// CHECK1-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 8
+// CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 7
+// CHECK1-NEXT: store i8* null, i8** [[TMP92]], align 8
+// CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 8
+// CHECK1-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**
+// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 8
+// CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 8
+// CHECK1-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**
+// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 8
+// CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 8
+// CHECK1-NEXT: store i8* null, i8** [[TMP97]], align 8
+// CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 0
+// CHECK1-NEXT: store i32 2, i32* [[TMP101]], align 4
+// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 1
+// CHECK1-NEXT: store i32 9, i32* [[TMP102]], align 4
+// CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 2
+// CHECK1-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 8
+// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 3
+// CHECK1-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 8
+// CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 4
+// CHECK1-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 8
+// CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 5
+// CHECK1-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 8
+// CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 6
+// CHECK1-NEXT: store i8** null, i8*** [[TMP107]], align 8
+// CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 7
+// CHECK1-NEXT: store i8** null, i8*** [[TMP108]], align 8
+// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 8
+// CHECK1-NEXT: store i64 0, i64* [[TMP109]], align 8
+// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 9
+// CHECK1-NEXT: store i64 0, i64* [[TMP110]], align 8
+// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 10
+// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4
+// CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 11
+// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4
+// CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]], i32 0, i32 12
+// CHECK1-NEXT: store i32 0, i32* [[TMP113]], align 4
+// CHECK1-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS7]])
+// CHECK1-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0
+// CHECK1-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
+// CHECK1: omp_offload.failed8:
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i64 [[TMP46]], [10 x float]* [[B]], i64 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP4]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
+// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT9]]
+// CHECK1: omp_offload.cont9:
+// CHECK1-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**
+// CHECK1-NEXT: store double* [[TMP116]], double** [[TMP118]], align 8
+// CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**
+// CHECK1-NEXT: store double* [[TMP116]], double** [[TMP120]], align 8
+// CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
+// CHECK1-NEXT: store i8* null, i8** [[TMP121]], align 8
+// CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**
+// CHECK1-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 8
+// CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**
+// CHECK1-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 8
+// CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
+// CHECK1-NEXT: store i8* null, i8** [[TMP126]], align 8
+// CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0
+// CHECK1-NEXT: store i32 2, i32* [[TMP129]], align 4
+// CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1
+// CHECK1-NEXT: store i32 2, i32* [[TMP130]], align 4
+// CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2
+// CHECK1-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 8
+// CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3
+// CHECK1-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 8
+// CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4
+// CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 8
+// CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5
+// CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 8
+// CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6
+// CHECK1-NEXT: store i8** null, i8*** [[TMP135]], align 8
+// CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7
+// CHECK1-NEXT: store i8** null, i8*** [[TMP136]], align 8
+// CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8
+// CHECK1-NEXT: store i64 0, i64* [[TMP137]], align 8
+// CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 9
+// CHECK1-NEXT: store i64 0, i64* [[TMP138]], align 8
+// CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 10
+// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4
+// CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 11
+// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4
+// CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 12
+// CHECK1-NEXT: store i32 0, i32* [[TMP141]], align 4
+// CHECK1-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]])
+// CHECK1-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0
+// CHECK1-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
+// CHECK1: omp_offload.failed14:
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]
+// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT15]]
+// CHECK1: omp_offload.cont15:
+// CHECK1-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])
+// CHECK1-NEXT: ret i32 [[TMP144]]
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// CHECK1-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8
+// CHECK1-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK1-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8
+// CHECK1-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8
+// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// CHECK1-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
+// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
+// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
+// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
+// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
+// CHECK1-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
+// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
+// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
+// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
+// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
+// CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
+// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
+// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
+// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
+// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// CHECK1-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)
+// CHECK1-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// CHECK1-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8
+// CHECK1-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
+// CHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4
+// CHECK1-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// CHECK1-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)
+// CHECK1-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// CHECK1-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)
+// CHECK1-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// CHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8
+// CHECK1-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8
+// CHECK1-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// CHECK1-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8
+// CHECK1-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// CHECK1-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)
+// CHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// CHECK1-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)
+// CHECK1-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// CHECK1-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK1-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2
+// CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3
+// CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1
+// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2
+// CHECK1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// CHECK1-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]
+// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]
+// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
+// CHECK1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// CHECK1-NEXT: store i64 1, i64* [[X]], align 8
+// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// CHECK1-NEXT: store i8 1, i8* [[Y]], align 8
+// CHECK1-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// CHECK1-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK1-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8
+// CHECK1-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK1-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*
+// CHECK1-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*
+// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 8, i1 false)
+// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double
+// CHECK1-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i64 0
+// CHECK1-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i64 0
+// CHECK1-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 8
+// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// CHECK1-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 8
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@_Z3bariPd
+// CHECK1-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
+// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-NEXT: ret i32 [[TMP9]]
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
+// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+// CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
+// CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
+// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
+// CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
+// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
+// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
+// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 2, [[TMP2]]
+// CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 2
+// CHECK1-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP9]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i64 40, i1 false)
+// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
+// CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
+// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
+// CHECK1-NEXT: store double* [[A]], double** [[TMP13]], align 8
+// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8
+// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
+// CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP16]], align 8
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
+// CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP18]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
+// CHECK1-NEXT: store i64 2, i64* [[TMP21]], align 8
+// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
+// CHECK1-NEXT: store i64 2, i64* [[TMP23]], align 8
+// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8
+// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64*
+// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP26]], align 8
+// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64*
+// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP28]], align 8
+// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
+// CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8
+// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
+// CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**
+// CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 8
+// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
+// CHECK1-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**
+// CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 8
+// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
+// CHECK1-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 8
+// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
+// CHECK1-NEXT: store i8* null, i8** [[TMP35]], align 8
+// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK1-NEXT: store i32 2, i32* [[TMP39]], align 4
+// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK1-NEXT: store i32 5, i32* [[TMP40]], align 4
+// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK1-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 8
+// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK1-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8
+// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK1-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 8
+// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK1-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 8
+// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK1-NEXT: store i8** null, i8*** [[TMP45]], align 8
+// CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK1-NEXT: store i8** null, i8*** [[TMP46]], align 8
+// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK1-NEXT: store i64 0, i64* [[TMP47]], align 8
+// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK1-NEXT: store i64 0, i64* [[TMP48]], align 8
+// CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4
+// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4
+// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK1-NEXT: store i32 0, i32* [[TMP51]], align 4
+// CHECK1-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK1-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0
+// CHECK1-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK1: omp_offload.failed:
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
+// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK1: omp_offload.cont:
+// CHECK1-NEXT: [[TMP54:%.*]] = mul nsw i64 1, [[TMP2]]
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP54]]
+// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// CHECK1-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
+// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP55]] to i32
+// CHECK1-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4
+// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP56]]
+// CHECK1-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])
+// CHECK1-NEXT: ret i32 [[ADD4]]
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
+// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
+// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
+// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
+// CHECK1-NEXT: store i8 [[TMP2]], i8* [[CONV1]], align 1
+// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
+// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
+// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
+// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP7]], align 8
+// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
+// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64*
+// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8
+// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8
+// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**
+// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 8
+// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**
+// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK1-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK1-NEXT: store i32 3, i32* [[TMP22]], align 4
+// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK1-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 8
+// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK1-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8
+// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 8
+// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 8
+// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK1-NEXT: store i8** null, i8*** [[TMP27]], align 8
+// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK1-NEXT: store i8** null, i8*** [[TMP28]], align 8
+// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK1-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK1-NEXT: store i64 0, i64* [[TMP30]], align 8
+// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4
+// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4
+// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK1-NEXT: store i32 0, i32* [[TMP33]], align 4
+// CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
+// CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK1: omp_offload.failed:
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK1: omp_offload.cont:
+// CHECK1-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-NEXT: ret i32 [[TMP36]]
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 8
+// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
+// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
+// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
+// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8
+// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**
+// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
+// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8
+// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK1-NEXT: store i32 2, i32* [[TMP14]], align 4
+// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK1-NEXT: store i32 2, i32* [[TMP15]], align 4
+// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK1-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 8
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK1-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK1-NEXT: store i8** null, i8*** [[TMP20]], align 8
+// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK1-NEXT: store i8** null, i8*** [[TMP21]], align 8
+// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK1-NEXT: store i64 0, i64* [[TMP22]], align 8
+// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK1-NEXT: store i64 0, i64* [[TMP23]], align 8
+// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK1-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4
+// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK1-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4
+// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK1-NEXT: store i32 0, i32* [[TMP26]], align 4
+// CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
+// CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK1: omp_offload.failed:
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i64 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK1: omp_offload.cont:
+// CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4
+// CHECK1-NEXT: ret i32 [[TMP29]]
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
+// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
+// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
+// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// CHECK1-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
+// CHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// CHECK1-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
+// CHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8
+// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// CHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
+// CHECK1-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// CHECK1-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double
+// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
+// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
+// CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8
+// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8
+// CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
+// CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]
+// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// CHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
+// CHECK1-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// CHECK1-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
+// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
+// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
+// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*
+// CHECK1-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
+// CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32
+// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
+// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
+// CHECK1-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1
+// CHECK1-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// CHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK1-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK1-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CHECK1-SAME: () #[[ATTR5:[0-9]+]] {
+// CHECK1-NEXT: entry:
+// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@_Z3fooiPd
+// CHECK2-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2
+// CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// CHECK2-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK2-NEXT: [[P:%.*]] = alloca i32*, align 64
+// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
+// CHECK2-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK2-NEXT: store i16 0, i16* [[AA]], align 2
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
+// CHECK2-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
+// CHECK2-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
+// CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
+// CHECK2-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP4]], i32* [[X]], align 4
+// CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4
+// CHECK2-NEXT: store i32* [[A]], i32** [[P]], align 64
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[P]], align 64
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* @ga, align 4
+// CHECK2-NEXT: store i32 [[TMP9]], i32* [[GA_CASTED]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[GA_CASTED]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
+// CHECK2-NEXT: store i32 [[TMP7]], i32* [[TMP12]], align 4
+// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
+// CHECK2-NEXT: store i32 [[TMP7]], i32* [[TMP14]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 4
+// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32**
+// CHECK2-NEXT: store i32* [[TMP8]], i32** [[TMP17]], align 4
+// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
+// CHECK2-NEXT: store i32* [[TMP8]], i32** [[TMP19]], align 4
+// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 4
+// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
+// CHECK2-NEXT: store i32 [[TMP10]], i32* [[TMP22]], align 4
+// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK2-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
+// CHECK2-NEXT: store i32 [[TMP10]], i32* [[TMP24]], align 4
+// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK2-NEXT: store i8* null, i8** [[TMP25]], align 4
+// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK2-NEXT: store i32 2, i32* [[TMP28]], align 4
+// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK2-NEXT: store i32 3, i32* [[TMP29]], align 4
+// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK2-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 4
+// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK2-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4
+// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK2-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP32]], align 4
+// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK2-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP33]], align 4
+// CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK2-NEXT: store i8** null, i8*** [[TMP34]], align 4
+// CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK2-NEXT: store i8** null, i8*** [[TMP35]], align 4
+// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK2-NEXT: store i64 0, i64* [[TMP36]], align 8
+// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK2-NEXT: store i64 0, i64* [[TMP37]], align 8
+// CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP38]], align 4
+// CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP39]], align 4
+// CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK2-NEXT: store i32 0, i32* [[TMP40]], align 4
+// CHECK2-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK2-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0
+// CHECK2-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK2: omp_offload.failed:
+// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], i32* [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]]
+// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK2: omp_offload.cont:
+// CHECK2-NEXT: [[TMP43:%.*]] = load i16, i16* [[AA]], align 2
+// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
+// CHECK2-NEXT: store i16 [[TMP43]], i16* [[CONV]], align 2
+// CHECK2-NEXT: [[TMP44:%.*]] = load i32, i32* [[AA_CASTED]], align 4
+// CHECK2-NEXT: [[TMP45:%.*]] = mul nuw i32 [[TMP0]], 4
+// CHECK2-NEXT: [[TMP46:%.*]] = sext i32 [[TMP45]] to i64
+// CHECK2-NEXT: [[TMP47:%.*]] = mul nuw i32 5, [[TMP2]]
+// CHECK2-NEXT: [[TMP48:%.*]] = mul nuw i32 [[TMP47]], 8
+// CHECK2-NEXT: [[TMP49:%.*]] = sext i32 [[TMP48]] to i64
+// CHECK2-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i32 72, i1 false)
+// CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
+// CHECK2-NEXT: store i32 [[TMP44]], i32* [[TMP52]], align 4
+// CHECK2-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32*
+// CHECK2-NEXT: store i32 [[TMP44]], i32* [[TMP54]], align 4
+// CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
+// CHECK2-NEXT: store i8* null, i8** [[TMP55]], align 4
+// CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**
+// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 4
+// CHECK2-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**
+// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 4
+// CHECK2-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
+// CHECK2-NEXT: store i8* null, i8** [[TMP60]], align 4
+// CHECK2-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2
+// CHECK2-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
+// CHECK2-NEXT: store i32 [[TMP0]], i32* [[TMP62]], align 4
+// CHECK2-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2
+// CHECK2-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*
+// CHECK2-NEXT: store i32 [[TMP0]], i32* [[TMP64]], align 4
+// CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2
+// CHECK2-NEXT: store i8* null, i8** [[TMP65]], align 4
+// CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 3
+// CHECK2-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**
+// CHECK2-NEXT: store float* [[VLA]], float** [[TMP67]], align 4
+// CHECK2-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 3
+// CHECK2-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**
+// CHECK2-NEXT: store float* [[VLA]], float** [[TMP69]], align 4
+// CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
+// CHECK2-NEXT: store i64 [[TMP46]], i64* [[TMP70]], align 4
+// CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 3
+// CHECK2-NEXT: store i8* null, i8** [[TMP71]], align 4
+// CHECK2-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 4
+// CHECK2-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**
+// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 4
+// CHECK2-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 4
+// CHECK2-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**
+// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 4
+// CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 4
+// CHECK2-NEXT: store i8* null, i8** [[TMP76]], align 4
+// CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 5
+// CHECK2-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32*
+// CHECK2-NEXT: store i32 5, i32* [[TMP78]], align 4
+// CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 5
+// CHECK2-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*
+// CHECK2-NEXT: store i32 5, i32* [[TMP80]], align 4
+// CHECK2-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 5
+// CHECK2-NEXT: store i8* null, i8** [[TMP81]], align 4
+// CHECK2-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 6
+// CHECK2-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32*
+// CHECK2-NEXT: store i32 [[TMP2]], i32* [[TMP83]], align 4
+// CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 6
+// CHECK2-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32*
+// CHECK2-NEXT: store i32 [[TMP2]], i32* [[TMP85]], align 4
+// CHECK2-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 6
+// CHECK2-NEXT: store i8* null, i8** [[TMP86]], align 4
+// CHECK2-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 7
+// CHECK2-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**
+// CHECK2-NEXT: store double* [[VLA1]], double** [[TMP88]], align 4
+// CHECK2-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 7
+// CHECK2-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**
+// CHECK2-NEXT: store double* [[VLA1]], double** [[TMP90]], align 4
+// CHECK2-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
+// CHECK2-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 4
+// CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 7
+// CHECK2-NEXT: store i8* null, i8** [[TMP92]], align 4
+// CHECK2-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 8
+// CHECK2-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**
+// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 4
+// CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 8
+// CHECK2-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**
+// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 4
+// CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 8
+// CHECK2-NEXT: store i8* null, i8** [[TMP97]], align 4
+// CHECK2-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 0
+// CHECK2-NEXT: store i32 2, i32* [[TMP101]], align 4
+// CHECK2-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 1
+// CHECK2-NEXT: store i32 9, i32* [[TMP102]], align 4
+// CHECK2-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 2
+// CHECK2-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 4
+// CHECK2-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 3
+// CHECK2-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 4
+// CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 4
+// CHECK2-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 4
+// CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 5
+// CHECK2-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 4
+// CHECK2-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 6
+// CHECK2-NEXT: store i8** null, i8*** [[TMP107]], align 4
+// CHECK2-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 7
+// CHECK2-NEXT: store i8** null, i8*** [[TMP108]], align 4
+// CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 8
+// CHECK2-NEXT: store i64 0, i64* [[TMP109]], align 8
+// CHECK2-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 9
+// CHECK2-NEXT: store i64 0, i64* [[TMP110]], align 8
+// CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 10
+// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4
+// CHECK2-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 11
+// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4
+// CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 12
+// CHECK2-NEXT: store i32 0, i32* [[TMP113]], align 4
+// CHECK2-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]])
+// CHECK2-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0
+// CHECK2-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CHECK2: omp_offload.failed6:
+// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP44]], [10 x float]* [[B]], i32 [[TMP0]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP2]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
+// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CHECK2: omp_offload.cont7:
+// CHECK2-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK2-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**
+// CHECK2-NEXT: store double* [[TMP116]], double** [[TMP118]], align 4
+// CHECK2-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**
+// CHECK2-NEXT: store double* [[TMP116]], double** [[TMP120]], align 4
+// CHECK2-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0
+// CHECK2-NEXT: store i8* null, i8** [[TMP121]], align 4
+// CHECK2-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**
+// CHECK2-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 4
+// CHECK2-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**
+// CHECK2-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 4
+// CHECK2-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1
+// CHECK2-NEXT: store i8* null, i8** [[TMP126]], align 4
+// CHECK2-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 0
+// CHECK2-NEXT: store i32 2, i32* [[TMP129]], align 4
+// CHECK2-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 1
+// CHECK2-NEXT: store i32 2, i32* [[TMP130]], align 4
+// CHECK2-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 2
+// CHECK2-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 4
+// CHECK2-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 3
+// CHECK2-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 4
+// CHECK2-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 4
+// CHECK2-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 4
+// CHECK2-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 5
+// CHECK2-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 4
+// CHECK2-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 6
+// CHECK2-NEXT: store i8** null, i8*** [[TMP135]], align 4
+// CHECK2-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 7
+// CHECK2-NEXT: store i8** null, i8*** [[TMP136]], align 4
+// CHECK2-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 8
+// CHECK2-NEXT: store i64 0, i64* [[TMP137]], align 8
+// CHECK2-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 9
+// CHECK2-NEXT: store i64 0, i64* [[TMP138]], align 8
+// CHECK2-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 10
+// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4
+// CHECK2-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 11
+// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4
+// CHECK2-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 12
+// CHECK2-NEXT: store i32 0, i32* [[TMP141]], align 4
+// CHECK2-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]])
+// CHECK2-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0
+// CHECK2-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]
+// CHECK2: omp_offload.failed12:
+// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]
+// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT13]]
+// CHECK2: omp_offload.cont13:
+// CHECK2-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])
+// CHECK2-NEXT: ret i32 [[TMP144]]
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// CHECK2-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4
+// CHECK2-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK2-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// CHECK2-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
+// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
+// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
+// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
+// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
+// CHECK2-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// CHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
+// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
+// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// CHECK2-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
+// CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
+// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
+// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
+// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// CHECK2-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)
+// CHECK2-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// CHECK2-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4
+// CHECK2-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
+// CHECK2-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4
+// CHECK2-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// CHECK2-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)
+// CHECK2-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// CHECK2-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)
+// CHECK2-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// CHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8
+// CHECK2-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4
+// CHECK2-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4
+// CHECK2-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// CHECK2-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
+// CHECK2-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// CHECK2-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)
+// CHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// CHECK2-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)
+// CHECK2-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// CHECK2-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// CHECK2-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK2-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2
+// CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3
+// CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1
+// CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
+// CHECK2-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// CHECK2-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]
+// CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]
+// CHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3
+// CHECK2-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// CHECK2-NEXT: store i64 1, i64* [[X]], align 4
+// CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// CHECK2-NEXT: store i8 1, i8* [[Y]], align 4
+// CHECK2-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// CHECK2-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK2-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4
+// CHECK2-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK2-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK2-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*
+// CHECK2-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*
+// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 8, i1 false)
+// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double
+// CHECK2-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i32 0
+// CHECK2-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 0
+// CHECK2-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// CHECK2-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 4
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@_Z3bariPd
+// CHECK2-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
+// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-NEXT: ret i32 [[TMP9]]
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// CHECK2-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
+// CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// CHECK2-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
+// CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
+// CHECK2-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
+// CHECK2-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
+// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]]
+// CHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// CHECK2-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i64
+// CHECK2-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i32 40, i1 false)
+// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
+// CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
+// CHECK2-NEXT: store double* [[A]], double** [[TMP13]], align 4
+// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
+// CHECK2-NEXT: store i32 [[TMP5]], i32* [[TMP16]], align 4
+// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
+// CHECK2-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
+// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 4
+// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK2-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
+// CHECK2-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
+// CHECK2-NEXT: store i32 2, i32* [[TMP23]], align 4
+// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK2-NEXT: store i8* null, i8** [[TMP24]], align 4
+// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK2-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
+// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP26]], align 4
+// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK2-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
+// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4
+// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
+// CHECK2-NEXT: store i8* null, i8** [[TMP29]], align 4
+// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
+// CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**
+// CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 4
+// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
+// CHECK2-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**
+// CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 4
+// CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
+// CHECK2-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 4
+// CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
+// CHECK2-NEXT: store i8* null, i8** [[TMP35]], align 4
+// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK2-NEXT: store i32 2, i32* [[TMP39]], align 4
+// CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK2-NEXT: store i32 5, i32* [[TMP40]], align 4
+// CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK2-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 4
+// CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK2-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4
+// CHECK2-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK2-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 4
+// CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK2-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 4
+// CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK2-NEXT: store i8** null, i8*** [[TMP45]], align 4
+// CHECK2-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK2-NEXT: store i8** null, i8*** [[TMP46]], align 4
+// CHECK2-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK2-NEXT: store i64 0, i64* [[TMP47]], align 8
+// CHECK2-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK2-NEXT: store i64 0, i64* [[TMP48]], align 8
+// CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4
+// CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4
+// CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK2-NEXT: store i32 0, i32* [[TMP51]], align 4
+// CHECK2-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK2-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0
+// CHECK2-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK2: omp_offload.failed:
+// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
+// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK2: omp_offload.cont:
+// CHECK2-NEXT: [[TMP54:%.*]] = mul nsw i32 1, [[TMP1]]
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP54]]
+// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// CHECK2-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
+// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP55]] to i32
+// CHECK2-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4
+// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP56]]
+// CHECK2-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])
+// CHECK2-NEXT: ret i32 [[ADD3]]
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
+// CHECK2-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
+// CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK2-NEXT: store i8 0, i8* [[AAA]], align 1
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
+// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
+// CHECK2-NEXT: store i8 [[TMP2]], i8* [[CONV]], align 1
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
+// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
+// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
+// CHECK2-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
+// CHECK2-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
+// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 4
+// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**
+// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 4
+// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**
+// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 4
+// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 4
+// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK2-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK2-NEXT: store i32 3, i32* [[TMP22]], align 4
+// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK2-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 4
+// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK2-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4
+// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK2-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 4
+// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK2-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 4
+// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK2-NEXT: store i8** null, i8*** [[TMP27]], align 4
+// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK2-NEXT: store i8** null, i8*** [[TMP28]], align 4
+// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK2-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK2-NEXT: store i64 0, i64* [[TMP30]], align 8
+// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4
+// CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4
+// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK2-NEXT: store i32 0, i32* [[TMP33]], align 4
+// CHECK2-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK2-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
+// CHECK2-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK2: omp_offload.failed:
+// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK2: omp_offload.cont:
+// CHECK2-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-NEXT: ret i32 [[TMP36]]
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// CHECK2-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
+// CHECK2-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
+// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
+// CHECK2-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**
+// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
+// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 4
+// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK2-NEXT: store i32 2, i32* [[TMP14]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK2-NEXT: store i32 2, i32* [[TMP15]], align 4
+// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK2-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 4
+// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK2-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 4
+// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK2-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 4
+// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK2-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 4
+// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK2-NEXT: store i8** null, i8*** [[TMP20]], align 4
+// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK2-NEXT: store i8** null, i8*** [[TMP21]], align 4
+// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK2-NEXT: store i64 0, i64* [[TMP22]], align 8
+// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK2-NEXT: store i64 0, i64* [[TMP23]], align 8
+// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK2-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4
+// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK2-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4
+// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK2-NEXT: store i32 0, i32* [[TMP26]], align 4
+// CHECK2-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
+// CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK2: omp_offload.failed:
+// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK2: omp_offload.cont:
+// CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4
+// CHECK2-NEXT: ret i32 [[TMP29]]
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
+// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// CHECK2-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// CHECK2-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
+// CHECK2-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK2-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// CHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// CHECK2-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// CHECK2-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
+// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
+// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 4
+// CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4
+// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// CHECK2-NEXT: store double [[INC]], double* [[A4]], align 4
+// CHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
+// CHECK2-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]
+// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// CHECK2-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
+// CHECK2-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// CHECK2-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// CHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
+// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// CHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
+// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK2-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
+// CHECK2-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32
+// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
+// CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
+// CHECK2-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1
+// CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// CHECK2-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// CHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK2-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK2-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CHECK2-SAME: () #[[ATTR5:[0-9]+]] {
+// CHECK2-NEXT: entry:
+// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@_Z3fooiPd
+// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
+// CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// CHECK3-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK3-NEXT: [[P:%.*]] = alloca i32*, align 64
+// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[GA_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [9 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [9 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [9 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
+// CHECK3-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-NEXT: [[KERNEL_ARGS11:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
+// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
+// CHECK3-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
+// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
+// CHECK3-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
+// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
+// CHECK3-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[TMP4]], i32* [[X]], align 4
+// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4
+// CHECK3-NEXT: store i32* [[A]], i32** [[P]], align 64
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[P]], align 64
+// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* @ga, align 4
+// CHECK3-NEXT: store i32 [[TMP9]], i32* [[GA_CASTED]], align 4
+// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[GA_CASTED]], align 4
+// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
+// CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP12]], align 4
+// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
+// CHECK3-NEXT: store i32 [[TMP7]], i32* [[TMP14]], align 4
+// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4
+// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32**
+// CHECK3-NEXT: store i32* [[TMP8]], i32** [[TMP17]], align 4
+// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32**
+// CHECK3-NEXT: store i32* [[TMP8]], i32** [[TMP19]], align 4
+// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4
+// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
+// CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP22]], align 4
+// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
+// CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP24]], align 4
+// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4
+// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK3-NEXT: store i32 2, i32* [[TMP28]], align 4
+// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK3-NEXT: store i32 3, i32* [[TMP29]], align 4
+// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK3-NEXT: store i8** [[TMP26]], i8*** [[TMP30]], align 4
+// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK3-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4
+// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP32]], align 4
+// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP33]], align 4
+// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK3-NEXT: store i8** null, i8*** [[TMP34]], align 4
+// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK3-NEXT: store i8** null, i8*** [[TMP35]], align 4
+// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK3-NEXT: store i64 0, i64* [[TMP36]], align 8
+// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK3-NEXT: store i64 0, i64* [[TMP37]], align 8
+// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP38]], align 4
+// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP39]], align 4
+// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK3-NEXT: store i32 0, i32* [[TMP40]], align 4
+// CHECK3-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK3-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0
+// CHECK3-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK3: omp_offload.failed:
+// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63(i32 [[TMP7]], i32* [[TMP8]], i32 [[TMP10]]) #[[ATTR3:[0-9]+]]
+// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK3: omp_offload.cont:
+// CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[AA]], align 2
+// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
+// CHECK3-NEXT: store i16 [[TMP43]], i16* [[CONV]], align 2
+// CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[AA_CASTED]], align 4
+// CHECK3-NEXT: [[TMP45:%.*]] = mul nuw i32 [[TMP0]], 4
+// CHECK3-NEXT: [[TMP46:%.*]] = sext i32 [[TMP45]] to i64
+// CHECK3-NEXT: [[TMP47:%.*]] = mul nuw i32 5, [[TMP2]]
+// CHECK3-NEXT: [[TMP48:%.*]] = mul nuw i32 [[TMP47]], 8
+// CHECK3-NEXT: [[TMP49:%.*]] = sext i32 [[TMP48]] to i64
+// CHECK3-NEXT: [[TMP50:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.1 to i8*), i32 72, i1 false)
+// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
+// CHECK3-NEXT: store i32 [[TMP44]], i32* [[TMP52]], align 4
+// CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to i32*
+// CHECK3-NEXT: store i32 [[TMP44]], i32* [[TMP54]], align 4
+// CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
+// CHECK3-NEXT: store i8* null, i8** [[TMP55]], align 4
+// CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to [10 x float]**
+// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP57]], align 4
+// CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to [10 x float]**
+// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP59]], align 4
+// CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
+// CHECK3-NEXT: store i8* null, i8** [[TMP60]], align 4
+// CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
+// CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP62]], align 4
+// CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*
+// CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP64]], align 4
+// CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 2
+// CHECK3-NEXT: store i8* null, i8** [[TMP65]], align 4
+// CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 3
+// CHECK3-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to float**
+// CHECK3-NEXT: store float* [[VLA]], float** [[TMP67]], align 4
+// CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 3
+// CHECK3-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to float**
+// CHECK3-NEXT: store float* [[VLA]], float** [[TMP69]], align 4
+// CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
+// CHECK3-NEXT: store i64 [[TMP46]], i64* [[TMP70]], align 4
+// CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 3
+// CHECK3-NEXT: store i8* null, i8** [[TMP71]], align 4
+// CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 4
+// CHECK3-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [5 x [10 x double]]**
+// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP73]], align 4
+// CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 4
+// CHECK3-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [5 x [10 x double]]**
+// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP75]], align 4
+// CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 4
+// CHECK3-NEXT: store i8* null, i8** [[TMP76]], align 4
+// CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 5
+// CHECK3-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32*
+// CHECK3-NEXT: store i32 5, i32* [[TMP78]], align 4
+// CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 5
+// CHECK3-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*
+// CHECK3-NEXT: store i32 5, i32* [[TMP80]], align 4
+// CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 5
+// CHECK3-NEXT: store i8* null, i8** [[TMP81]], align 4
+// CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 6
+// CHECK3-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32*
+// CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP83]], align 4
+// CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 6
+// CHECK3-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32*
+// CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP85]], align 4
+// CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 6
+// CHECK3-NEXT: store i8* null, i8** [[TMP86]], align 4
+// CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 7
+// CHECK3-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to double**
+// CHECK3-NEXT: store double* [[VLA1]], double** [[TMP88]], align 4
+// CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 7
+// CHECK3-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to double**
+// CHECK3-NEXT: store double* [[VLA1]], double** [[TMP90]], align 4
+// CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
+// CHECK3-NEXT: store i64 [[TMP49]], i64* [[TMP91]], align 4
+// CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 7
+// CHECK3-NEXT: store i8* null, i8** [[TMP92]], align 4
+// CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 8
+// CHECK3-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to %struct.TT**
+// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP94]], align 4
+// CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 8
+// CHECK3-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to %struct.TT**
+// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP96]], align 4
+// CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 8
+// CHECK3-NEXT: store i8* null, i8** [[TMP97]], align 4
+// CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 0
+// CHECK3-NEXT: store i32 2, i32* [[TMP101]], align 4
+// CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 1
+// CHECK3-NEXT: store i32 9, i32* [[TMP102]], align 4
+// CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 2
+// CHECK3-NEXT: store i8** [[TMP98]], i8*** [[TMP103]], align 4
+// CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 3
+// CHECK3-NEXT: store i8** [[TMP99]], i8*** [[TMP104]], align 4
+// CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 4
+// CHECK3-NEXT: store i64* [[TMP100]], i64** [[TMP105]], align 4
+// CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 5
+// CHECK3-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.2, i32 0, i32 0), i64** [[TMP106]], align 4
+// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 6
+// CHECK3-NEXT: store i8** null, i8*** [[TMP107]], align 4
+// CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 7
+// CHECK3-NEXT: store i8** null, i8*** [[TMP108]], align 4
+// CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 8
+// CHECK3-NEXT: store i64 0, i64* [[TMP109]], align 8
+// CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 9
+// CHECK3-NEXT: store i64 0, i64* [[TMP110]], align 8
+// CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 10
+// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP111]], align 4
+// CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 11
+// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP112]], align 4
+// CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]], i32 0, i32 12
+// CHECK3-NEXT: store i32 0, i32* [[TMP113]], align 4
+// CHECK3-NEXT: [[TMP114:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS5]])
+// CHECK3-NEXT: [[TMP115:%.*]] = icmp ne i32 [[TMP114]], 0
+// CHECK3-NEXT: br i1 [[TMP115]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CHECK3: omp_offload.failed6:
+// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70(i32 [[TMP44]], [10 x float]* [[B]], i32 [[TMP0]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP2]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
+// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CHECK3: omp_offload.cont7:
+// CHECK3-NEXT: [[TMP116:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to double**
+// CHECK3-NEXT: store double* [[TMP116]], double** [[TMP118]], align 4
+// CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to double**
+// CHECK3-NEXT: store double* [[TMP116]], double** [[TMP120]], align 4
+// CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0
+// CHECK3-NEXT: store i8* null, i8** [[TMP121]], align 4
+// CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to %struct.TT.0**
+// CHECK3-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP123]], align 4
+// CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to %struct.TT.0**
+// CHECK3-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[TMP125]], align 4
+// CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1
+// CHECK3-NEXT: store i8* null, i8** [[TMP126]], align 4
+// CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 0
+// CHECK3-NEXT: store i32 2, i32* [[TMP129]], align 4
+// CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 1
+// CHECK3-NEXT: store i32 2, i32* [[TMP130]], align 4
+// CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 2
+// CHECK3-NEXT: store i8** [[TMP127]], i8*** [[TMP131]], align 4
+// CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 3
+// CHECK3-NEXT: store i8** [[TMP128]], i8*** [[TMP132]], align 4
+// CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 4
+// CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.3, i32 0, i32 0), i64** [[TMP133]], align 4
+// CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 5
+// CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.4, i32 0, i32 0), i64** [[TMP134]], align 4
+// CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 6
+// CHECK3-NEXT: store i8** null, i8*** [[TMP135]], align 4
+// CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 7
+// CHECK3-NEXT: store i8** null, i8*** [[TMP136]], align 4
+// CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 8
+// CHECK3-NEXT: store i64 0, i64* [[TMP137]], align 8
+// CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 9
+// CHECK3-NEXT: store i64 0, i64* [[TMP138]], align 8
+// CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 10
+// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP139]], align 4
+// CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 11
+// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP140]], align 4
+// CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]], i32 0, i32 12
+// CHECK3-NEXT: store i32 0, i32* [[TMP141]], align 4
+// CHECK3-NEXT: [[TMP142:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS11]])
+// CHECK3-NEXT: [[TMP143:%.*]] = icmp ne i32 [[TMP142]], 0
+// CHECK3-NEXT: br i1 [[TMP143]], label [[OMP_OFFLOAD_FAILED12:%.*]], label [[OMP_OFFLOAD_CONT13:%.*]]
+// CHECK3: omp_offload.failed12:
+// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111(double* [[TMP116]], %struct.TT.0* [[E]]) #[[ATTR3]]
+// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT13]]
+// CHECK3: omp_offload.cont13:
+// CHECK3-NEXT: [[TMP144:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-NEXT: [[TMP145:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP145]])
+// CHECK3-NEXT: ret i32 [[TMP144]]
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// CHECK3-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4
+// CHECK3-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK3-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// CHECK3-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
+// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
+// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
+// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
+// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
+// CHECK3-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
+// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
+// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
+// CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
+// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
+// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
+// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
+// CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
+// CHECK3-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// CHECK3-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)
+// CHECK3-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// CHECK3-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4
+// CHECK3-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
+// CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK3-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4
+// CHECK3-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// CHECK3-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)
+// CHECK3-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// CHECK3-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)
+// CHECK3-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// CHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8
+// CHECK3-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4
+// CHECK3-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4
+// CHECK3-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// CHECK3-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
+// CHECK3-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// CHECK3-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)
+// CHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// CHECK3-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)
+// CHECK3-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// CHECK3-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// CHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK3-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2
+// CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3
+// CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1
+// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
+// CHECK3-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// CHECK3-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]
+// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]
+// CHECK3-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3
+// CHECK3-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// CHECK3-NEXT: store i64 1, i64* [[X]], align 4
+// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// CHECK3-NEXT: store i8 1, i8* [[Y]], align 4
+// CHECK3-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// CHECK3-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR2]] {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK3-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4
+// CHECK3-NEXT: [[E1:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// CHECK3-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK3-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = bitcast %struct.TT.0* [[E1]] to i8*
+// CHECK3-NEXT: [[TMP2:%.*]] = bitcast %struct.TT.0* [[TMP0]] to i8*
+// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 8, i1 false)
+// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E1]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP3]] to double
+// CHECK3-NEXT: [[TMP4:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP4]], i32 0
+// CHECK3-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[TMP5]], i32 0
+// CHECK3-NEXT: [[TMP6:%.*]] = load double, double* [[ARRAYIDX2]], align 4
+// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// CHECK3-NEXT: store double [[INC]], double* [[ARRAYIDX2]], align 4
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@_Z3bariPd
+// CHECK3-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
+// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])
+// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-NEXT: ret i32 [[TMP9]]
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
+// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
+// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
+// CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
+// CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
+// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 2, [[TMP1]]
+// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// CHECK3-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i64
+// CHECK3-NEXT: [[TMP9:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
+// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP9]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.5 to i8*), i32 40, i1 false)
+// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
+// CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
+// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
+// CHECK3-NEXT: store double* [[A]], double** [[TMP13]], align 4
+// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4
+// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
+// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP16]], align 4
+// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
+// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
+// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4
+// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
+// CHECK3-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
+// CHECK3-NEXT: store i32 2, i32* [[TMP23]], align 4
+// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4
+// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
+// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP26]], align 4
+// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
+// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP28]], align 4
+// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
+// CHECK3-NEXT: store i8* null, i8** [[TMP29]], align 4
+// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
+// CHECK3-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i16**
+// CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP31]], align 4
+// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
+// CHECK3-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i16**
+// CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP33]], align 4
+// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
+// CHECK3-NEXT: store i64 [[TMP8]], i64* [[TMP34]], align 4
+// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
+// CHECK3-NEXT: store i8* null, i8** [[TMP35]], align 4
+// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK3-NEXT: store i32 2, i32* [[TMP39]], align 4
+// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK3-NEXT: store i32 5, i32* [[TMP40]], align 4
+// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK3-NEXT: store i8** [[TMP36]], i8*** [[TMP41]], align 4
+// CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK3-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4
+// CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK3-NEXT: store i64* [[TMP38]], i64** [[TMP43]], align 4
+// CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK3-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP44]], align 4
+// CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK3-NEXT: store i8** null, i8*** [[TMP45]], align 4
+// CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK3-NEXT: store i8** null, i8*** [[TMP46]], align 4
+// CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK3-NEXT: store i64 0, i64* [[TMP47]], align 8
+// CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK3-NEXT: store i64 0, i64* [[TMP48]], align 8
+// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP49]], align 4
+// CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP50]], align 4
+// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK3-NEXT: store i32 0, i32* [[TMP51]], align 4
+// CHECK3-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK3-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0
+// CHECK3-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK3: omp_offload.failed:
+// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
+// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK3: omp_offload.cont:
+// CHECK3-NEXT: [[TMP54:%.*]] = mul nsw i32 1, [[TMP1]]
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP54]]
+// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// CHECK3-NEXT: [[TMP55:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
+// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP55]] to i32
+// CHECK3-NEXT: [[TMP56:%.*]] = load i32, i32* [[B]], align 4
+// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP56]]
+// CHECK3-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP57]])
+// CHECK3-NEXT: ret i32 [[ADD3]]
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
+// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
+// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1
+// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
+// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
+// CHECK3-NEXT: store i8 [[TMP2]], i8* [[CONV]], align 1
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
+// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
+// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
+// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4
+// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4
+// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
+// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4
+// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32*
+// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4
+// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4
+// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [10 x i32]**
+// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP15]], align 4
+// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [10 x i32]**
+// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP17]], align 4
+// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4
+// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK3-NEXT: store i32 2, i32* [[TMP21]], align 4
+// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK3-NEXT: store i32 3, i32* [[TMP22]], align 4
+// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK3-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 4
+// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK3-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4
+// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP25]], align 4
+// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP26]], align 4
+// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK3-NEXT: store i8** null, i8*** [[TMP27]], align 4
+// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK3-NEXT: store i8** null, i8*** [[TMP28]], align 4
+// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK3-NEXT: store i64 0, i64* [[TMP29]], align 8
+// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK3-NEXT: store i64 0, i64* [[TMP30]], align 8
+// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP31]], align 4
+// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP32]], align 4
+// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK3-NEXT: store i32 0, i32* [[TMP33]], align 4
+// CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
+// CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK3: omp_offload.failed:
+// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK3: omp_offload.cont:
+// CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-NEXT: ret i32 [[TMP36]]
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [2 x i8*], align 4
+// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
+// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
+// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4
+// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to [10 x i32]**
+// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP8]], align 4
+// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to [10 x i32]**
+// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP10]], align 4
+// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4
+// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK3-NEXT: store i32 2, i32* [[TMP14]], align 4
+// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK3-NEXT: store i32 2, i32* [[TMP15]], align 4
+// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK3-NEXT: store i8** [[TMP12]], i8*** [[TMP16]], align 4
+// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK3-NEXT: store i8** [[TMP13]], i8*** [[TMP17]], align 4
+// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.9, i32 0, i32 0), i64** [[TMP18]], align 4
+// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.10, i32 0, i32 0), i64** [[TMP19]], align 4
+// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK3-NEXT: store i8** null, i8*** [[TMP20]], align 4
+// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK3-NEXT: store i8** null, i8*** [[TMP21]], align 4
+// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK3-NEXT: store i64 0, i64* [[TMP22]], align 8
+// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK3-NEXT: store i64 0, i64* [[TMP23]], align 8
+// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK3-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], [3 x i32]* [[TMP24]], align 4
+// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK3-NEXT: store [3 x i32] zeroinitializer, [3 x i32]* [[TMP25]], align 4
+// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK3-NEXT: store i32 0, i32* [[TMP26]], align 4
+// CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 -1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]])
+// CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
+// CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK3: omp_offload.failed:
+// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128(i32 [[TMP1]], [10 x i32]* [[B]]) #[[ATTR3]]
+// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CHECK3: omp_offload.cont:
+// CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4
+// CHECK3-NEXT: ret i32 [[TMP29]]
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
+// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// CHECK3-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// CHECK3-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
+// CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// CHECK3-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// CHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// CHECK3-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)
+// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
+// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
+// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4
+// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4
+// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// CHECK3-NEXT: store double [[INC]], double* [[A4]], align 4
+// CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
+// CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]
+// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// CHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
+// CHECK3-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// CHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
+// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
+// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK3-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
+// CHECK3-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32
+// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
+// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
+// CHECK3-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1
+// CHECK3-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// CHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// CHECK3-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK3-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CHECK3-SAME: () #[[ATTR5:[0-9]+]] {
+// CHECK3-NEXT: entry:
+// CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
+// CHECK3-NEXT: ret void
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z3fooiPd
+// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[AA:%.*]] = alloca i16, align 2
+// SIMD-ONLY0-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// SIMD-ONLY0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// SIMD-ONLY0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// SIMD-ONLY0-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// SIMD-ONLY0-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// SIMD-ONLY0-NEXT: [[P:%.*]] = alloca i32*, align 64
+// SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: store i16 0, i16* [[AA]], align 2
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY0-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
+// SIMD-ONLY0-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
+// SIMD-ONLY0-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
+// SIMD-ONLY0-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// SIMD-ONLY0-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: store i32 [[TMP6]], i32* [[X]], align 4
+// SIMD-ONLY0-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4
+// SIMD-ONLY0-NEXT: store i32* [[A]], i32** [[P]], align 64
+// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i16, i16* [[AA]], align 2
+// SIMD-ONLY0-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
+// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY0-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
+// SIMD-ONLY0-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2
+// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
+// SIMD-ONLY0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
+// SIMD-ONLY0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4
+// SIMD-ONLY0-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
+// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2
+// SIMD-ONLY0-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8
+// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]]
+// SIMD-ONLY0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]]
+// SIMD-ONLY0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i64 3
+// SIMD-ONLY0-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8
+// SIMD-ONLY0-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: store i64 1, i64* [[X8]], align 8
+// SIMD-ONLY0-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
+// SIMD-ONLY0-NEXT: store i8 1, i8* [[Y9]], align 8
+// SIMD-ONLY0-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, i32* [[X10]], align 4
+// SIMD-ONLY0-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double
+// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP11]], i64 0
+// SIMD-ONLY0-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 8
+// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP12]], i64 0
+// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX13]], align 8
+// SIMD-ONLY0-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
+// SIMD-ONLY0-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 8
+// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY0-NEXT: call void @llvm.stackrestore(i8* [[TMP15]])
+// SIMD-ONLY0-NEXT: ret i32 [[TMP14]]
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z3bariPd
+// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
+// SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])
+// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// SIMD-ONLY0-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])
+// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// SIMD-ONLY0-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])
+// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// SIMD-ONLY0-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: ret i32 [[TMP9]]
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// SIMD-ONLY0-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[B:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// SIMD-ONLY0-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// SIMD-ONLY0-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY0-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
+// SIMD-ONLY0-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
+// SIMD-ONLY0-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
+// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY0-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
+// SIMD-ONLY0-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
+// SIMD-ONLY0-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: store double [[ADD2]], double* [[A]], align 8
+// SIMD-ONLY0-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8
+// SIMD-ONLY0-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// SIMD-ONLY0-NEXT: store double [[INC]], double* [[A3]], align 8
+// SIMD-ONLY0-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
+// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
+// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
+// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// SIMD-ONLY0-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
+// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
+// SIMD-ONLY0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
+// SIMD-ONLY0-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
+// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
+// SIMD-ONLY0-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
+// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY0-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
+// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY0-NEXT: call void @llvm.stackrestore(i8* [[TMP11]])
+// SIMD-ONLY0-NEXT: ret i32 [[ADD9]]
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZL7fstatici
+// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// SIMD-ONLY0-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: store i8 0, i8* [[AAA]], align 1
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1
+// SIMD-ONLY0-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
+// SIMD-ONLY0-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY0-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8
+// SIMD-ONLY0-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1
+// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
+// SIMD-ONLY0-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: ret i32 [[TMP3]]
+//
+//
+// SIMD-ONLY0-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// SIMD-ONLY0-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY0-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY0-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY0-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY0-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1
+// SIMD-ONLY0-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY0-NEXT: ret i32 [[TMP2]]
+//
+//
+// SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z3fooiPd
+// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY01-NEXT: entry:
+// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY01-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY01-NEXT: [[AA:%.*]] = alloca i16, align 2
+// SIMD-ONLY01-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// SIMD-ONLY01-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// SIMD-ONLY01-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// SIMD-ONLY01-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// SIMD-ONLY01-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// SIMD-ONLY01-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// SIMD-ONLY01-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// SIMD-ONLY01-NEXT: [[P:%.*]] = alloca i32*, align 64
+// SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: store i16 0, i16* [[AA]], align 2
+// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY01-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY01-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
+// SIMD-ONLY01-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
+// SIMD-ONLY01-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
+// SIMD-ONLY01-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// SIMD-ONLY01-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: store i32 [[TMP6]], i32* [[X]], align 4
+// SIMD-ONLY01-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// SIMD-ONLY01-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4
+// SIMD-ONLY01-NEXT: store i32* [[A]], i32** [[P]], align 64
+// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = load i16, i16* [[AA]], align 2
+// SIMD-ONLY01-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
+// SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY01-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
+// SIMD-ONLY01-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2
+// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
+// SIMD-ONLY01-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// SIMD-ONLY01-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
+// SIMD-ONLY01-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4
+// SIMD-ONLY01-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
+// SIMD-ONLY01-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2
+// SIMD-ONLY01-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8
+// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]]
+// SIMD-ONLY01-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]]
+// SIMD-ONLY01-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i64 3
+// SIMD-ONLY01-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8
+// SIMD-ONLY01-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
+// SIMD-ONLY01-NEXT: store i64 1, i64* [[X8]], align 8
+// SIMD-ONLY01-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
+// SIMD-ONLY01-NEXT: store i8 1, i8* [[Y9]], align 8
+// SIMD-ONLY01-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY01-NEXT: [[TMP10:%.*]] = load i32, i32* [[X10]], align 4
+// SIMD-ONLY01-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double
+// SIMD-ONLY01-NEXT: [[TMP11:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP11]], i64 0
+// SIMD-ONLY01-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 8
+// SIMD-ONLY01-NEXT: [[TMP12:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP12]], i64 0
+// SIMD-ONLY01-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX13]], align 8
+// SIMD-ONLY01-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
+// SIMD-ONLY01-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 8
+// SIMD-ONLY01-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY01-NEXT: call void @llvm.stackrestore(i8* [[TMP15]])
+// SIMD-ONLY01-NEXT: ret i32 [[TMP14]]
+//
+//
+// SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z3bariPd
+// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY01-NEXT: entry:
+// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY01-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY01-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
+// SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])
+// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// SIMD-ONLY01-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])
+// SIMD-ONLY01-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// SIMD-ONLY01-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])
+// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// SIMD-ONLY01-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])
+// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// SIMD-ONLY01-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: ret i32 [[TMP9]]
+//
+//
+// SIMD-ONLY01-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// SIMD-ONLY01-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY01-NEXT: entry:
+// SIMD-ONLY01-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY01-NEXT: [[B:%.*]] = alloca i32, align 4
+// SIMD-ONLY01-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// SIMD-ONLY01-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// SIMD-ONLY01-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY01-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY01-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY01-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
+// SIMD-ONLY01-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
+// SIMD-ONLY01-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
+// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY01-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
+// SIMD-ONLY01-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
+// SIMD-ONLY01-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY01-NEXT: store double [[ADD2]], double* [[A]], align 8
+// SIMD-ONLY01-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8
+// SIMD-ONLY01-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// SIMD-ONLY01-NEXT: store double [[INC]], double* [[A3]], align 8
+// SIMD-ONLY01-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
+// SIMD-ONLY01-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
+// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
+// SIMD-ONLY01-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// SIMD-ONLY01-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
+// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
+// SIMD-ONLY01-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
+// SIMD-ONLY01-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
+// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
+// SIMD-ONLY01-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
+// SIMD-ONLY01-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY01-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
+// SIMD-ONLY01-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY01-NEXT: call void @llvm.stackrestore(i8* [[TMP11]])
+// SIMD-ONLY01-NEXT: ret i32 [[ADD9]]
+//
+//
+// SIMD-ONLY01-LABEL: define {{[^@]+}}@_ZL7fstatici
+// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY01-NEXT: entry:
+// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY01-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// SIMD-ONLY01-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: store i8 0, i8* [[AAA]], align 1
+// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY01-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1
+// SIMD-ONLY01-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
+// SIMD-ONLY01-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY01-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8
+// SIMD-ONLY01-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1
+// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
+// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY01-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
+// SIMD-ONLY01-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: ret i32 [[TMP3]]
+//
+//
+// SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// SIMD-ONLY01-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY01-NEXT: entry:
+// SIMD-ONLY01-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY01-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY01-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY01-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY01-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY01-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
+// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY01-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1
+// SIMD-ONLY01-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY01-NEXT: ret i32 [[TMP2]]
+//
+//
+// SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z3fooiPd
+// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY02-NEXT: entry:
+// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[AA:%.*]] = alloca i16, align 2
+// SIMD-ONLY02-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// SIMD-ONLY02-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// SIMD-ONLY02-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// SIMD-ONLY02-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// SIMD-ONLY02-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// SIMD-ONLY02-NEXT: [[P:%.*]] = alloca i32*, align 64
+// SIMD-ONLY02-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: store i16 0, i16* [[AA]], align 2
+// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY02-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY02-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
+// SIMD-ONLY02-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
+// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
+// SIMD-ONLY02-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
+// SIMD-ONLY02-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// SIMD-ONLY02-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store i32 [[TMP4]], i32* [[X]], align 4
+// SIMD-ONLY02-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4
+// SIMD-ONLY02-NEXT: store i32* [[A]], i32** [[P]], align 64
+// SIMD-ONLY02-NEXT: [[TMP6:%.*]] = load i16, i16* [[AA]], align 2
+// SIMD-ONLY02-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i32
+// SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY02-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
+// SIMD-ONLY02-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2
+// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
+// SIMD-ONLY02-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// SIMD-ONLY02-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
+// SIMD-ONLY02-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4
+// SIMD-ONLY02-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
+// SIMD-ONLY02-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2
+// SIMD-ONLY02-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8
+// SIMD-ONLY02-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]
+// SIMD-ONLY02-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]]
+// SIMD-ONLY02-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i32 3
+// SIMD-ONLY02-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8
+// SIMD-ONLY02-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
+// SIMD-ONLY02-NEXT: store i64 1, i64* [[X8]], align 4
+// SIMD-ONLY02-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
+// SIMD-ONLY02-NEXT: store i8 1, i8* [[Y9]], align 4
+// SIMD-ONLY02-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i32, i32* [[X10]], align 4
+// SIMD-ONLY02-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double
+// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP9]], i32 0
+// SIMD-ONLY02-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 4
+// SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP10]], i32 0
+// SIMD-ONLY02-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 4
+// SIMD-ONLY02-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// SIMD-ONLY02-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 4
+// SIMD-ONLY02-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY02-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// SIMD-ONLY02-NEXT: ret i32 [[TMP12]]
+//
+//
+// SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z3bariPd
+// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY02-NEXT: entry:
+// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
+// SIMD-ONLY02-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])
+// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// SIMD-ONLY02-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])
+// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// SIMD-ONLY02-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])
+// SIMD-ONLY02-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// SIMD-ONLY02-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])
+// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// SIMD-ONLY02-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: ret i32 [[TMP9]]
+//
+//
+// SIMD-ONLY02-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// SIMD-ONLY02-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY02-NEXT: entry:
+// SIMD-ONLY02-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[B:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// SIMD-ONLY02-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY02-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY02-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
+// SIMD-ONLY02-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
+// SIMD-ONLY02-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY02-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
+// SIMD-ONLY02-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
+// SIMD-ONLY02-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY02-NEXT: store double [[ADD2]], double* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
+// SIMD-ONLY02-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
+// SIMD-ONLY02-NEXT: store double [[INC]], double* [[A3]], align 4
+// SIMD-ONLY02-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
+// SIMD-ONLY02-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
+// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
+// SIMD-ONLY02-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// SIMD-ONLY02-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
+// SIMD-ONLY02-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
+// SIMD-ONLY02-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
+// SIMD-ONLY02-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
+// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
+// SIMD-ONLY02-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
+// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY02-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
+// SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY02-NEXT: call void @llvm.stackrestore(i8* [[TMP10]])
+// SIMD-ONLY02-NEXT: ret i32 [[ADD9]]
+//
+//
+// SIMD-ONLY02-LABEL: define {{[^@]+}}@_ZL7fstatici
+// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY02-NEXT: entry:
+// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// SIMD-ONLY02-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY02-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: store i8 0, i8* [[AAA]], align 1
+// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY02-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1
+// SIMD-ONLY02-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
+// SIMD-ONLY02-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY02-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8
+// SIMD-ONLY02-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1
+// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
+// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY02-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
+// SIMD-ONLY02-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: ret i32 [[TMP3]]
+//
+//
+// SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// SIMD-ONLY02-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY02-NEXT: entry:
+// SIMD-ONLY02-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY02-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY02-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY02-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
+// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY02-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1
+// SIMD-ONLY02-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY02-NEXT: ret i32 [[TMP2]]
+//
+//
+// SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z3fooiPd
+// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY03-NEXT: entry:
+// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[AA:%.*]] = alloca i16, align 2
+// SIMD-ONLY03-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// SIMD-ONLY03-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// SIMD-ONLY03-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// SIMD-ONLY03-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// SIMD-ONLY03-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// SIMD-ONLY03-NEXT: [[P:%.*]] = alloca i32*, align 64
+// SIMD-ONLY03-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: store i16 0, i16* [[AA]], align 2
+// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY03-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY03-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
+// SIMD-ONLY03-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
+// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
+// SIMD-ONLY03-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
+// SIMD-ONLY03-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// SIMD-ONLY03-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store i32 [[TMP4]], i32* [[X]], align 4
+// SIMD-ONLY03-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4
+// SIMD-ONLY03-NEXT: store i32* [[A]], i32** [[P]], align 64
+// SIMD-ONLY03-NEXT: [[TMP6:%.*]] = load i16, i16* [[AA]], align 2
+// SIMD-ONLY03-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i32
+// SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY03-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
+// SIMD-ONLY03-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2
+// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
+// SIMD-ONLY03-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// SIMD-ONLY03-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
+// SIMD-ONLY03-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4
+// SIMD-ONLY03-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
+// SIMD-ONLY03-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2
+// SIMD-ONLY03-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8
+// SIMD-ONLY03-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]
+// SIMD-ONLY03-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]]
+// SIMD-ONLY03-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i32 3
+// SIMD-ONLY03-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8
+// SIMD-ONLY03-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
+// SIMD-ONLY03-NEXT: store i64 1, i64* [[X8]], align 4
+// SIMD-ONLY03-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
+// SIMD-ONLY03-NEXT: store i8 1, i8* [[Y9]], align 4
+// SIMD-ONLY03-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i32, i32* [[X10]], align 4
+// SIMD-ONLY03-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double
+// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP9]], i32 0
+// SIMD-ONLY03-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 4
+// SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP10]], i32 0
+// SIMD-ONLY03-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 4
+// SIMD-ONLY03-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// SIMD-ONLY03-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 4
+// SIMD-ONLY03-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY03-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// SIMD-ONLY03-NEXT: ret i32 [[TMP12]]
+//
+//
+// SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z3bariPd
+// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY03-NEXT: entry:
+// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
+// SIMD-ONLY03-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])
+// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// SIMD-ONLY03-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])
+// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// SIMD-ONLY03-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])
+// SIMD-ONLY03-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// SIMD-ONLY03-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])
+// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// SIMD-ONLY03-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: ret i32 [[TMP9]]
+//
+//
+// SIMD-ONLY03-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// SIMD-ONLY03-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY03-NEXT: entry:
+// SIMD-ONLY03-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[B:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// SIMD-ONLY03-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY03-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY03-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
+// SIMD-ONLY03-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
+// SIMD-ONLY03-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY03-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
+// SIMD-ONLY03-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
+// SIMD-ONLY03-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY03-NEXT: store double [[ADD2]], double* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
+// SIMD-ONLY03-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
+// SIMD-ONLY03-NEXT: store double [[INC]], double* [[A3]], align 4
+// SIMD-ONLY03-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
+// SIMD-ONLY03-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
+// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
+// SIMD-ONLY03-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// SIMD-ONLY03-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
+// SIMD-ONLY03-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
+// SIMD-ONLY03-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
+// SIMD-ONLY03-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
+// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
+// SIMD-ONLY03-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
+// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY03-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
+// SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY03-NEXT: call void @llvm.stackrestore(i8* [[TMP10]])
+// SIMD-ONLY03-NEXT: ret i32 [[ADD9]]
+//
+//
+// SIMD-ONLY03-LABEL: define {{[^@]+}}@_ZL7fstatici
+// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY03-NEXT: entry:
+// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// SIMD-ONLY03-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY03-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: store i8 0, i8* [[AAA]], align 1
+// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY03-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1
+// SIMD-ONLY03-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
+// SIMD-ONLY03-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY03-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8
+// SIMD-ONLY03-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1
+// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
+// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY03-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
+// SIMD-ONLY03-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: ret i32 [[TMP3]]
+//
+//
+// SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// SIMD-ONLY03-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY03-NEXT: entry:
+// SIMD-ONLY03-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY03-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY03-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY03-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
+// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY03-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1
+// SIMD-ONLY03-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY03-NEXT: ret i32 [[TMP2]]
+//
+//
+// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// TCHECK-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {
+// TCHECK-NEXT: entry:
+// TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8
+// TCHECK-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8
+// TCHECK-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8
+// TCHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*
+// TCHECK-NEXT: ret void
+//
+//
+// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// TCHECK-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
+// TCHECK-NEXT: entry:
+// TCHECK-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
+// TCHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
+// TCHECK-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
+// TCHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
+// TCHECK-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
+// TCHECK-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// TCHECK-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// TCHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// TCHECK-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// TCHECK-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
+// TCHECK-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
+// TCHECK-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// TCHECK-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
+// TCHECK-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
+// TCHECK-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// TCHECK-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
+// TCHECK-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
+// TCHECK-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
+// TCHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
+// TCHECK-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
+// TCHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// TCHECK-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
+// TCHECK-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
+// TCHECK-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// TCHECK-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
+// TCHECK-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
+// TCHECK-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
+// TCHECK-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// TCHECK-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)
+// TCHECK-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// TCHECK-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8
+// TCHECK-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
+// TCHECK-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// TCHECK-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4
+// TCHECK-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// TCHECK-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)
+// TCHECK-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// TCHECK-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)
+// TCHECK-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// TCHECK-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8
+// TCHECK-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// TCHECK-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8
+// TCHECK-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// TCHECK-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8
+// TCHECK-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// TCHECK-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)
+// TCHECK-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// TCHECK-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)
+// TCHECK-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// TCHECK-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// TCHECK-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// TCHECK-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2
+// TCHECK-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// TCHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3
+// TCHECK-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// TCHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1
+// TCHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2
+// TCHECK-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// TCHECK-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]
+// TCHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]
+// TCHECK-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
+// TCHECK-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// TCHECK-NEXT: store i64 1, i64* [[X]], align 8
+// TCHECK-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// TCHECK-NEXT: store i8 1, i8* [[Y]], align 8
+// TCHECK-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// TCHECK-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// TCHECK-NEXT: ret void
+//
+//
+// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// TCHECK-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
+// TCHECK-NEXT: entry:
+// TCHECK-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// TCHECK-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8
+// TCHECK-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// TCHECK-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8
+// TCHECK-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8
+// TCHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0
+// TCHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4
+// TCHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
+// TCHECK-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 0
+// TCHECK-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8
+// TCHECK-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// TCHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i64 0
+// TCHECK-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 8
+// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00
+// TCHECK-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 8
+// TCHECK-NEXT: ret void
+//
+//
+// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// TCHECK-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK-NEXT: entry:
+// TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// TCHECK-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
+// TCHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
+// TCHECK-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// TCHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
+// TCHECK-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// TCHECK-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*
+// TCHECK-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// TCHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// TCHECK-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
+// TCHECK-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32
+// TCHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
+// TCHECK-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
+// TCHECK-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1
+// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2
+// TCHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
+// TCHECK-NEXT: ret void
+//
+//
+// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// TCHECK-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
+// TCHECK-NEXT: entry:
+// TCHECK-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
+// TCHECK-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// TCHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// TCHECK-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
+// TCHECK-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// TCHECK-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// TCHECK-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
+// TCHECK-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// TCHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
+// TCHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// TCHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// TCHECK-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
+// TCHECK-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// TCHECK-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
+// TCHECK-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// TCHECK-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
+// TCHECK-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// TCHECK-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8
+// TCHECK-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// TCHECK-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
+// TCHECK-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// TCHECK-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)
+// TCHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double
+// TCHECK-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
+// TCHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK-NEXT: store double [[ADD]], double* [[A]], align 8
+// TCHECK-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8
+// TCHECK-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// TCHECK-NEXT: store double [[INC]], double* [[A5]], align 8
+// TCHECK-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
+// TCHECK-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]
+// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]
+// TCHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// TCHECK-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
+// TCHECK-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// TCHECK-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// TCHECK-NEXT: ret void
+//
+//
+// TCHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// TCHECK-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK-NEXT: entry:
+// TCHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// TCHECK-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// TCHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// TCHECK-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// TCHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2
+// TCHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// TCHECK-NEXT: ret void
+//
+//
+// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// TCHECK1-SAME: (i64 noundef [[A:%.*]], i32* noundef [[P:%.*]], i64 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {
+// TCHECK1-NEXT: entry:
+// TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 8
+// TCHECK1-NEXT: [[GA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK1-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 8
+// TCHECK1-NEXT: store i64 [[GA]], i64* [[GA_ADDR]], align 8
+// TCHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[GA_ADDR]] to i32*
+// TCHECK1-NEXT: ret void
+//
+//
+// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// TCHECK1-SAME: (i64 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
+// TCHECK1-NEXT: entry:
+// TCHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
+// TCHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
+// TCHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
+// TCHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
+// TCHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
+// TCHECK1-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// TCHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// TCHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// TCHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[__VLA_EXPR2:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// TCHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
+// TCHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
+// TCHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// TCHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
+// TCHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
+// TCHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// TCHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
+// TCHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
+// TCHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
+// TCHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
+// TCHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// TCHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
+// TCHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// TCHECK1-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 40, i1 false)
+// TCHECK1-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// TCHECK1-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 8
+// TCHECK1-NEXT: [[VLA6:%.*]] = alloca float, i64 [[TMP1]], align 4
+// TCHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// TCHECK1-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP1]], 4
+// TCHECK1-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// TCHECK1-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i64 [[TMP11]], i1 false)
+// TCHECK1-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// TCHECK1-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i64 400, i1 false)
+// TCHECK1-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// TCHECK1-NEXT: [[VLA8:%.*]] = alloca double, i64 [[TMP16]], align 8
+// TCHECK1-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// TCHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR2]], align 8
+// TCHECK1-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP4]], [[TMP5]]
+// TCHECK1-NEXT: [[TMP18:%.*]] = mul nuw i64 [[TMP17]], 8
+// TCHECK1-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// TCHECK1-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i64 [[TMP18]], i1 false)
+// TCHECK1-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// TCHECK1-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP21]], i8* align 8 [[TMP22]], i64 16, i1 false)
+// TCHECK1-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// TCHECK1-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// TCHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// TCHECK1-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2
+// TCHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// TCHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3
+// TCHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// TCHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1
+// TCHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2
+// TCHECK1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// TCHECK1-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]]
+// TCHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]]
+// TCHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
+// TCHECK1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// TCHECK1-NEXT: store i64 1, i64* [[X]], align 8
+// TCHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// TCHECK1-NEXT: store i8 1, i8* [[Y]], align 8
+// TCHECK1-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// TCHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// TCHECK1-NEXT: ret void
+//
+//
+// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// TCHECK1-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
+// TCHECK1-NEXT: entry:
+// TCHECK1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// TCHECK1-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 8
+// TCHECK1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// TCHECK1-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 8
+// TCHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0
+// TCHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4
+// TCHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
+// TCHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i64 0
+// TCHECK1-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 8
+// TCHECK1-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// TCHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i64 0
+// TCHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 8
+// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00
+// TCHECK1-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 8
+// TCHECK1-NEXT: ret void
+//
+//
+// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// TCHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK1-NEXT: entry:
+// TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// TCHECK1-NEXT: [[B2:%.*]] = alloca [10 x i32], align 4
+// TCHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
+// TCHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// TCHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
+// TCHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B2]] to i8*
+// TCHECK1-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// TCHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// TCHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 1
+// TCHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP4]] to i32
+// TCHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
+// TCHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
+// TCHECK1-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1
+// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2
+// TCHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK1-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
+// TCHECK1-NEXT: ret void
+//
+//
+// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// TCHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
+// TCHECK1-NEXT: entry:
+// TCHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
+// TCHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// TCHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// TCHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
+// TCHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
+// TCHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
+// TCHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// TCHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
+// TCHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
+// TCHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// TCHECK1-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 8
+// TCHECK1-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// TCHECK1-NEXT: [[VLA3:%.*]] = alloca i16, i64 [[TMP5]], align 2
+// TCHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// TCHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR1]], align 8
+// TCHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP1]], [[TMP2]]
+// TCHECK1-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 2
+// TCHECK1-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// TCHECK1-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i64 [[TMP7]], i1 false)
+// TCHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP10]] to double
+// TCHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
+// TCHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
+// TCHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[A5]], align 8
+// TCHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// TCHECK1-NEXT: store double [[INC]], double* [[A5]], align 8
+// TCHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
+// TCHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP2]]
+// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i64 [[TMP12]]
+// TCHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// TCHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
+// TCHECK1-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// TCHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// TCHECK1-NEXT: ret void
+//
+//
+// TCHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// TCHECK1-SAME: (i64 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK1-NEXT: entry:
+// TCHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// TCHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
+// TCHECK1-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
+// TCHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
+// TCHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
+// TCHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
+// TCHECK1-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK1-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i64 40, i1 false)
+// TCHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4
+// TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
+// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2
+// TCHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK1-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// TCHECK1-NEXT: ret void
+//
+//
+// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// TCHECK2-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {
+// TCHECK2-NEXT: entry:
+// TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4
+// TCHECK2-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK2-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4
+// TCHECK2-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4
+// TCHECK2-NEXT: ret void
+//
+//
+// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// TCHECK2-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
+// TCHECK2-NEXT: entry:
+// TCHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
+// TCHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
+// TCHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
+// TCHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
+// TCHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
+// TCHECK2-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// TCHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// TCHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// TCHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// TCHECK2-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
+// TCHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
+// TCHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// TCHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
+// TCHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
+// TCHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// TCHECK2-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
+// TCHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
+// TCHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
+// TCHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
+// TCHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
+// TCHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// TCHECK2-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)
+// TCHECK2-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// TCHECK2-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4
+// TCHECK2-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
+// TCHECK2-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// TCHECK2-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4
+// TCHECK2-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// TCHECK2-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)
+// TCHECK2-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// TCHECK2-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)
+// TCHECK2-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// TCHECK2-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8
+// TCHECK2-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4
+// TCHECK2-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4
+// TCHECK2-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// TCHECK2-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
+// TCHECK2-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// TCHECK2-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)
+// TCHECK2-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// TCHECK2-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)
+// TCHECK2-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// TCHECK2-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// TCHECK2-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// TCHECK2-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2
+// TCHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// TCHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3
+// TCHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// TCHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1
+// TCHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
+// TCHECK2-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// TCHECK2-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]
+// TCHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]
+// TCHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3
+// TCHECK2-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// TCHECK2-NEXT: store i64 1, i64* [[X]], align 4
+// TCHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// TCHECK2-NEXT: store i8 1, i8* [[Y]], align 4
+// TCHECK2-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// TCHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// TCHECK2-NEXT: ret void
+//
+//
+// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// TCHECK2-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
+// TCHECK2-NEXT: entry:
+// TCHECK2-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// TCHECK2-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4
+// TCHECK2-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// TCHECK2-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4
+// TCHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0
+// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4
+// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
+// TCHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 0
+// TCHECK2-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4
+// TCHECK2-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// TCHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i32 0
+// TCHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 4
+// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00
+// TCHECK2-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 4
+// TCHECK2-NEXT: ret void
+//
+//
+// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// TCHECK2-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK2-NEXT: entry:
+// TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// TCHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK2-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
+// TCHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// TCHECK2-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
+// TCHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK2-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// TCHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
+// TCHECK2-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32
+// TCHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
+// TCHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
+// TCHECK2-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1
+// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// TCHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
+// TCHECK2-NEXT: ret void
+//
+//
+// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// TCHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
+// TCHECK2-NEXT: entry:
+// TCHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
+// TCHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// TCHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// TCHECK2-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
+// TCHECK2-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// TCHECK2-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// TCHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// TCHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// TCHECK2-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4
+// TCHECK2-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// TCHECK2-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
+// TCHECK2-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// TCHECK2-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// TCHECK2-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// TCHECK2-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// TCHECK2-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// TCHECK2-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)
+// TCHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// TCHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
+// TCHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
+// TCHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK2-NEXT: store double [[ADD]], double* [[A]], align 4
+// TCHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK2-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4
+// TCHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// TCHECK2-NEXT: store double [[INC]], double* [[A4]], align 4
+// TCHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
+// TCHECK2-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
+// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]
+// TCHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// TCHECK2-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
+// TCHECK2-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// TCHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// TCHECK2-NEXT: ret void
+//
+//
+// TCHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// TCHECK2-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK2-NEXT: entry:
+// TCHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// TCHECK2-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// TCHECK2-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK2-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// TCHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// TCHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK2-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// TCHECK2-NEXT: ret void
+//
+//
+// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l63
+// TCHECK3-SAME: (i32 noundef [[A:%.*]], i32* noundef [[P:%.*]], i32 noundef [[GA:%.*]]) #[[ATTR0:[0-9]+]] {
+// TCHECK3-NEXT: entry:
+// TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[P_ADDR:%.*]] = alloca i32*, align 4
+// TCHECK3-NEXT: [[GA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK3-NEXT: store i32* [[P]], i32** [[P_ADDR]], align 4
+// TCHECK3-NEXT: store i32 [[GA]], i32* [[GA_ADDR]], align 4
+// TCHECK3-NEXT: ret void
+//
+//
+// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l70
+// TCHECK3-SAME: (i32 noundef [[AA:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
+// TCHECK3-NEXT: entry:
+// TCHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
+// TCHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
+// TCHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
+// TCHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
+// TCHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
+// TCHECK3-NEXT: [[B5:%.*]] = alloca [10 x float], align 4
+// TCHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// TCHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[C7:%.*]] = alloca [5 x [10 x double]], align 8
+// TCHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[__VLA_EXPR2:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[D9:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// TCHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
+// TCHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
+// TCHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// TCHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
+// TCHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
+// TCHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// TCHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
+// TCHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
+// TCHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
+// TCHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
+// TCHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
+// TCHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP8:%.*]] = bitcast [10 x float]* [[B5]] to i8*
+// TCHECK3-NEXT: [[TMP9:%.*]] = bitcast [10 x float]* [[TMP0]] to i8*
+// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 40, i1 false)
+// TCHECK3-NEXT: [[TMP10:%.*]] = call i8* @llvm.stacksave()
+// TCHECK3-NEXT: store i8* [[TMP10]], i8** [[SAVED_STACK]], align 4
+// TCHECK3-NEXT: [[VLA6:%.*]] = alloca float, i32 [[TMP1]], align 4
+// TCHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// TCHECK3-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP1]], 4
+// TCHECK3-NEXT: [[TMP12:%.*]] = bitcast float* [[VLA6]] to i8*
+// TCHECK3-NEXT: [[TMP13:%.*]] = bitcast float* [[TMP2]] to i8*
+// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP12]], i8* align 4 [[TMP13]], i32 [[TMP11]], i1 false)
+// TCHECK3-NEXT: [[TMP14:%.*]] = bitcast [5 x [10 x double]]* [[C7]] to i8*
+// TCHECK3-NEXT: [[TMP15:%.*]] = bitcast [5 x [10 x double]]* [[TMP3]] to i8*
+// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP14]], i8* align 8 [[TMP15]], i32 400, i1 false)
+// TCHECK3-NEXT: [[TMP16:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// TCHECK3-NEXT: [[VLA8:%.*]] = alloca double, i32 [[TMP16]], align 8
+// TCHECK3-NEXT: store i32 [[TMP4]], i32* [[__VLA_EXPR1]], align 4
+// TCHECK3-NEXT: store i32 [[TMP5]], i32* [[__VLA_EXPR2]], align 4
+// TCHECK3-NEXT: [[TMP17:%.*]] = mul nuw i32 [[TMP4]], [[TMP5]]
+// TCHECK3-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
+// TCHECK3-NEXT: [[TMP19:%.*]] = bitcast double* [[VLA8]] to i8*
+// TCHECK3-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP6]] to i8*
+// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 [[TMP19]], i8* align 8 [[TMP20]], i32 [[TMP18]], i1 false)
+// TCHECK3-NEXT: [[TMP21:%.*]] = bitcast %struct.TT* [[D9]] to i8*
+// TCHECK3-NEXT: [[TMP22:%.*]] = bitcast %struct.TT* [[TMP7]] to i8*
+// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP21]], i8* align 4 [[TMP22]], i32 12, i1 false)
+// TCHECK3-NEXT: [[TMP23:%.*]] = load i16, i16* [[CONV]], align 2
+// TCHECK3-NEXT: [[CONV10:%.*]] = sext i16 [[TMP23]] to i32
+// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1
+// TCHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16
+// TCHECK3-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2
+// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2
+// TCHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// TCHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3
+// TCHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4
+// TCHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1
+// TCHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2
+// TCHECK3-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8
+// TCHECK3-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]]
+// TCHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]]
+// TCHECK3-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i32 3
+// TCHECK3-NEXT: store double 1.000000e+00, double* [[ARRAYIDX16]], align 8
+// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 0
+// TCHECK3-NEXT: store i64 1, i64* [[X]], align 4
+// TCHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D9]], i32 0, i32 1
+// TCHECK3-NEXT: store i8 1, i8* [[Y]], align 4
+// TCHECK3-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// TCHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP25]])
+// TCHECK3-NEXT: ret void
+//
+//
+// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooiPd_l111
+// TCHECK3-SAME: (double* noundef [[PTR:%.*]], %struct.TT.0* noundef nonnull align 4 dereferenceable(8) [[E:%.*]]) #[[ATTR0]] {
+// TCHECK3-NEXT: entry:
+// TCHECK3-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// TCHECK3-NEXT: [[E_ADDR:%.*]] = alloca %struct.TT.0*, align 4
+// TCHECK3-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// TCHECK3-NEXT: store %struct.TT.0* [[E]], %struct.TT.0** [[E_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP0:%.*]] = load %struct.TT.0*, %struct.TT.0** [[E_ADDR]], align 4
+// TCHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0:%.*]], %struct.TT.0* [[TMP0]], i32 0, i32 0
+// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4
+// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
+// TCHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[TMP2]], i32 0
+// TCHECK3-NEXT: store double [[CONV]], double* [[ARRAYIDX]], align 4
+// TCHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// TCHECK3-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[TMP3]], i32 0
+// TCHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[ARRAYIDX1]], align 4
+// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00
+// TCHECK3-NEXT: store double [[INC]], double* [[ARRAYIDX1]], align 4
+// TCHECK3-NEXT: ret void
+//
+//
+// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l142
+// TCHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK3-NEXT: entry:
+// TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// TCHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
+// TCHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// TCHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
+// TCHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK3-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// TCHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1
+// TCHECK3-NEXT: [[CONV2:%.*]] = sext i8 [[TMP4]] to i32
+// TCHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
+// TCHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8
+// TCHECK3-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1
+// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// TCHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1
+// TCHECK3-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
+// TCHECK3-NEXT: ret void
+//
+//
+// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l167
+// TCHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
+// TCHECK3-NEXT: entry:
+// TCHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
+// TCHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// TCHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// TCHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
+// TCHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
+// TCHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
+// TCHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
+// TCHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave()
+// TCHECK3-NEXT: store i8* [[TMP4]], i8** [[SAVED_STACK]], align 4
+// TCHECK3-NEXT: [[TMP5:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// TCHECK3-NEXT: [[VLA3:%.*]] = alloca i16, i32 [[TMP5]], align 2
+// TCHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// TCHECK3-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// TCHECK3-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]]
+// TCHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP6]], 2
+// TCHECK3-NEXT: [[TMP8:%.*]] = bitcast i16* [[VLA3]] to i8*
+// TCHECK3-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP3]] to i8*
+// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP8]], i8* align 2 [[TMP9]], i32 [[TMP7]], i1 false)
+// TCHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[B_ADDR]], align 4
+// TCHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
+// TCHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
+// TCHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK3-NEXT: store double [[ADD]], double* [[A]], align 4
+// TCHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
+// TCHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4
+// TCHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// TCHECK3-NEXT: store double [[INC]], double* [[A4]], align 4
+// TCHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
+// TCHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
+// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA3]], i32 [[TMP12]]
+// TCHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// TCHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
+// TCHECK3-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// TCHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// TCHECK3-NEXT: ret void
+//
+//
+// TCHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l128
+// TCHECK3-SAME: (i32 noundef [[A:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
+// TCHECK3-NEXT: entry:
+// TCHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// TCHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
+// TCHECK3-NEXT: [[B1:%.*]] = alloca [10 x i32], align 4
+// TCHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
+// TCHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
+// TCHECK3-NEXT: [[TMP1:%.*]] = bitcast [10 x i32]* [[B1]] to i8*
+// TCHECK3-NEXT: [[TMP2:%.*]] = bitcast [10 x i32]* [[TMP0]] to i8*
+// TCHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP1]], i8* align 4 [[TMP2]], i32 40, i1 false)
+// TCHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// TCHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
+// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2
+// TCHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// TCHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1
+// TCHECK3-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4
+// TCHECK3-NEXT: ret void
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z3fooiPd
+// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[AA:%.*]] = alloca i16, align 2
+// SIMD-ONLY1-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// SIMD-ONLY1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// SIMD-ONLY1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// SIMD-ONLY1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// SIMD-ONLY1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// SIMD-ONLY1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// SIMD-ONLY1-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// SIMD-ONLY1-NEXT: [[P:%.*]] = alloca i32*, align 64
+// SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: store i16 0, i16* [[AA]], align 2
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY1-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
+// SIMD-ONLY1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
+// SIMD-ONLY1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
+// SIMD-ONLY1-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// SIMD-ONLY1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: store i32 [[TMP6]], i32* [[X]], align 4
+// SIMD-ONLY1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4
+// SIMD-ONLY1-NEXT: store i32* [[A]], i32** [[P]], align 64
+// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i16, i16* [[AA]], align 2
+// SIMD-ONLY1-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
+// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
+// SIMD-ONLY1-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2
+// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
+// SIMD-ONLY1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// SIMD-ONLY1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
+// SIMD-ONLY1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4
+// SIMD-ONLY1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
+// SIMD-ONLY1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2
+// SIMD-ONLY1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8
+// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]]
+// SIMD-ONLY1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]]
+// SIMD-ONLY1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i64 3
+// SIMD-ONLY1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8
+// SIMD-ONLY1-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: store i64 1, i64* [[X8]], align 8
+// SIMD-ONLY1-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
+// SIMD-ONLY1-NEXT: store i8 1, i8* [[Y9]], align 8
+// SIMD-ONLY1-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, i32* [[X10]], align 4
+// SIMD-ONLY1-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double
+// SIMD-ONLY1-NEXT: [[TMP11:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP11]], i64 0
+// SIMD-ONLY1-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 8
+// SIMD-ONLY1-NEXT: [[TMP12:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP12]], i64 0
+// SIMD-ONLY1-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX13]], align 8
+// SIMD-ONLY1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
+// SIMD-ONLY1-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 8
+// SIMD-ONLY1-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY1-NEXT: call void @llvm.stackrestore(i8* [[TMP15]])
+// SIMD-ONLY1-NEXT: ret i32 [[TMP14]]
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z3bariPd
+// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
+// SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])
+// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// SIMD-ONLY1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])
+// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// SIMD-ONLY1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])
+// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// SIMD-ONLY1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: ret i32 [[TMP9]]
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// SIMD-ONLY1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[B:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// SIMD-ONLY1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// SIMD-ONLY1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
+// SIMD-ONLY1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
+// SIMD-ONLY1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
+// SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
+// SIMD-ONLY1-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
+// SIMD-ONLY1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: store double [[ADD2]], double* [[A]], align 8
+// SIMD-ONLY1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY1-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8
+// SIMD-ONLY1-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// SIMD-ONLY1-NEXT: store double [[INC]], double* [[A3]], align 8
+// SIMD-ONLY1-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
+// SIMD-ONLY1-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
+// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
+// SIMD-ONLY1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// SIMD-ONLY1-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
+// SIMD-ONLY1-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
+// SIMD-ONLY1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
+// SIMD-ONLY1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
+// SIMD-ONLY1-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
+// SIMD-ONLY1-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
+// SIMD-ONLY1-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY1-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
+// SIMD-ONLY1-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY1-NEXT: call void @llvm.stackrestore(i8* [[TMP11]])
+// SIMD-ONLY1-NEXT: ret i32 [[ADD9]]
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZL7fstatici
+// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// SIMD-ONLY1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: store i8 0, i8* [[AAA]], align 1
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1
+// SIMD-ONLY1-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
+// SIMD-ONLY1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8
+// SIMD-ONLY1-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1
+// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
+// SIMD-ONLY1-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: ret i32 [[TMP3]]
+//
+//
+// SIMD-ONLY1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// SIMD-ONLY1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY1-NEXT: entry:
+// SIMD-ONLY1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY1-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
+// SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY1-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1
+// SIMD-ONLY1-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY1-NEXT: ret i32 [[TMP2]]
+//
+//
+// SIMD-ONLY11-LABEL: define {{[^@]+}}@_Z3fooiPd
+// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY11-NEXT: entry:
+// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY11-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY11-NEXT: [[AA:%.*]] = alloca i16, align 2
+// SIMD-ONLY11-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// SIMD-ONLY11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// SIMD-ONLY11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// SIMD-ONLY11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// SIMD-ONLY11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
+// SIMD-ONLY11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
+// SIMD-ONLY11-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// SIMD-ONLY11-NEXT: [[P:%.*]] = alloca i32*, align 64
+// SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// SIMD-ONLY11-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: store i16 0, i16* [[AA]], align 2
+// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY11-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
+// SIMD-ONLY11-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
+// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
+// SIMD-ONLY11-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
+// SIMD-ONLY11-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
+// SIMD-ONLY11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: store i32 [[TMP6]], i32* [[X]], align 4
+// SIMD-ONLY11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// SIMD-ONLY11-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: store i32 [[TMP7]], i32* [[Y]], align 4
+// SIMD-ONLY11-NEXT: store i32* [[A]], i32** [[P]], align 64
+// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = load i16, i16* [[AA]], align 2
+// SIMD-ONLY11-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
+// SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
+// SIMD-ONLY11-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2
+// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
+// SIMD-ONLY11-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// SIMD-ONLY11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
+// SIMD-ONLY11-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4
+// SIMD-ONLY11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
+// SIMD-ONLY11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2
+// SIMD-ONLY11-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8
+// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]]
+// SIMD-ONLY11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]]
+// SIMD-ONLY11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i64 3
+// SIMD-ONLY11-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8
+// SIMD-ONLY11-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
+// SIMD-ONLY11-NEXT: store i64 1, i64* [[X8]], align 8
+// SIMD-ONLY11-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
+// SIMD-ONLY11-NEXT: store i8 1, i8* [[Y9]], align 8
+// SIMD-ONLY11-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY11-NEXT: [[TMP10:%.*]] = load i32, i32* [[X10]], align 4
+// SIMD-ONLY11-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP10]] to double
+// SIMD-ONLY11-NEXT: [[TMP11:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP11]], i64 0
+// SIMD-ONLY11-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 8
+// SIMD-ONLY11-NEXT: [[TMP12:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY11-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP12]], i64 0
+// SIMD-ONLY11-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX13]], align 8
+// SIMD-ONLY11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
+// SIMD-ONLY11-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 8
+// SIMD-ONLY11-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY11-NEXT: call void @llvm.stackrestore(i8* [[TMP15]])
+// SIMD-ONLY11-NEXT: ret i32 [[TMP14]]
+//
+//
+// SIMD-ONLY11-LABEL: define {{[^@]+}}@_Z3bariPd
+// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY11-NEXT: entry:
+// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY11-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 8
+// SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
+// SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 8
+// SIMD-ONLY11-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 8
+// SIMD-ONLY11-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooiPd(i32 noundef signext [[TMP0]], double* noundef [[TMP1]])
+// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// SIMD-ONLY11-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP3]])
+// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// SIMD-ONLY11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP5]])
+// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// SIMD-ONLY11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP7]])
+// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// SIMD-ONLY11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: ret i32 [[TMP9]]
+//
+//
+// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// SIMD-ONLY11-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY11-NEXT: entry:
+// SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
+// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY11-NEXT: [[B:%.*]] = alloca i32, align 4
+// SIMD-ONLY11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
+// SIMD-ONLY11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
+// SIMD-ONLY11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
+// SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
+// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY11-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY11-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
+// SIMD-ONLY11-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
+// SIMD-ONLY11-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
+// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
+// SIMD-ONLY11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
+// SIMD-ONLY11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY11-NEXT: store double [[ADD2]], double* [[A]], align 8
+// SIMD-ONLY11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY11-NEXT: [[TMP6:%.*]] = load double, double* [[A3]], align 8
+// SIMD-ONLY11-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
+// SIMD-ONLY11-NEXT: store double [[INC]], double* [[A3]], align 8
+// SIMD-ONLY11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
+// SIMD-ONLY11-NEXT: [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
+// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
+// SIMD-ONLY11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
+// SIMD-ONLY11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
+// SIMD-ONLY11-NEXT: [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
+// SIMD-ONLY11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
+// SIMD-ONLY11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
+// SIMD-ONLY11-NEXT: [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
+// SIMD-ONLY11-NEXT: [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
+// SIMD-ONLY11-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY11-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
+// SIMD-ONLY11-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
+// SIMD-ONLY11-NEXT: call void @llvm.stackrestore(i8* [[TMP11]])
+// SIMD-ONLY11-NEXT: ret i32 [[ADD9]]
+//
+//
+// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZL7fstatici
+// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY11-NEXT: entry:
+// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY11-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// SIMD-ONLY11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: store i8 0, i8* [[AAA]], align 1
+// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY11-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1
+// SIMD-ONLY11-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
+// SIMD-ONLY11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8
+// SIMD-ONLY11-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1
+// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
+// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
+// SIMD-ONLY11-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: ret i32 [[TMP3]]
+//
+//
+// SIMD-ONLY11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// SIMD-ONLY11-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY11-NEXT: entry:
+// SIMD-ONLY11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY11-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY11-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY11-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
+// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1
+// SIMD-ONLY11-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY11-NEXT: ret i32 [[TMP2]]
+//
+//
+// SIMD-ONLY12-LABEL: define {{[^@]+}}@_Z3fooiPd
+// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY12-NEXT: entry:
+// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[AA:%.*]] = alloca i16, align 2
+// SIMD-ONLY12-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// SIMD-ONLY12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// SIMD-ONLY12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// SIMD-ONLY12-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// SIMD-ONLY12-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// SIMD-ONLY12-NEXT: [[P:%.*]] = alloca i32*, align 64
+// SIMD-ONLY12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: store i16 0, i16* [[AA]], align 2
+// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY12-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY12-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
+// SIMD-ONLY12-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
+// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
+// SIMD-ONLY12-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
+// SIMD-ONLY12-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// SIMD-ONLY12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store i32 [[TMP4]], i32* [[X]], align 4
+// SIMD-ONLY12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4
+// SIMD-ONLY12-NEXT: store i32* [[A]], i32** [[P]], align 64
+// SIMD-ONLY12-NEXT: [[TMP6:%.*]] = load i16, i16* [[AA]], align 2
+// SIMD-ONLY12-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i32
+// SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
+// SIMD-ONLY12-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2
+// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
+// SIMD-ONLY12-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// SIMD-ONLY12-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
+// SIMD-ONLY12-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4
+// SIMD-ONLY12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
+// SIMD-ONLY12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2
+// SIMD-ONLY12-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8
+// SIMD-ONLY12-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]
+// SIMD-ONLY12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]]
+// SIMD-ONLY12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i32 3
+// SIMD-ONLY12-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8
+// SIMD-ONLY12-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
+// SIMD-ONLY12-NEXT: store i64 1, i64* [[X8]], align 4
+// SIMD-ONLY12-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
+// SIMD-ONLY12-NEXT: store i8 1, i8* [[Y9]], align 4
+// SIMD-ONLY12-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i32, i32* [[X10]], align 4
+// SIMD-ONLY12-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double
+// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP9]], i32 0
+// SIMD-ONLY12-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 4
+// SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP10]], i32 0
+// SIMD-ONLY12-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 4
+// SIMD-ONLY12-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// SIMD-ONLY12-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 4
+// SIMD-ONLY12-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY12-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// SIMD-ONLY12-NEXT: ret i32 [[TMP12]]
+//
+//
+// SIMD-ONLY12-LABEL: define {{[^@]+}}@_Z3bariPd
+// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY12-NEXT: entry:
+// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
+// SIMD-ONLY12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])
+// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// SIMD-ONLY12-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])
+// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// SIMD-ONLY12-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])
+// SIMD-ONLY12-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// SIMD-ONLY12-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])
+// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// SIMD-ONLY12-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: ret i32 [[TMP9]]
+//
+//
+// SIMD-ONLY12-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// SIMD-ONLY12-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY12-NEXT: entry:
+// SIMD-ONLY12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[B:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// SIMD-ONLY12-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY12-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY12-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
+// SIMD-ONLY12-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
+// SIMD-ONLY12-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
+// SIMD-ONLY12-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
+// SIMD-ONLY12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY12-NEXT: store double [[ADD2]], double* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
+// SIMD-ONLY12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
+// SIMD-ONLY12-NEXT: store double [[INC]], double* [[A3]], align 4
+// SIMD-ONLY12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
+// SIMD-ONLY12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
+// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
+// SIMD-ONLY12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// SIMD-ONLY12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
+// SIMD-ONLY12-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
+// SIMD-ONLY12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
+// SIMD-ONLY12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
+// SIMD-ONLY12-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
+// SIMD-ONLY12-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
+// SIMD-ONLY12-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY12-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
+// SIMD-ONLY12-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY12-NEXT: call void @llvm.stackrestore(i8* [[TMP10]])
+// SIMD-ONLY12-NEXT: ret i32 [[ADD9]]
+//
+//
+// SIMD-ONLY12-LABEL: define {{[^@]+}}@_ZL7fstatici
+// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY12-NEXT: entry:
+// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// SIMD-ONLY12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: store i8 0, i8* [[AAA]], align 1
+// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY12-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1
+// SIMD-ONLY12-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
+// SIMD-ONLY12-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8
+// SIMD-ONLY12-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1
+// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
+// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
+// SIMD-ONLY12-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: ret i32 [[TMP3]]
+//
+//
+// SIMD-ONLY12-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// SIMD-ONLY12-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY12-NEXT: entry:
+// SIMD-ONLY12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY12-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY12-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
+// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY12-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1
+// SIMD-ONLY12-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY12-NEXT: ret i32 [[TMP2]]
+//
+//
+// SIMD-ONLY13-LABEL: define {{[^@]+}}@_Z3fooiPd
+// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY13-NEXT: entry:
+// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[AA:%.*]] = alloca i16, align 2
+// SIMD-ONLY13-NEXT: [[B:%.*]] = alloca [10 x float], align 4
+// SIMD-ONLY13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// SIMD-ONLY13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
+// SIMD-ONLY13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
+// SIMD-ONLY13-NEXT: [[E:%.*]] = alloca [[STRUCT_TT_0:%.*]], align 4
+// SIMD-ONLY13-NEXT: [[P:%.*]] = alloca i32*, align 64
+// SIMD-ONLY13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: store i16 0, i16* [[AA]], align 2
+// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY13-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY13-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
+// SIMD-ONLY13-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
+// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
+// SIMD-ONLY13-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
+// SIMD-ONLY13-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
+// SIMD-ONLY13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store i32 [[TMP4]], i32* [[X]], align 4
+// SIMD-ONLY13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 1
+// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store i32 [[TMP5]], i32* [[Y]], align 4
+// SIMD-ONLY13-NEXT: store i32* [[A]], i32** [[P]], align 64
+// SIMD-ONLY13-NEXT: [[TMP6:%.*]] = load i16, i16* [[AA]], align 2
+// SIMD-ONLY13-NEXT: [[CONV:%.*]] = sext i16 [[TMP6]] to i32
+// SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
+// SIMD-ONLY13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2
+// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
+// SIMD-ONLY13-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4
+// SIMD-ONLY13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
+// SIMD-ONLY13-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4
+// SIMD-ONLY13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
+// SIMD-ONLY13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2
+// SIMD-ONLY13-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8
+// SIMD-ONLY13-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]]
+// SIMD-ONLY13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]]
+// SIMD-ONLY13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX6]], i32 3
+// SIMD-ONLY13-NEXT: store double 1.000000e+00, double* [[ARRAYIDX7]], align 8
+// SIMD-ONLY13-NEXT: [[X8:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
+// SIMD-ONLY13-NEXT: store i64 1, i64* [[X8]], align 4
+// SIMD-ONLY13-NEXT: [[Y9:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
+// SIMD-ONLY13-NEXT: store i8 1, i8* [[Y9]], align 4
+// SIMD-ONLY13-NEXT: [[X10:%.*]] = getelementptr inbounds [[STRUCT_TT_0]], %struct.TT.0* [[E]], i32 0, i32 0
+// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i32, i32* [[X10]], align 4
+// SIMD-ONLY13-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP8]] to double
+// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds double, double* [[TMP9]], i32 0
+// SIMD-ONLY13-NEXT: store double [[CONV11]], double* [[ARRAYIDX12]], align 4
+// SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, double* [[TMP10]], i32 0
+// SIMD-ONLY13-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 4
+// SIMD-ONLY13-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
+// SIMD-ONLY13-NEXT: store double [[INC]], double* [[ARRAYIDX13]], align 4
+// SIMD-ONLY13-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY13-NEXT: call void @llvm.stackrestore(i8* [[TMP13]])
+// SIMD-ONLY13-NEXT: ret i32 [[TMP12]]
+//
+//
+// SIMD-ONLY13-LABEL: define {{[^@]+}}@_Z3bariPd
+// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]], double* noundef [[PTR:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY13-NEXT: entry:
+// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[PTR_ADDR:%.*]] = alloca double*, align 4
+// SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
+// SIMD-ONLY13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store double* [[PTR]], double** [[PTR_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load double*, double** [[PTR_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooiPd(i32 noundef [[TMP0]], double* noundef [[TMP1]])
+// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CALL]]
+// SIMD-ONLY13-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP3]])
+// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], [[CALL1]]
+// SIMD-ONLY13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP5]])
+// SIMD-ONLY13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], [[CALL3]]
+// SIMD-ONLY13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP7]])
+// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP8]], [[CALL5]]
+// SIMD-ONLY13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: ret i32 [[TMP9]]
+//
+//
+// SIMD-ONLY13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
+// SIMD-ONLY13-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY13-NEXT: entry:
+// SIMD-ONLY13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
+// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[B:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
+// SIMD-ONLY13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY13-NEXT: store i32 [[ADD]], i32* [[B]], align 4
+// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
+// SIMD-ONLY13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
+// SIMD-ONLY13-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
+// SIMD-ONLY13-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
+// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
+// SIMD-ONLY13-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
+// SIMD-ONLY13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY13-NEXT: store double [[ADD2]], double* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
+// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4
+// SIMD-ONLY13-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
+// SIMD-ONLY13-NEXT: store double [[INC]], double* [[A3]], align 4
+// SIMD-ONLY13-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16
+// SIMD-ONLY13-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
+// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
+// SIMD-ONLY13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
+// SIMD-ONLY13-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
+// SIMD-ONLY13-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
+// SIMD-ONLY13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
+// SIMD-ONLY13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
+// SIMD-ONLY13-NEXT: [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
+// SIMD-ONLY13-NEXT: [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
+// SIMD-ONLY13-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4
+// SIMD-ONLY13-NEXT: [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
+// SIMD-ONLY13-NEXT: [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
+// SIMD-ONLY13-NEXT: call void @llvm.stackrestore(i8* [[TMP10]])
+// SIMD-ONLY13-NEXT: ret i32 [[ADD9]]
+//
+//
+// SIMD-ONLY13-LABEL: define {{[^@]+}}@_ZL7fstatici
+// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// SIMD-ONLY13-NEXT: entry:
+// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[AAA:%.*]] = alloca i8, align 1
+// SIMD-ONLY13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: store i8 0, i8* [[AAA]], align 1
+// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY13-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i8, i8* [[AAA]], align 1
+// SIMD-ONLY13-NEXT: [[CONV:%.*]] = sext i8 [[TMP1]] to i32
+// SIMD-ONLY13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
+// SIMD-ONLY13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8
+// SIMD-ONLY13-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1
+// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
+// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
+// SIMD-ONLY13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: ret i32 [[TMP3]]
+//
+//
+// SIMD-ONLY13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
+// SIMD-ONLY13-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY13-NEXT: entry:
+// SIMD-ONLY13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[A:%.*]] = alloca i32, align 4
+// SIMD-ONLY13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
+// SIMD-ONLY13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store i32 0, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
+// SIMD-ONLY13-NEXT: store i32 [[ADD]], i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
+// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1
+// SIMD-ONLY13-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4
+// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4
+// SIMD-ONLY13-NEXT: ret i32 [[TMP2]]
+//
diff --git a/clang/test/OpenMP/target_is_device_ptr_codegen.cpp b/clang/test/OpenMP/target_is_device_ptr_codegen.cpp
index b010d0dcea192..09c4d568bb096 100644
--- a/clang/test/OpenMP/target_is_device_ptr_codegen.cpp
+++ b/clang/test/OpenMP/target_is_device_ptr_codegen.cpp
@@ -1,193 +1,76 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
// expected-no-diagnostics
#ifndef HEADER
#define HEADER
///==========================================================================///
-// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64
+// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK10
// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-64
-// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32
+// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK11
+// RUN: %clang_cc1 -DCK1 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK12
// RUN: %clang_cc1 -DCK1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK1 --check-prefix CK1-32
+// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK13
-// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
+// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY00 %s
// RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
+// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY01 %s
+// RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY02 %s
// RUN: %clang_cc1 -DCK1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
-// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}
+// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY03 %s
#ifdef CK1
double *g;
-// CK1: @g ={{.*}} global ptr
-// CK1: [[SIZES00:@.+]] = {{.+}}constant [1 x i[[sz:64|32]]] [i{{64|32}} {{8|4}}]
-// CK1: [[TYPES00:@.+]] = {{.+}}constant [1 x i64] [i64 288]
-// CK1: [[SIZES01:@.+]] = {{.+}}constant [1 x i[[sz]]] [i[[sz]] {{8|4}}]
-// CK1: [[TYPES01:@.+]] = {{.+}}constant [1 x i64] [i64 288]
-// CK1: [[SIZES02:@.+]] = {{.+}}constant [1 x i[[sz]]] [i[[sz]] {{8|4}}]
-// CK1: [[TYPES02:@.+]] = {{.+}}constant [1 x i64] [i64 288]
-// CK1: [[SIZES03:@.+]] = {{.+}}constant [1 x i[[sz]]] [i[[sz]] {{8|4}}]
-// CK1: [[TYPES03:@.+]] = {{.+}}constant [1 x i64] [i64 288]
-// CK1: [[SIZES04:@.+]] = {{.+}}constant [1 x i[[sz]]] [i[[sz]] {{8|4}}]
-// CK1: [[TYPES04:@.+]] = {{.+}}constant [1 x i64] [i64 288]
-// CK1: [[SIZES05:@.+]] = {{.+}}constant [1 x i[[sz]]] [i[[sz]] {{8|4}}]
-// CK1: [[TYPES05:@.+]] = {{.+}}constant [1 x i64] [i64 288]
-// CK1: [[SIZES06:@.+]] = {{.+}}constant [2 x i[[sz]]] [i[[sz]] {{8|4}}, i[[sz]] {{8|4}}]
-// CK1: [[TYPES06:@.+]] = {{.+}}constant [2 x i64] [i64 288, i64 288]
-// CK1-LABEL: @_Z3foo{{.*}}(
template<typename T>
void foo(float *&lr, T *&tr) {
float *l;
T *t;
-// CK1-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:.+]], i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
-// CK1-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
-// CK1-DAG: store ptr [[BPGEP:%.+]], ptr [[BPARG]]
-// CK1-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
-// CK1-DAG: store ptr [[PGEP:%.+]], ptr [[PARG]]
-// CK1-DAG: [[BPGEP]] = getelementptr inbounds {{.+}}[[BPS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[PGEP]] = getelementptr inbounds {{.+}}[[PS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[BP1:%.+]] = getelementptr inbounds {{.+}}[[BPS]], i32 0, i32 0
-// CK1-DAG: [[P1:%.+]] = getelementptr inbounds {{.+}}[[PS]], i32 0, i32 0
-// CK1-DAG: store ptr [[VAL:%.+]], ptr [[BP1]]
-// CK1-DAG: store ptr [[VAL]], ptr [[P1]]
-// CK1-DAG: [[VAL]] = load ptr, ptr [[ADDR:@g]],
-
-// CK1: call void [[KERNEL:@.+]](ptr [[VAL]])
+
#pragma omp target is_device_ptr(g)
{
++g;
}
-// CK1-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:.+]], i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
-// CK1-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
-// CK1-DAG: store ptr [[BPGEP:%.+]], ptr [[BPARG]]
-// CK1-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
-// CK1-DAG: store ptr [[PGEP:%.+]], ptr [[PARG]]
-// CK1-DAG: [[BPGEP]] = getelementptr inbounds {{.+}}[[BPS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[PGEP]] = getelementptr inbounds {{.+}}[[PS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[BP1:%.+]] = getelementptr inbounds {{.+}}[[BPS]], i32 0, i32 0
-// CK1-DAG: [[P1:%.+]] = getelementptr inbounds {{.+}}[[PS]], i32 0, i32 0
-// CK1-DAG: store ptr [[VAL:%.+]], ptr [[BP1]]
-// CK1-DAG: store ptr [[VAL]], ptr [[P1]]
-// CK1-DAG: [[VAL]] = load ptr, ptr [[ADDR:%.+]],
-
-// CK1: call void [[KERNEL:@.+]](ptr [[VAL]])
+
#pragma omp target is_device_ptr(l)
{
++l;
}
-// CK1-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:.+]], i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
-// CK1-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
-// CK1-DAG: store ptr [[BPGEP:%.+]], ptr [[BPARG]]
-// CK1-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
-// CK1-DAG: store ptr [[PGEP:%.+]], ptr [[PARG]]
-// CK1-DAG: [[BPGEP]] = getelementptr inbounds {{.+}}[[BPS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[PGEP]] = getelementptr inbounds {{.+}}[[PS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[BP1:%.+]] = getelementptr inbounds {{.+}}[[BPS]], i32 0, i32 0
-// CK1-DAG: [[P1:%.+]] = getelementptr inbounds {{.+}}[[PS]], i32 0, i32 0
-// CK1-DAG: store ptr [[VAL:%.+]], ptr [[BP1]]
-// CK1-DAG: store ptr [[VAL]], ptr [[P1]]
-// CK1-DAG: [[VAL]] = load ptr, ptr [[ADDR:%.+]],
-
-// CK1: call void [[KERNEL:@.+]](ptr [[VAL]])
+
#pragma omp target is_device_ptr(t)
{
++t;
}
-// CK1-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:.+]], i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
-// CK1-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
-// CK1-DAG: store ptr [[BPGEP:%.+]], ptr [[BPARG]]
-// CK1-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
-// CK1-DAG: store ptr [[PGEP:%.+]], ptr [[PARG]]
-// CK1-DAG: [[BPGEP]] = getelementptr inbounds {{.+}}[[BPS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[PGEP]] = getelementptr inbounds {{.+}}[[PS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[BP1:%.+]] = getelementptr inbounds {{.+}}[[BPS]], i32 0, i32 0
-// CK1-DAG: [[P1:%.+]] = getelementptr inbounds {{.+}}[[PS]], i32 0, i32 0
-// CK1-DAG: store ptr [[VAL:%.+]], ptr [[BP1]]
-// CK1-DAG: store ptr [[VAL]], ptr [[P1]]
-// CK1-DAG: [[VAL]] = load ptr, ptr [[ADDR:%.+]],
-// CK1-DAG: [[ADDR]] = load ptr, ptr [[ADDR2:%.+]],
-
-// CK1: call void [[KERNEL:@.+]](ptr [[VAL]])
+
#pragma omp target is_device_ptr(lr)
{
++lr;
}
-// CK1-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:.+]], i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
-// CK1-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
-// CK1-DAG: store ptr [[BPGEP:%.+]], ptr [[BPARG]]
-// CK1-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
-// CK1-DAG: store ptr [[PGEP:%.+]], ptr [[PARG]]
-// CK1-DAG: [[BPGEP]] = getelementptr inbounds {{.+}}[[BPS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[PGEP]] = getelementptr inbounds {{.+}}[[PS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[BP1:%.+]] = getelementptr inbounds {{.+}}[[BPS]], i32 0, i32 0
-// CK1-DAG: [[P1:%.+]] = getelementptr inbounds {{.+}}[[PS]], i32 0, i32 0
-// CK1-DAG: store ptr [[VAL:%.+]], ptr [[BP1]]
-// CK1-DAG: store ptr [[VAL]], ptr [[P1]]
-// CK1-DAG: [[VAL]] = load ptr, ptr [[ADDR:%.+]],
-// CK1-DAG: [[ADDR]] = load ptr, ptr [[ADDR2:%.+]],
-
-// CK1: call void [[KERNEL:@.+]](ptr [[VAL]])
+
#pragma omp target is_device_ptr(tr)
{
++tr;
}
-// CK1-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:.+]], i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
-// CK1-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
-// CK1-DAG: store ptr [[BPGEP:%.+]], ptr [[BPARG]]
-// CK1-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
-// CK1-DAG: store ptr [[PGEP:%.+]], ptr [[PARG]]
-// CK1-DAG: [[BPGEP]] = getelementptr inbounds {{.+}}[[BPS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[PGEP]] = getelementptr inbounds {{.+}}[[PS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[BP1:%.+]] = getelementptr inbounds {{.+}}[[BPS]], i32 0, i32 0
-// CK1-DAG: [[P1:%.+]] = getelementptr inbounds {{.+}}[[PS]], i32 0, i32 0
-// CK1-DAG: store ptr [[VAL:%.+]], ptr [[BP1]]
-// CK1-DAG: store ptr [[VAL]], ptr [[P1]]
-// CK1-DAG: [[VAL]] = load ptr, ptr [[ADDR:%.+]],
-// CK1-DAG: [[ADDR]] = load ptr, ptr [[ADDR2:%.+]],
-
-// CK1: call void [[KERNEL:@.+]](ptr [[VAL]])
+
#pragma omp target is_device_ptr(tr, lr)
{
++tr;
}
-// CK1-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:.+]], i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
-// CK1-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
-// CK1-DAG: store ptr [[BPGEP:%.+]], ptr [[BPARG]]
-// CK1-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
-// CK1-DAG: store ptr [[PGEP:%.+]], ptr [[PARG]]
-// CK1-DAG: [[BPGEP]] = getelementptr inbounds {{.+}}[[BPS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[PGEP]] = getelementptr inbounds {{.+}}[[PS:%[^,]+]], i32 0, i32 0
-// CK1-DAG: [[BP1:%.+]] = getelementptr inbounds {{.+}}[[BPS]], i32 0, i32 0
-// CK1-DAG: [[P1:%.+]] = getelementptr inbounds {{.+}}[[PS]], i32 0, i32 0
-// CK1-DAG: store ptr [[VAL:%.+]], ptr [[BP1]]
-// CK1-DAG: store ptr [[VAL]], ptr [[P1]]
-// CK1-DAG: [[VAL]] = load ptr, ptr [[ADDR:%.+]],
-// CK1-DAG: [[ADDR]] = load ptr, ptr [[ADDR2:%.+]],
-
-// CK1-DAG: [[_BP1:%.+]] = getelementptr inbounds {{.+}}[[BPS]], i32 0, i32 1
-// CK1-DAG: [[_P1:%.+]] = getelementptr inbounds {{.+}}[[PS]], i32 0, i32 1
-// CK1-DAG: store ptr [[_VAL:%.+]], ptr [[_BP1]]
-// CK1-DAG: store ptr [[_VAL]], ptr [[_P1]]
-// CK1-DAG: [[_VAL]] = load ptr, ptr [[_ADDR:%.+]],
-// CK1-DAG: [[_ADDR]] = load ptr, ptr [[_ADDR2:%.+]],
-
-// CK1: call void [[KERNEL:@.+]](ptr [[VAL]], ptr [[_VAL]])
+
+
#pragma omp target is_device_ptr(tr, lr)
{
++tr,++lr;
@@ -200,23 +83,21 @@ void bar(float *&a, int *&b) {
#endif
///==========================================================================///
-// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64
+// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK20
// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-64
-// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32
+// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK21
+// RUN: %clang_cc1 -DCK2 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK22
// RUN: %clang_cc1 -DCK2 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK2 --check-prefix CK2-32
+// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK23
-// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s
+// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY10 %s
// RUN: %clang_cc1 -DCK2 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
-// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s
+// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY11 %s
+// RUN: %clang_cc1 -DCK2 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY12 %s
// RUN: %clang_cc1 -DCK2 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
-// SIMD-ONLY1-NOT: {{__kmpc|__tgt}}
+// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY13 %s
#ifdef CK2
-// CK2: [[ST:%.+]] = type { ptr, ptr }
template <typename T>
struct ST {
@@ -224,70 +105,23 @@ struct ST {
double *&b;
ST(double *&b) : a(0), b(b) {}
- // CK2-LABEL: @{{.*}}foo{{.*}}
void foo(double *&arg) {
int *la = 0;
-// CK2-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:.+]], i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
-// CK2-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
-// CK2-DAG: store ptr [[BPGEP:%.+]], ptr [[BPARG]]
-// CK2-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
-// CK2-DAG: store ptr [[PGEP:%.+]], ptr [[PARG]]
-// CK2-DAG: [[BPGEP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]]
-// CK2-DAG: [[PGEP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]]
-
-// CK2-DAG: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1:%.+]], i32 0, i32 0
-// CK2-DAG: [[BP0:%.+]] = getelementptr inbounds {{.+}}[[BP]], i{{.+}} 0, i{{.+}} 0
-// CK2-DAG: [[P0:%.+]] = getelementptr inbounds {{.+}}[[P]], i{{.+}} 0, i{{.+}} 0
-// CK2-DAG: store ptr [[THIS1]], ptr [[BP0]]
-// CK2-DAG: store ptr [[A]], ptr [[P0]]
+
#pragma omp target is_device_ptr(a)
{
a++;
}
-// CK2-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:.+]], i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
-// CK2-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
-// CK2-DAG: store ptr [[BPGEP:%.+]], ptr [[BPARG]]
-// CK2-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
-// CK2-DAG: store ptr [[PGEP:%.+]], ptr [[PARG]]
-// CK2-DAG: [[SARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 4
-// CK2-DAG: store ptr [[SIZE:%.+]], ptr [[SARG]]
-// CK2-DAG: [[BPGEP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]]
-// CK2-DAG: [[PGEP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]]
-
-// CK2-DAG: [[S:%[^,]+]] = sdiv exact i64 [[SZ:%.+]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
-// CK2-DAG: [[SIZE:%[^,]+]] = getelementptr inbounds [2 x i64], ptr %.offload_sizes, i32 0, i32 0
-// CK2-DAG: store i64 [[S]], ptr [[SIZE]]
-// CK2-DAG: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
-// CK2-DAG: [[BP0:%.+]] = getelementptr inbounds {{.+}}[[BP]], i{{.+}} 0, i{{.+}} 0
-// CK2-DAG: [[P0:%.+]] = getelementptr inbounds {{.+}}[[P]], i{{.+}} 0, i{{.+}} 0
-// CK2-DAG: store ptr [[THIS1]], ptr [[BP0]]
-// CK2-DAG: store ptr [[B]], ptr [[P0]]
+
#pragma omp target is_device_ptr(b)
{
b++;
}
-// CK2-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:.+]], i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
-// CK2-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
-// CK2-DAG: store ptr [[BPGEP:%.+]], ptr [[BPARG]]
-// CK2-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
-// CK2-DAG: store ptr [[PGEP:%.+]], ptr [[PARG]]
-// CK2-DAG: [[SARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 4
-// CK2-DAG: store ptr [[SIZE:%.+]], ptr [[SARG]]
-// CK2-DAG: [[BPGEP]] = getelementptr inbounds {{.+}}[[BP:%[^,]+]]
-// CK2-DAG: [[PGEP]] = getelementptr inbounds {{.+}}[[P:%[^,]+]]
-
-// CK2-DAG: [[A8:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
-// CK2-DAG: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
-// CK2-DAG: [[S:%[^,]+]] = sdiv exact i64 [[SZ:%.+]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
-// CK2-DAG: store i64 [[S]], ptr [[SIZE:%.+]]
-
-// CK2-DAG: [[BP0:%.+]] = getelementptr inbounds {{.+}}[[BP]], i{{.+}} 0, i{{.+}} 0
-// CK2-DAG: [[P0:%.+]] = getelementptr inbounds {{.+}}[[P]], i{{.+}} 0, i{{.+}} 0
-// CK2-DAG: store ptr [[THIS1]], ptr [[BP0]]
-// CK2-DAG: store ptr [[A8]], ptr [[TMP64:%.+]]
+
+
#pragma omp target is_device_ptr(a, b)
{
a++;
@@ -303,42 +137,5595 @@ void bar(double *arg){
}
#endif
///==========================================================================///
-// RUN: %clang_cc1 -DCK3 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64
+// RUN: %clang_cc1 -DCK3 -verify -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK30
// RUN: %clang_cc1 -DCK3 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-64
-// RUN: %clang_cc1 -DCK3 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32
+// RUN: %clang_cc1 -fopenmp -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK31
+// RUN: %clang_cc1 -DCK3 -verify -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CK32
// RUN: %clang_cc1 -DCK3 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK3 --check-prefix CK3-32
+// RUN: %clang_cc1 -fopenmp -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CK33
-// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s
+// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY20 %s
// RUN: %clang_cc1 -DCK3 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
-// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY1 %s
+// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY21 %s
+// RUN: %clang_cc1 -DCK3 -verify -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY22 %s
// RUN: %clang_cc1 -DCK3 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
-// SIMD-ONLY1-NOT: {{__kmpc|__tgt}}
+// RUN: %clang_cc1 -fopenmp-simd -fopenmp-targets=i386-pc-linux-gnu -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY23 %s
#ifdef CK3
-// CK3-DAG: [[SIZES:@.+]] = {{.+}}constant [1 x i[[SZ:64|32]]] [i{{64|32}} {{8|4}}]
// OMP_MAP_TARGET_PARAM = 0x20 | OMP_MAP_TO = 0x1 = 0x21
-// CK3-DAG: [[TYPES:@.+]] = {{.+}}constant [1 x i64] [i64 [[#0x21]]]
void bar() {
__attribute__((aligned(64))) double *ptr;
- // CK3-DAG: [[RET:%.+]] = call i32 @__tgt_target_kernel(ptr @{{.+}}, i64 [[DEVICE:.+]], i32 -1, i32 0, ptr @.{{.+}}.region_id, ptr [[ARGS:%.+]])
- // CK3-DAG: [[BPARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 2
- // CK3-DAG: store ptr [[BPGEP:%.+]], ptr [[BPARG]]
- // CK3-DAG: [[PARG:%.+]] = getelementptr inbounds {{.+}}[[ARGS]], i32 0, i32 3
- // CK3-DAG: store ptr [[PGEP:%.+]], ptr [[PARG]]
- // CK3-DAG: [[BPGEP]] = getelementptr inbounds {{.+}}[[BPS:%[^,]+]], i32 0, i32 0
- // CK3-DAG: [[PGEP]] = getelementptr inbounds {{.+}}[[PS:%[^,]+]], i32 0, i32 0
- // CK3-DAG: [[BP1:%.+]] = getelementptr inbounds {{.+}}[[BPS]], i32 0, i32 0
- // CK3-DAG: [[P1:%.+]] = getelementptr inbounds {{.+}}[[PS]], i32 0, i32 0
- // CK3-DAG: store ptr [[PTR:%.+]], ptr [[BP1]]
- // CK3-DAG: store ptr [[PTR]], ptr [[P1]]
-
- // CK3: call void [[KERNEL:@.+]](ptr [[PTR]])
+
#pragma omp target is_device_ptr(ptr)
*ptr = 0;
}
#endif
#endif
+// CK1-64-LABEL: define {{[^@]+}}@_Z3barRPfRPi
+// CK1-64-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK1-64-NEXT: entry:
+// CK1-64-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// CK1-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// CK1-64-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// CK1-64-NEXT: call void @_Z3fooIiEvRPfRPT_(ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP1]])
+// CK1-64-NEXT: ret void
+// CK1-64-LABEL: define {{[^@]+}}@_Z3fooIiEvRPfRPT_
+// CK1-64-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[LR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[TR:%.*]]) #[[ATTR0]] comdat {
+// CK1-64-NEXT: entry:
+// CK1-64-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[L:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[T:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[_TMP19:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[_TMP26:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x ptr], align 8
+// CK1-64-NEXT: [[_TMP33:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[_TMP34:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_BASEPTRS35:%.*]] = alloca [2 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_PTRS36:%.*]] = alloca [2 x ptr], align 8
+// CK1-64-NEXT: [[DOTOFFLOAD_MAPPERS37:%.*]] = alloca [2 x ptr], align 8
+// CK1-64-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK1-64-NEXT: [[TMP0:%.*]] = load ptr, ptr @g, align 8
+// CK1-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8
+// CK1-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 8
+// CK1-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CK1-64-NEXT: store ptr null, ptr [[TMP3]], align 8
+// CK1-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK1-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK1-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK1-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK1-64-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK1-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK1-64-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK1-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK1-64-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
+// CK1-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK1-64-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8
+// CK1-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK1-64-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 8
+// CK1-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK1-64-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 8
+// CK1-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK1-64-NEXT: store ptr null, ptr [[TMP12]], align 8
+// CK1-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK1-64-NEXT: store ptr null, ptr [[TMP13]], align 8
+// CK1-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK1-64-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK1-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK1-64-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK1-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK1-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK1-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK1-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK1-64-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK1-64-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37.region_id, ptr [[KERNEL_ARGS]])
+// CK1-64-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK1-64-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK1-64: omp_offload.failed:
+// CK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK1-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK1-64: omp_offload.cont:
+// CK1-64-NEXT: [[TMP21:%.*]] = load ptr, ptr [[L]], align 8
+// CK1-64-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP21]], ptr [[TMP22]], align 8
+// CK1-64-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP21]], ptr [[TMP23]], align 8
+// CK1-64-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
+// CK1-64-NEXT: store ptr null, ptr [[TMP24]], align 8
+// CK1-64-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK1-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK1-64-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0
+// CK1-64-NEXT: store i32 2, ptr [[TMP27]], align 4
+// CK1-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1
+// CK1-64-NEXT: store i32 1, ptr [[TMP28]], align 4
+// CK1-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2
+// CK1-64-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 8
+// CK1-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3
+// CK1-64-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 8
+// CK1-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4
+// CK1-64-NEXT: store ptr @.offload_sizes.1, ptr [[TMP31]], align 8
+// CK1-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5
+// CK1-64-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP32]], align 8
+// CK1-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6
+// CK1-64-NEXT: store ptr null, ptr [[TMP33]], align 8
+// CK1-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7
+// CK1-64-NEXT: store ptr null, ptr [[TMP34]], align 8
+// CK1-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8
+// CK1-64-NEXT: store i64 0, ptr [[TMP35]], align 8
+// CK1-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9
+// CK1-64-NEXT: store i64 0, ptr [[TMP36]], align 8
+// CK1-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10
+// CK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP37]], align 4
+// CK1-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11
+// CK1-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 4
+// CK1-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12
+// CK1-64-NEXT: store i32 0, ptr [[TMP39]], align 4
+// CK1-64-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43.region_id, ptr [[KERNEL_ARGS4]])
+// CK1-64-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
+// CK1-64-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
+// CK1-64: omp_offload.failed5:
+// CK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43(ptr [[TMP21]]) #[[ATTR2]]
+// CK1-64-NEXT: br label [[OMP_OFFLOAD_CONT6]]
+// CK1-64: omp_offload.cont6:
+// CK1-64-NEXT: [[TMP42:%.*]] = load ptr, ptr [[T]], align 8
+// CK1-64-NEXT: [[TMP43:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP42]], ptr [[TMP43]], align 8
+// CK1-64-NEXT: [[TMP44:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP42]], ptr [[TMP44]], align 8
+// CK1-64-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
+// CK1-64-NEXT: store ptr null, ptr [[TMP45]], align 8
+// CK1-64-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK1-64-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK1-64-NEXT: [[KERNEL_ARGS10:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-64-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 0
+// CK1-64-NEXT: store i32 2, ptr [[TMP48]], align 4
+// CK1-64-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 1
+// CK1-64-NEXT: store i32 1, ptr [[TMP49]], align 4
+// CK1-64-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 2
+// CK1-64-NEXT: store ptr [[TMP46]], ptr [[TMP50]], align 8
+// CK1-64-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 3
+// CK1-64-NEXT: store ptr [[TMP47]], ptr [[TMP51]], align 8
+// CK1-64-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 4
+// CK1-64-NEXT: store ptr @.offload_sizes.3, ptr [[TMP52]], align 8
+// CK1-64-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 5
+// CK1-64-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP53]], align 8
+// CK1-64-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 6
+// CK1-64-NEXT: store ptr null, ptr [[TMP54]], align 8
+// CK1-64-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 7
+// CK1-64-NEXT: store ptr null, ptr [[TMP55]], align 8
+// CK1-64-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 8
+// CK1-64-NEXT: store i64 0, ptr [[TMP56]], align 8
+// CK1-64-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 9
+// CK1-64-NEXT: store i64 0, ptr [[TMP57]], align 8
+// CK1-64-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 10
+// CK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP58]], align 4
+// CK1-64-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 11
+// CK1-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP59]], align 4
+// CK1-64-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 12
+// CK1-64-NEXT: store i32 0, ptr [[TMP60]], align 4
+// CK1-64-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49.region_id, ptr [[KERNEL_ARGS10]])
+// CK1-64-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0
+// CK1-64-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
+// CK1-64: omp_offload.failed11:
+// CK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49(ptr [[TMP42]]) #[[ATTR2]]
+// CK1-64-NEXT: br label [[OMP_OFFLOAD_CONT12]]
+// CK1-64: omp_offload.cont12:
+// CK1-64-NEXT: [[TMP63:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[TMP63]], ptr [[TMP]], align 8
+// CK1-64-NEXT: [[TMP64:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK1-64-NEXT: [[TMP65:%.*]] = load ptr, ptr [[TMP64]], align 8
+// CK1-64-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP65]], ptr [[TMP66]], align 8
+// CK1-64-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP65]], ptr [[TMP67]], align 8
+// CK1-64-NEXT: [[TMP68:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0
+// CK1-64-NEXT: store ptr null, ptr [[TMP68]], align 8
+// CK1-64-NEXT: [[TMP69:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK1-64-NEXT: [[TMP70:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK1-64-NEXT: [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-64-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 0
+// CK1-64-NEXT: store i32 2, ptr [[TMP71]], align 4
+// CK1-64-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 1
+// CK1-64-NEXT: store i32 1, ptr [[TMP72]], align 4
+// CK1-64-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 2
+// CK1-64-NEXT: store ptr [[TMP69]], ptr [[TMP73]], align 8
+// CK1-64-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 3
+// CK1-64-NEXT: store ptr [[TMP70]], ptr [[TMP74]], align 8
+// CK1-64-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 4
+// CK1-64-NEXT: store ptr @.offload_sizes.5, ptr [[TMP75]], align 8
+// CK1-64-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 5
+// CK1-64-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP76]], align 8
+// CK1-64-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 6
+// CK1-64-NEXT: store ptr null, ptr [[TMP77]], align 8
+// CK1-64-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 7
+// CK1-64-NEXT: store ptr null, ptr [[TMP78]], align 8
+// CK1-64-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 8
+// CK1-64-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK1-64-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 9
+// CK1-64-NEXT: store i64 0, ptr [[TMP80]], align 8
+// CK1-64-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 10
+// CK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP81]], align 4
+// CK1-64-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 11
+// CK1-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP82]], align 4
+// CK1-64-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 12
+// CK1-64-NEXT: store i32 0, ptr [[TMP83]], align 4
+// CK1-64-NEXT: [[TMP84:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55.region_id, ptr [[KERNEL_ARGS16]])
+// CK1-64-NEXT: [[TMP85:%.*]] = icmp ne i32 [[TMP84]], 0
+// CK1-64-NEXT: br i1 [[TMP85]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
+// CK1-64: omp_offload.failed17:
+// CK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55(ptr [[TMP65]]) #[[ATTR2]]
+// CK1-64-NEXT: br label [[OMP_OFFLOAD_CONT18]]
+// CK1-64: omp_offload.cont18:
+// CK1-64-NEXT: [[TMP86:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[TMP86]], ptr [[_TMP19]], align 8
+// CK1-64-NEXT: [[TMP87:%.*]] = load ptr, ptr [[_TMP19]], align 8
+// CK1-64-NEXT: [[TMP88:%.*]] = load ptr, ptr [[TMP87]], align 8
+// CK1-64-NEXT: [[TMP89:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP88]], ptr [[TMP89]], align 8
+// CK1-64-NEXT: [[TMP90:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP88]], ptr [[TMP90]], align 8
+// CK1-64-NEXT: [[TMP91:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
+// CK1-64-NEXT: store ptr null, ptr [[TMP91]], align 8
+// CK1-64-NEXT: [[TMP92:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK1-64-NEXT: [[TMP93:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK1-64-NEXT: [[KERNEL_ARGS23:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-64-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 0
+// CK1-64-NEXT: store i32 2, ptr [[TMP94]], align 4
+// CK1-64-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 1
+// CK1-64-NEXT: store i32 1, ptr [[TMP95]], align 4
+// CK1-64-NEXT: [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 2
+// CK1-64-NEXT: store ptr [[TMP92]], ptr [[TMP96]], align 8
+// CK1-64-NEXT: [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 3
+// CK1-64-NEXT: store ptr [[TMP93]], ptr [[TMP97]], align 8
+// CK1-64-NEXT: [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 4
+// CK1-64-NEXT: store ptr @.offload_sizes.7, ptr [[TMP98]], align 8
+// CK1-64-NEXT: [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 5
+// CK1-64-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP99]], align 8
+// CK1-64-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 6
+// CK1-64-NEXT: store ptr null, ptr [[TMP100]], align 8
+// CK1-64-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 7
+// CK1-64-NEXT: store ptr null, ptr [[TMP101]], align 8
+// CK1-64-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 8
+// CK1-64-NEXT: store i64 0, ptr [[TMP102]], align 8
+// CK1-64-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 9
+// CK1-64-NEXT: store i64 0, ptr [[TMP103]], align 8
+// CK1-64-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 10
+// CK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP104]], align 4
+// CK1-64-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 11
+// CK1-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP105]], align 4
+// CK1-64-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 12
+// CK1-64-NEXT: store i32 0, ptr [[TMP106]], align 4
+// CK1-64-NEXT: [[TMP107:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61.region_id, ptr [[KERNEL_ARGS23]])
+// CK1-64-NEXT: [[TMP108:%.*]] = icmp ne i32 [[TMP107]], 0
+// CK1-64-NEXT: br i1 [[TMP108]], label [[OMP_OFFLOAD_FAILED24:%.*]], label [[OMP_OFFLOAD_CONT25:%.*]]
+// CK1-64: omp_offload.failed24:
+// CK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61(ptr [[TMP88]]) #[[ATTR2]]
+// CK1-64-NEXT: br label [[OMP_OFFLOAD_CONT25]]
+// CK1-64: omp_offload.cont25:
+// CK1-64-NEXT: [[TMP109:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[TMP109]], ptr [[_TMP26]], align 8
+// CK1-64-NEXT: [[TMP110:%.*]] = load ptr, ptr [[_TMP26]], align 8
+// CK1-64-NEXT: [[TMP111:%.*]] = load ptr, ptr [[TMP110]], align 8
+// CK1-64-NEXT: [[TMP112:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP111]], ptr [[TMP112]], align 8
+// CK1-64-NEXT: [[TMP113:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP111]], ptr [[TMP113]], align 8
+// CK1-64-NEXT: [[TMP114:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 0
+// CK1-64-NEXT: store ptr null, ptr [[TMP114]], align 8
+// CK1-64-NEXT: [[TMP115:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK1-64-NEXT: [[TMP116:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK1-64-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-64-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 0
+// CK1-64-NEXT: store i32 2, ptr [[TMP117]], align 4
+// CK1-64-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 1
+// CK1-64-NEXT: store i32 1, ptr [[TMP118]], align 4
+// CK1-64-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 2
+// CK1-64-NEXT: store ptr [[TMP115]], ptr [[TMP119]], align 8
+// CK1-64-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 3
+// CK1-64-NEXT: store ptr [[TMP116]], ptr [[TMP120]], align 8
+// CK1-64-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 4
+// CK1-64-NEXT: store ptr @.offload_sizes.9, ptr [[TMP121]], align 8
+// CK1-64-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 5
+// CK1-64-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP122]], align 8
+// CK1-64-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 6
+// CK1-64-NEXT: store ptr null, ptr [[TMP123]], align 8
+// CK1-64-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 7
+// CK1-64-NEXT: store ptr null, ptr [[TMP124]], align 8
+// CK1-64-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 8
+// CK1-64-NEXT: store i64 0, ptr [[TMP125]], align 8
+// CK1-64-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 9
+// CK1-64-NEXT: store i64 0, ptr [[TMP126]], align 8
+// CK1-64-NEXT: [[TMP127:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 10
+// CK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP127]], align 4
+// CK1-64-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 11
+// CK1-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP128]], align 4
+// CK1-64-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 12
+// CK1-64-NEXT: store i32 0, ptr [[TMP129]], align 4
+// CK1-64-NEXT: [[TMP130:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67.region_id, ptr [[KERNEL_ARGS30]])
+// CK1-64-NEXT: [[TMP131:%.*]] = icmp ne i32 [[TMP130]], 0
+// CK1-64-NEXT: br i1 [[TMP131]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]]
+// CK1-64: omp_offload.failed31:
+// CK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67(ptr [[TMP111]]) #[[ATTR2]]
+// CK1-64-NEXT: br label [[OMP_OFFLOAD_CONT32]]
+// CK1-64: omp_offload.cont32:
+// CK1-64-NEXT: [[TMP132:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[TMP132]], ptr [[_TMP33]], align 8
+// CK1-64-NEXT: [[TMP133:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[TMP133]], ptr [[_TMP34]], align 8
+// CK1-64-NEXT: [[TMP134:%.*]] = load ptr, ptr [[_TMP33]], align 8
+// CK1-64-NEXT: [[TMP135:%.*]] = load ptr, ptr [[TMP134]], align 8
+// CK1-64-NEXT: [[TMP136:%.*]] = load ptr, ptr [[_TMP34]], align 8
+// CK1-64-NEXT: [[TMP137:%.*]] = load ptr, ptr [[TMP136]], align 8
+// CK1-64-NEXT: [[TMP138:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP135]], ptr [[TMP138]], align 8
+// CK1-64-NEXT: [[TMP139:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK1-64-NEXT: store ptr [[TMP135]], ptr [[TMP139]], align 8
+// CK1-64-NEXT: [[TMP140:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i64 0, i64 0
+// CK1-64-NEXT: store ptr null, ptr [[TMP140]], align 8
+// CK1-64-NEXT: [[TMP141:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 1
+// CK1-64-NEXT: store ptr [[TMP137]], ptr [[TMP141]], align 8
+// CK1-64-NEXT: [[TMP142:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 1
+// CK1-64-NEXT: store ptr [[TMP137]], ptr [[TMP142]], align 8
+// CK1-64-NEXT: [[TMP143:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i64 0, i64 1
+// CK1-64-NEXT: store ptr null, ptr [[TMP143]], align 8
+// CK1-64-NEXT: [[TMP144:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK1-64-NEXT: [[TMP145:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK1-64-NEXT: [[KERNEL_ARGS38:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-64-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 0
+// CK1-64-NEXT: store i32 2, ptr [[TMP146]], align 4
+// CK1-64-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 1
+// CK1-64-NEXT: store i32 2, ptr [[TMP147]], align 4
+// CK1-64-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 2
+// CK1-64-NEXT: store ptr [[TMP144]], ptr [[TMP148]], align 8
+// CK1-64-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 3
+// CK1-64-NEXT: store ptr [[TMP145]], ptr [[TMP149]], align 8
+// CK1-64-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 4
+// CK1-64-NEXT: store ptr @.offload_sizes.11, ptr [[TMP150]], align 8
+// CK1-64-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 5
+// CK1-64-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP151]], align 8
+// CK1-64-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 6
+// CK1-64-NEXT: store ptr null, ptr [[TMP152]], align 8
+// CK1-64-NEXT: [[TMP153:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 7
+// CK1-64-NEXT: store ptr null, ptr [[TMP153]], align 8
+// CK1-64-NEXT: [[TMP154:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 8
+// CK1-64-NEXT: store i64 0, ptr [[TMP154]], align 8
+// CK1-64-NEXT: [[TMP155:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 9
+// CK1-64-NEXT: store i64 0, ptr [[TMP155]], align 8
+// CK1-64-NEXT: [[TMP156:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 10
+// CK1-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP156]], align 4
+// CK1-64-NEXT: [[TMP157:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 11
+// CK1-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP157]], align 4
+// CK1-64-NEXT: [[TMP158:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 12
+// CK1-64-NEXT: store i32 0, ptr [[TMP158]], align 4
+// CK1-64-NEXT: [[TMP159:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74.region_id, ptr [[KERNEL_ARGS38]])
+// CK1-64-NEXT: [[TMP160:%.*]] = icmp ne i32 [[TMP159]], 0
+// CK1-64-NEXT: br i1 [[TMP160]], label [[OMP_OFFLOAD_FAILED39:%.*]], label [[OMP_OFFLOAD_CONT40:%.*]]
+// CK1-64: omp_offload.failed39:
+// CK1-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74(ptr [[TMP135]], ptr [[TMP137]]) #[[ATTR2]]
+// CK1-64-NEXT: br label [[OMP_OFFLOAD_CONT40]]
+// CK1-64: omp_offload.cont40:
+// CK1-64-NEXT: ret void
+// CK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37
+// CK1-64-SAME: (ptr noundef [[G:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK1-64-NEXT: entry:
+// CK1-64-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8
+// CK1-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8
+// CK1-64-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK1-64-NEXT: store ptr [[INCDEC_PTR]], ptr [[G_ADDR]], align 8
+// CK1-64-NEXT: ret void
+// CK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43
+// CK1-64-SAME: (ptr noundef [[L:%.*]]) #[[ATTR1]] {
+// CK1-64-NEXT: entry:
+// CK1-64-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
+// CK1-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[L_ADDR]], align 8
+// CK1-64-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i32 1
+// CK1-64-NEXT: store ptr [[INCDEC_PTR]], ptr [[L_ADDR]], align 8
+// CK1-64-NEXT: ret void
+// CK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49
+// CK1-64-SAME: (ptr noundef [[T:%.*]]) #[[ATTR1]] {
+// CK1-64-NEXT: entry:
+// CK1-64-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8
+// CK1-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8
+// CK1-64-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
+// CK1-64-NEXT: store ptr [[INCDEC_PTR]], ptr [[T_ADDR]], align 8
+// CK1-64-NEXT: ret void
+// CK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55
+// CK1-64-SAME: (ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK1-64-NEXT: entry:
+// CK1-64-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[LR_ADDR]], ptr [[TMP]], align 8
+// CK1-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK1-64-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK1-64-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 1
+// CK1-64-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK1-64-NEXT: ret void
+// CK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61
+// CK1-64-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK1-64-NEXT: entry:
+// CK1-64-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 8
+// CK1-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK1-64-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK1-64-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK1-64-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK1-64-NEXT: ret void
+// CK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67
+// CK1-64-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK1-64-NEXT: entry:
+// CK1-64-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 8
+// CK1-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK1-64-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK1-64-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK1-64-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK1-64-NEXT: ret void
+// CK1-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74
+// CK1-64-SAME: (ptr noundef [[TR:%.*]], ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK1-64-NEXT: entry:
+// CK1-64-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
+// CK1-64-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 8
+// CK1-64-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 8
+// CK1-64-NEXT: store ptr [[LR_ADDR]], ptr [[_TMP1]], align 8
+// CK1-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK1-64-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK1-64-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK1-64-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK1-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8
+// CK1-64-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CK1-64-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i32 1
+// CK1-64-NEXT: store ptr [[INCDEC_PTR2]], ptr [[TMP2]], align 8
+// CK1-64-NEXT: ret void
+// CK1-64-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK1-64-SAME: () #[[ATTR3:[0-9]+]] {
+// CK1-64-NEXT: entry:
+// CK1-64-NEXT: call void @__tgt_register_requires(i64 1)
+// CK1-64-NEXT: ret void
+// CK2-64-LABEL: define {{[^@]+}}@_Z3barPd
+// CK2-64-SAME: (ptr noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK2-64-NEXT: entry:
+// CK2-64-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
+// CK2-64-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 8
+// CK2-64-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
+// CK2-64-NEXT: call void @_ZN2STIdEC1ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
+// CK2-64-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
+// CK2-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8
+// CK2-64-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK2-64-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8
+// CK2-64-NEXT: ret void
+// CK2-64-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
+// CK2-64-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
+// CK2-64-NEXT: entry:
+// CK2-64-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK2-64-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// CK2-64-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// CK2-64-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// CK2-64-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]])
+// CK2-64-NEXT: ret void
+// CK2-64-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
+// CK2-64-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 {
+// CK2-64-NEXT: entry:
+// CK2-64-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK2-64-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
+// CK2-64-NEXT: [[LA:%.*]] = alloca ptr, align 8
+// CK2-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
+// CK2-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
+// CK2-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
+// CK2-64-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x ptr], align 8
+// CK2-64-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x ptr], align 8
+// CK2-64-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x ptr], align 8
+// CK2-64-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [2 x i64], align 8
+// CK2-64-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [3 x ptr], align 8
+// CK2-64-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [3 x ptr], align 8
+// CK2-64-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [3 x ptr], align 8
+// CK2-64-NEXT: [[DOTOFFLOAD_SIZES13:%.*]] = alloca [3 x i64], align 8
+// CK2-64-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
+// CK2-64-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: store ptr null, ptr [[LA]], align 8
+// CK2-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK2-64-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK2-64-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 8
+// CK2-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK2-64-NEXT: store ptr [[A]], ptr [[TMP1]], align 8
+// CK2-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CK2-64-NEXT: store ptr null, ptr [[TMP2]], align 8
+// CK2-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK2-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK2-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK2-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK2-64-NEXT: store i32 2, ptr [[TMP5]], align 4
+// CK2-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK2-64-NEXT: store i32 1, ptr [[TMP6]], align 4
+// CK2-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK2-64-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
+// CK2-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK2-64-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
+// CK2-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK2-64-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8
+// CK2-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK2-64-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8
+// CK2-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK2-64-NEXT: store ptr null, ptr [[TMP11]], align 8
+// CK2-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK2-64-NEXT: store ptr null, ptr [[TMP12]], align 8
+// CK2-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK2-64-NEXT: store i64 0, ptr [[TMP13]], align 8
+// CK2-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK2-64-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK2-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK2-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP15]], align 4
+// CK2-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK2-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
+// CK2-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK2-64-NEXT: store i32 0, ptr [[TMP17]], align 4
+// CK2-64-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112.region_id, ptr [[KERNEL_ARGS]])
+// CK2-64-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
+// CK2-64-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK2-64: omp_offload.failed:
+// CK2-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112(ptr [[THIS1]]) #[[ATTR3:[0-9]+]]
+// CK2-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK2-64: omp_offload.cont:
+// CK2-64-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK2-64-NEXT: [[TMP20:%.*]] = load ptr, ptr [[B]], align 8
+// CK2-64-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[B]], i32 1
+// CK2-64-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+// CK2-64-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[B]] to i64
+// CK2-64-NEXT: [[TMP24:%.*]] = sub i64 [[TMP22]], [[TMP23]]
+// CK2-64-NEXT: [[TMP25:%.*]] = sdiv exact i64 [[TMP24]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK2-64-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.1, i64 16, i1 false)
+// CK2-64-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK2-64-NEXT: store ptr [[THIS1]], ptr [[TMP26]], align 8
+// CK2-64-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK2-64-NEXT: store ptr [[B]], ptr [[TMP27]], align 8
+// CK2-64-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK2-64-NEXT: store i64 [[TMP25]], ptr [[TMP28]], align 8
+// CK2-64-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 0
+// CK2-64-NEXT: store ptr null, ptr [[TMP29]], align 8
+// CK2-64-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
+// CK2-64-NEXT: store ptr [[THIS1]], ptr [[TMP30]], align 8
+// CK2-64-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
+// CK2-64-NEXT: store ptr [[TMP20]], ptr [[TMP31]], align 8
+// CK2-64-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 1
+// CK2-64-NEXT: store ptr null, ptr [[TMP32]], align 8
+// CK2-64-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK2-64-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK2-64-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK2-64-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK2-64-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
+// CK2-64-NEXT: store i32 2, ptr [[TMP36]], align 4
+// CK2-64-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
+// CK2-64-NEXT: store i32 2, ptr [[TMP37]], align 4
+// CK2-64-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
+// CK2-64-NEXT: store ptr [[TMP33]], ptr [[TMP38]], align 8
+// CK2-64-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
+// CK2-64-NEXT: store ptr [[TMP34]], ptr [[TMP39]], align 8
+// CK2-64-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
+// CK2-64-NEXT: store ptr [[TMP35]], ptr [[TMP40]], align 8
+// CK2-64-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
+// CK2-64-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP41]], align 8
+// CK2-64-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
+// CK2-64-NEXT: store ptr null, ptr [[TMP42]], align 8
+// CK2-64-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
+// CK2-64-NEXT: store ptr null, ptr [[TMP43]], align 8
+// CK2-64-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
+// CK2-64-NEXT: store i64 0, ptr [[TMP44]], align 8
+// CK2-64-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
+// CK2-64-NEXT: store i64 0, ptr [[TMP45]], align 8
+// CK2-64-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
+// CK2-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP46]], align 4
+// CK2-64-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
+// CK2-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4
+// CK2-64-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
+// CK2-64-NEXT: store i32 0, ptr [[TMP48]], align 4
+// CK2-64-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118.region_id, ptr [[KERNEL_ARGS5]])
+// CK2-64-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
+// CK2-64-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CK2-64: omp_offload.failed6:
+// CK2-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118(ptr [[THIS1]]) #[[ATTR3]]
+// CK2-64-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CK2-64: omp_offload.cont7:
+// CK2-64-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
+// CK2-64-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK2-64-NEXT: [[TMP51:%.*]] = load ptr, ptr [[B9]], align 8
+// CK2-64-NEXT: [[TMP52:%.*]] = getelementptr ptr, ptr [[B9]], i32 1
+// CK2-64-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[TMP52]] to i64
+// CK2-64-NEXT: [[TMP54:%.*]] = ptrtoint ptr [[A8]] to i64
+// CK2-64-NEXT: [[TMP55:%.*]] = sub i64 [[TMP53]], [[TMP54]]
+// CK2-64-NEXT: [[TMP56:%.*]] = sdiv exact i64 [[TMP55]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK2-64-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES13]], ptr align 8 @.offload_sizes.3, i64 24, i1 false)
+// CK2-64-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK2-64-NEXT: store ptr [[THIS1]], ptr [[TMP57]], align 8
+// CK2-64-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK2-64-NEXT: store ptr [[A8]], ptr [[TMP58]], align 8
+// CK2-64-NEXT: [[TMP59:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK2-64-NEXT: store i64 [[TMP56]], ptr [[TMP59]], align 8
+// CK2-64-NEXT: [[TMP60:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
+// CK2-64-NEXT: store ptr null, ptr [[TMP60]], align 8
+// CK2-64-NEXT: [[TMP61:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
+// CK2-64-NEXT: store ptr [[THIS1]], ptr [[TMP61]], align 8
+// CK2-64-NEXT: [[TMP62:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
+// CK2-64-NEXT: store ptr [[A8]], ptr [[TMP62]], align 8
+// CK2-64-NEXT: [[TMP63:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
+// CK2-64-NEXT: store ptr null, ptr [[TMP63]], align 8
+// CK2-64-NEXT: [[TMP64:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 2
+// CK2-64-NEXT: store ptr [[THIS1]], ptr [[TMP64]], align 8
+// CK2-64-NEXT: [[TMP65:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 2
+// CK2-64-NEXT: store ptr [[TMP51]], ptr [[TMP65]], align 8
+// CK2-64-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 2
+// CK2-64-NEXT: store ptr null, ptr [[TMP66]], align 8
+// CK2-64-NEXT: [[TMP67:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK2-64-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK2-64-NEXT: [[TMP69:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK2-64-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK2-64-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
+// CK2-64-NEXT: store i32 2, ptr [[TMP70]], align 4
+// CK2-64-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
+// CK2-64-NEXT: store i32 3, ptr [[TMP71]], align 4
+// CK2-64-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
+// CK2-64-NEXT: store ptr [[TMP67]], ptr [[TMP72]], align 8
+// CK2-64-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
+// CK2-64-NEXT: store ptr [[TMP68]], ptr [[TMP73]], align 8
+// CK2-64-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
+// CK2-64-NEXT: store ptr [[TMP69]], ptr [[TMP74]], align 8
+// CK2-64-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
+// CK2-64-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP75]], align 8
+// CK2-64-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
+// CK2-64-NEXT: store ptr null, ptr [[TMP76]], align 8
+// CK2-64-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
+// CK2-64-NEXT: store ptr null, ptr [[TMP77]], align 8
+// CK2-64-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
+// CK2-64-NEXT: store i64 0, ptr [[TMP78]], align 8
+// CK2-64-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
+// CK2-64-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK2-64-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
+// CK2-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP80]], align 4
+// CK2-64-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
+// CK2-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP81]], align 4
+// CK2-64-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
+// CK2-64-NEXT: store i32 0, ptr [[TMP82]], align 4
+// CK2-64-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125.region_id, ptr [[KERNEL_ARGS14]])
+// CK2-64-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0
+// CK2-64-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
+// CK2-64: omp_offload.failed15:
+// CK2-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125(ptr [[THIS1]]) #[[ATTR3]]
+// CK2-64-NEXT: br label [[OMP_OFFLOAD_CONT16]]
+// CK2-64: omp_offload.cont16:
+// CK2-64-NEXT: ret void
+// CK2-64-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
+// CK2-64-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
+// CK2-64-NEXT: entry:
+// CK2-64-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK2-64-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// CK2-64-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// CK2-64-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK2-64-NEXT: store ptr null, ptr [[A]], align 8
+// CK2-64-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK2-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// CK2-64-NEXT: store ptr [[TMP0]], ptr [[B2]], align 8
+// CK2-64-NEXT: ret void
+// CK2-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112
+// CK2-64-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] {
+// CK2-64-NEXT: entry:
+// CK2-64-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK2-64-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK2-64-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8
+// CK2-64-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK2-64-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 8
+// CK2-64-NEXT: ret void
+// CK2-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118
+// CK2-64-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK2-64-NEXT: entry:
+// CK2-64-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK2-64-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 1
+// CK2-64-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B]], align 8
+// CK2-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CK2-64-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 1
+// CK2-64-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP1]], align 8
+// CK2-64-NEXT: ret void
+// CK2-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125
+// CK2-64-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK2-64-NEXT: entry:
+// CK2-64-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK2-64-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK2-64-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK2-64-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8
+// CK2-64-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK2-64-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 8
+// CK2-64-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP0]], i32 0, i32 1
+// CK2-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B]], align 8
+// CK2-64-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CK2-64-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 1
+// CK2-64-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP2]], align 8
+// CK2-64-NEXT: ret void
+// CK2-64-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK2-64-SAME: () #[[ATTR5:[0-9]+]] {
+// CK2-64-NEXT: entry:
+// CK2-64-NEXT: call void @__tgt_register_requires(i64 1)
+// CK2-64-NEXT: ret void
+// CK2-32-LABEL: define {{[^@]+}}@_Z3barPd
+// CK2-32-SAME: (ptr noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK2-32-NEXT: entry:
+// CK2-32-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 4
+// CK2-32-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
+// CK2-32-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 4
+// CK2-32-NEXT: call void @_ZN2STIdEC1ERPd(ptr noundef nonnull align 4 dereferenceable(8) [[A]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG_ADDR]])
+// CK2-32-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 4 dereferenceable(8) [[A]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG_ADDR]])
+// CK2-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 4
+// CK2-32-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK2-32-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 4
+// CK2-32-NEXT: ret void
+// CK2-32-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
+// CK2-32-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
+// CK2-32-NEXT: entry:
+// CK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK2-32-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// CK2-32-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// CK2-32-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// CK2-32-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])
+// CK2-32-NEXT: ret void
+// CK2-32-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
+// CK2-32-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 {
+// CK2-32-NEXT: entry:
+// CK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK2-32-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 4
+// CK2-32-NEXT: [[LA:%.*]] = alloca ptr, align 4
+// CK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
+// CK2-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
+// CK2-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
+// CK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x ptr], align 4
+// CK2-32-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x ptr], align 4
+// CK2-32-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x ptr], align 4
+// CK2-32-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [2 x i64], align 4
+// CK2-32-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [3 x ptr], align 4
+// CK2-32-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [3 x ptr], align 4
+// CK2-32-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [3 x ptr], align 4
+// CK2-32-NEXT: [[DOTOFFLOAD_SIZES13:%.*]] = alloca [3 x i64], align 4
+// CK2-32-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 4
+// CK2-32-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: store ptr null, ptr [[LA]], align 4
+// CK2-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK2-32-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK2-32-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 4
+// CK2-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK2-32-NEXT: store ptr [[A]], ptr [[TMP1]], align 4
+// CK2-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CK2-32-NEXT: store ptr null, ptr [[TMP2]], align 4
+// CK2-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK2-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK2-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK2-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK2-32-NEXT: store i32 2, ptr [[TMP5]], align 4
+// CK2-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK2-32-NEXT: store i32 1, ptr [[TMP6]], align 4
+// CK2-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK2-32-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4
+// CK2-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK2-32-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
+// CK2-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK2-32-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 4
+// CK2-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK2-32-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 4
+// CK2-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK2-32-NEXT: store ptr null, ptr [[TMP11]], align 4
+// CK2-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK2-32-NEXT: store ptr null, ptr [[TMP12]], align 4
+// CK2-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK2-32-NEXT: store i64 0, ptr [[TMP13]], align 8
+// CK2-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK2-32-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK2-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP15]], align 4
+// CK2-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK2-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
+// CK2-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK2-32-NEXT: store i32 0, ptr [[TMP17]], align 4
+// CK2-32-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112.region_id, ptr [[KERNEL_ARGS]])
+// CK2-32-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
+// CK2-32-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK2-32: omp_offload.failed:
+// CK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112(ptr [[THIS1]]) #[[ATTR3:[0-9]+]]
+// CK2-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK2-32: omp_offload.cont:
+// CK2-32-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK2-32-NEXT: [[TMP20:%.*]] = load ptr, ptr [[B]], align 4
+// CK2-32-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[B]], i32 1
+// CK2-32-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+// CK2-32-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[B]] to i64
+// CK2-32-NEXT: [[TMP24:%.*]] = sub i64 [[TMP22]], [[TMP23]]
+// CK2-32-NEXT: [[TMP25:%.*]] = sdiv exact i64 [[TMP24]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK2-32-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.1, i32 16, i1 false)
+// CK2-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK2-32-NEXT: store ptr [[THIS1]], ptr [[TMP26]], align 4
+// CK2-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK2-32-NEXT: store ptr [[B]], ptr [[TMP27]], align 4
+// CK2-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK2-32-NEXT: store i64 [[TMP25]], ptr [[TMP28]], align 4
+// CK2-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
+// CK2-32-NEXT: store ptr null, ptr [[TMP29]], align 4
+// CK2-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
+// CK2-32-NEXT: store ptr [[THIS1]], ptr [[TMP30]], align 4
+// CK2-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
+// CK2-32-NEXT: store ptr [[TMP20]], ptr [[TMP31]], align 4
+// CK2-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
+// CK2-32-NEXT: store ptr null, ptr [[TMP32]], align 4
+// CK2-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK2-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK2-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK2-32-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK2-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
+// CK2-32-NEXT: store i32 2, ptr [[TMP36]], align 4
+// CK2-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
+// CK2-32-NEXT: store i32 2, ptr [[TMP37]], align 4
+// CK2-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
+// CK2-32-NEXT: store ptr [[TMP33]], ptr [[TMP38]], align 4
+// CK2-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
+// CK2-32-NEXT: store ptr [[TMP34]], ptr [[TMP39]], align 4
+// CK2-32-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
+// CK2-32-NEXT: store ptr [[TMP35]], ptr [[TMP40]], align 4
+// CK2-32-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
+// CK2-32-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP41]], align 4
+// CK2-32-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
+// CK2-32-NEXT: store ptr null, ptr [[TMP42]], align 4
+// CK2-32-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
+// CK2-32-NEXT: store ptr null, ptr [[TMP43]], align 4
+// CK2-32-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
+// CK2-32-NEXT: store i64 0, ptr [[TMP44]], align 8
+// CK2-32-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
+// CK2-32-NEXT: store i64 0, ptr [[TMP45]], align 8
+// CK2-32-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
+// CK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP46]], align 4
+// CK2-32-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
+// CK2-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4
+// CK2-32-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
+// CK2-32-NEXT: store i32 0, ptr [[TMP48]], align 4
+// CK2-32-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118.region_id, ptr [[KERNEL_ARGS5]])
+// CK2-32-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
+// CK2-32-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CK2-32: omp_offload.failed6:
+// CK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118(ptr [[THIS1]]) #[[ATTR3]]
+// CK2-32-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CK2-32: omp_offload.cont7:
+// CK2-32-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
+// CK2-32-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK2-32-NEXT: [[TMP51:%.*]] = load ptr, ptr [[B9]], align 4
+// CK2-32-NEXT: [[TMP52:%.*]] = getelementptr ptr, ptr [[B9]], i32 1
+// CK2-32-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[TMP52]] to i64
+// CK2-32-NEXT: [[TMP54:%.*]] = ptrtoint ptr [[A8]] to i64
+// CK2-32-NEXT: [[TMP55:%.*]] = sub i64 [[TMP53]], [[TMP54]]
+// CK2-32-NEXT: [[TMP56:%.*]] = sdiv exact i64 [[TMP55]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK2-32-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES13]], ptr align 4 @.offload_sizes.3, i32 24, i1 false)
+// CK2-32-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK2-32-NEXT: store ptr [[THIS1]], ptr [[TMP57]], align 4
+// CK2-32-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK2-32-NEXT: store ptr [[A8]], ptr [[TMP58]], align 4
+// CK2-32-NEXT: [[TMP59:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK2-32-NEXT: store i64 [[TMP56]], ptr [[TMP59]], align 4
+// CK2-32-NEXT: [[TMP60:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 0
+// CK2-32-NEXT: store ptr null, ptr [[TMP60]], align 4
+// CK2-32-NEXT: [[TMP61:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
+// CK2-32-NEXT: store ptr [[THIS1]], ptr [[TMP61]], align 4
+// CK2-32-NEXT: [[TMP62:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
+// CK2-32-NEXT: store ptr [[A8]], ptr [[TMP62]], align 4
+// CK2-32-NEXT: [[TMP63:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 1
+// CK2-32-NEXT: store ptr null, ptr [[TMP63]], align 4
+// CK2-32-NEXT: [[TMP64:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 2
+// CK2-32-NEXT: store ptr [[THIS1]], ptr [[TMP64]], align 4
+// CK2-32-NEXT: [[TMP65:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 2
+// CK2-32-NEXT: store ptr [[TMP51]], ptr [[TMP65]], align 4
+// CK2-32-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 2
+// CK2-32-NEXT: store ptr null, ptr [[TMP66]], align 4
+// CK2-32-NEXT: [[TMP67:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK2-32-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK2-32-NEXT: [[TMP69:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK2-32-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK2-32-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
+// CK2-32-NEXT: store i32 2, ptr [[TMP70]], align 4
+// CK2-32-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
+// CK2-32-NEXT: store i32 3, ptr [[TMP71]], align 4
+// CK2-32-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
+// CK2-32-NEXT: store ptr [[TMP67]], ptr [[TMP72]], align 4
+// CK2-32-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
+// CK2-32-NEXT: store ptr [[TMP68]], ptr [[TMP73]], align 4
+// CK2-32-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
+// CK2-32-NEXT: store ptr [[TMP69]], ptr [[TMP74]], align 4
+// CK2-32-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
+// CK2-32-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP75]], align 4
+// CK2-32-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
+// CK2-32-NEXT: store ptr null, ptr [[TMP76]], align 4
+// CK2-32-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
+// CK2-32-NEXT: store ptr null, ptr [[TMP77]], align 4
+// CK2-32-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
+// CK2-32-NEXT: store i64 0, ptr [[TMP78]], align 8
+// CK2-32-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
+// CK2-32-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK2-32-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
+// CK2-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP80]], align 4
+// CK2-32-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
+// CK2-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP81]], align 4
+// CK2-32-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
+// CK2-32-NEXT: store i32 0, ptr [[TMP82]], align 4
+// CK2-32-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125.region_id, ptr [[KERNEL_ARGS14]])
+// CK2-32-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0
+// CK2-32-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
+// CK2-32: omp_offload.failed15:
+// CK2-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125(ptr [[THIS1]]) #[[ATTR3]]
+// CK2-32-NEXT: br label [[OMP_OFFLOAD_CONT16]]
+// CK2-32: omp_offload.cont16:
+// CK2-32-NEXT: ret void
+// CK2-32-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
+// CK2-32-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
+// CK2-32-NEXT: entry:
+// CK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK2-32-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// CK2-32-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// CK2-32-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK2-32-NEXT: store ptr null, ptr [[A]], align 4
+// CK2-32-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK2-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// CK2-32-NEXT: store ptr [[TMP0]], ptr [[B2]], align 4
+// CK2-32-NEXT: ret void
+// CK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112
+// CK2-32-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] {
+// CK2-32-NEXT: entry:
+// CK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK2-32-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK2-32-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 4
+// CK2-32-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK2-32-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 4
+// CK2-32-NEXT: ret void
+// CK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118
+// CK2-32-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK2-32-NEXT: entry:
+// CK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK2-32-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 1
+// CK2-32-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B]], align 4
+// CK2-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CK2-32-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 1
+// CK2-32-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP1]], align 4
+// CK2-32-NEXT: ret void
+// CK2-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125
+// CK2-32-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK2-32-NEXT: entry:
+// CK2-32-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK2-32-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK2-32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK2-32-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 4
+// CK2-32-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK2-32-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 4
+// CK2-32-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP0]], i32 0, i32 1
+// CK2-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B]], align 4
+// CK2-32-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CK2-32-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 1
+// CK2-32-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP2]], align 4
+// CK2-32-NEXT: ret void
+// CK2-32-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK2-32-SAME: () #[[ATTR5:[0-9]+]] {
+// CK2-32-NEXT: entry:
+// CK2-32-NEXT: call void @__tgt_register_requires(i64 1)
+// CK2-32-NEXT: ret void
+// CK3-64-LABEL: define {{[^@]+}}@_Z3barv
+// CK3-64-SAME: () #[[ATTR0:[0-9]+]] {
+// CK3-64-NEXT: entry:
+// CK3-64-NEXT: [[PTR:%.*]] = alloca ptr, align 64
+// CK3-64-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
+// CK3-64-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
+// CK3-64-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
+// CK3-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR]], align 64
+// CK3-64-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK3-64-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8
+// CK3-64-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK3-64-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 8
+// CK3-64-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CK3-64-NEXT: store ptr null, ptr [[TMP3]], align 8
+// CK3-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK3-64-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK3-64-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK3-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK3-64-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK3-64-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK3-64-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK3-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK3-64-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
+// CK3-64-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK3-64-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8
+// CK3-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK3-64-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 8
+// CK3-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK3-64-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 8
+// CK3-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK3-64-NEXT: store ptr null, ptr [[TMP12]], align 8
+// CK3-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK3-64-NEXT: store ptr null, ptr [[TMP13]], align 8
+// CK3-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK3-64-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK3-64-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK3-64-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK3-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK3-64-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK3-64-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK3-64-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK3-64-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK3-64-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK3-64-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159.region_id, ptr [[KERNEL_ARGS]])
+// CK3-64-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK3-64-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK3-64: omp_offload.failed:
+// CK3-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK3-64-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK3-64: omp_offload.cont:
+// CK3-64-NEXT: ret void
+// CK3-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159
+// CK3-64-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK3-64-NEXT: entry:
+// CK3-64-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
+// CK3-64-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
+// CK3-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
+// CK3-64-NEXT: store double 0.000000e+00, ptr [[TMP0]], align 8
+// CK3-64-NEXT: ret void
+// CK3-64-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK3-64-SAME: () #[[ATTR3:[0-9]+]] {
+// CK3-64-NEXT: entry:
+// CK3-64-NEXT: call void @__tgt_register_requires(i64 1)
+// CK3-64-NEXT: ret void
+// CK3-32-LABEL: define {{[^@]+}}@_Z3barv
+// CK3-32-SAME: () #[[ATTR0:[0-9]+]] {
+// CK3-32-NEXT: entry:
+// CK3-32-NEXT: [[PTR:%.*]] = alloca ptr, align 64
+// CK3-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
+// CK3-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
+// CK3-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
+// CK3-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR]], align 64
+// CK3-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK3-32-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 4
+// CK3-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK3-32-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 4
+// CK3-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CK3-32-NEXT: store ptr null, ptr [[TMP3]], align 4
+// CK3-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK3-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK3-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK3-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK3-32-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK3-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK3-32-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK3-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK3-32-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
+// CK3-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK3-32-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4
+// CK3-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK3-32-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 4
+// CK3-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK3-32-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 4
+// CK3-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK3-32-NEXT: store ptr null, ptr [[TMP12]], align 4
+// CK3-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK3-32-NEXT: store ptr null, ptr [[TMP13]], align 4
+// CK3-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK3-32-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK3-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK3-32-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK3-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK3-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK3-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK3-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK3-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK3-32-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK3-32-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159.region_id, ptr [[KERNEL_ARGS]])
+// CK3-32-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK3-32-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK3-32: omp_offload.failed:
+// CK3-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK3-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK3-32: omp_offload.cont:
+// CK3-32-NEXT: ret void
+// CK3-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159
+// CK3-32-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK3-32-NEXT: entry:
+// CK3-32-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4
+// CK3-32-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4
+// CK3-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4
+// CK3-32-NEXT: store double 0.000000e+00, ptr [[TMP0]], align 4
+// CK3-32-NEXT: ret void
+// CK3-32-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK3-32-SAME: () #[[ATTR3:[0-9]+]] {
+// CK3-32-NEXT: entry:
+// CK3-32-NEXT: call void @__tgt_register_requires(i64 1)
+// CK3-32-NEXT: ret void
+// CK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK1-SAME: () #[[ATTR3:[0-9]+]] {
+// CK1-NEXT: entry:
+// CK1-NEXT: call void @__tgt_register_requires(i64 1)
+// CK1-NEXT: ret void
+// CK1-32-LABEL: define {{[^@]+}}@_Z3barRPfRPi
+// CK1-32-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK1-32-NEXT: entry:
+// CK1-32-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// CK1-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
+// CK1-32-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// CK1-32-NEXT: call void @_Z3fooIiEvRPfRPT_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]])
+// CK1-32-NEXT: ret void
+// CK1-32-LABEL: define {{[^@]+}}@_Z3fooIiEvRPfRPT_
+// CK1-32-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TR:%.*]]) #[[ATTR0]] comdat {
+// CK1-32-NEXT: entry:
+// CK1-32-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[L:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[T:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[_TMP19:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[_TMP26:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x ptr], align 4
+// CK1-32-NEXT: [[_TMP33:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[_TMP34:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_BASEPTRS35:%.*]] = alloca [2 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_PTRS36:%.*]] = alloca [2 x ptr], align 4
+// CK1-32-NEXT: [[DOTOFFLOAD_MAPPERS37:%.*]] = alloca [2 x ptr], align 4
+// CK1-32-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK1-32-NEXT: [[TMP0:%.*]] = load ptr, ptr @g, align 4
+// CK1-32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 4
+// CK1-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 4
+// CK1-32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CK1-32-NEXT: store ptr null, ptr [[TMP3]], align 4
+// CK1-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK1-32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK1-32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK1-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK1-32-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK1-32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK1-32-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK1-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK1-32-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
+// CK1-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK1-32-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4
+// CK1-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK1-32-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 4
+// CK1-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK1-32-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 4
+// CK1-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK1-32-NEXT: store ptr null, ptr [[TMP12]], align 4
+// CK1-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK1-32-NEXT: store ptr null, ptr [[TMP13]], align 4
+// CK1-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK1-32-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK1-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK1-32-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK1-32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK1-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK1-32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK1-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK1-32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK1-32-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK1-32-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37.region_id, ptr [[KERNEL_ARGS]])
+// CK1-32-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK1-32-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK1-32: omp_offload.failed:
+// CK1-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK1-32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK1-32: omp_offload.cont:
+// CK1-32-NEXT: [[TMP21:%.*]] = load ptr, ptr [[L]], align 4
+// CK1-32-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP21]], ptr [[TMP22]], align 4
+// CK1-32-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP21]], ptr [[TMP23]], align 4
+// CK1-32-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0
+// CK1-32-NEXT: store ptr null, ptr [[TMP24]], align 4
+// CK1-32-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK1-32-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK1-32-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-32-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0
+// CK1-32-NEXT: store i32 2, ptr [[TMP27]], align 4
+// CK1-32-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1
+// CK1-32-NEXT: store i32 1, ptr [[TMP28]], align 4
+// CK1-32-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2
+// CK1-32-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 4
+// CK1-32-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3
+// CK1-32-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 4
+// CK1-32-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4
+// CK1-32-NEXT: store ptr @.offload_sizes.1, ptr [[TMP31]], align 4
+// CK1-32-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5
+// CK1-32-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP32]], align 4
+// CK1-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6
+// CK1-32-NEXT: store ptr null, ptr [[TMP33]], align 4
+// CK1-32-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7
+// CK1-32-NEXT: store ptr null, ptr [[TMP34]], align 4
+// CK1-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8
+// CK1-32-NEXT: store i64 0, ptr [[TMP35]], align 8
+// CK1-32-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9
+// CK1-32-NEXT: store i64 0, ptr [[TMP36]], align 8
+// CK1-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10
+// CK1-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP37]], align 4
+// CK1-32-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11
+// CK1-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 4
+// CK1-32-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12
+// CK1-32-NEXT: store i32 0, ptr [[TMP39]], align 4
+// CK1-32-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43.region_id, ptr [[KERNEL_ARGS4]])
+// CK1-32-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
+// CK1-32-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
+// CK1-32: omp_offload.failed5:
+// CK1-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43(ptr [[TMP21]]) #[[ATTR2]]
+// CK1-32-NEXT: br label [[OMP_OFFLOAD_CONT6]]
+// CK1-32: omp_offload.cont6:
+// CK1-32-NEXT: [[TMP42:%.*]] = load ptr, ptr [[T]], align 4
+// CK1-32-NEXT: [[TMP43:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP42]], ptr [[TMP43]], align 4
+// CK1-32-NEXT: [[TMP44:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP42]], ptr [[TMP44]], align 4
+// CK1-32-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0
+// CK1-32-NEXT: store ptr null, ptr [[TMP45]], align 4
+// CK1-32-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK1-32-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK1-32-NEXT: [[KERNEL_ARGS10:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-32-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 0
+// CK1-32-NEXT: store i32 2, ptr [[TMP48]], align 4
+// CK1-32-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 1
+// CK1-32-NEXT: store i32 1, ptr [[TMP49]], align 4
+// CK1-32-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 2
+// CK1-32-NEXT: store ptr [[TMP46]], ptr [[TMP50]], align 4
+// CK1-32-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 3
+// CK1-32-NEXT: store ptr [[TMP47]], ptr [[TMP51]], align 4
+// CK1-32-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 4
+// CK1-32-NEXT: store ptr @.offload_sizes.3, ptr [[TMP52]], align 4
+// CK1-32-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 5
+// CK1-32-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP53]], align 4
+// CK1-32-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 6
+// CK1-32-NEXT: store ptr null, ptr [[TMP54]], align 4
+// CK1-32-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 7
+// CK1-32-NEXT: store ptr null, ptr [[TMP55]], align 4
+// CK1-32-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 8
+// CK1-32-NEXT: store i64 0, ptr [[TMP56]], align 8
+// CK1-32-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 9
+// CK1-32-NEXT: store i64 0, ptr [[TMP57]], align 8
+// CK1-32-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 10
+// CK1-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP58]], align 4
+// CK1-32-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 11
+// CK1-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP59]], align 4
+// CK1-32-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 12
+// CK1-32-NEXT: store i32 0, ptr [[TMP60]], align 4
+// CK1-32-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49.region_id, ptr [[KERNEL_ARGS10]])
+// CK1-32-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0
+// CK1-32-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
+// CK1-32: omp_offload.failed11:
+// CK1-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49(ptr [[TMP42]]) #[[ATTR2]]
+// CK1-32-NEXT: br label [[OMP_OFFLOAD_CONT12]]
+// CK1-32: omp_offload.cont12:
+// CK1-32-NEXT: [[TMP63:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[TMP63]], ptr [[TMP]], align 4
+// CK1-32-NEXT: [[TMP64:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK1-32-NEXT: [[TMP65:%.*]] = load ptr, ptr [[TMP64]], align 4
+// CK1-32-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP65]], ptr [[TMP66]], align 4
+// CK1-32-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP65]], ptr [[TMP67]], align 4
+// CK1-32-NEXT: [[TMP68:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
+// CK1-32-NEXT: store ptr null, ptr [[TMP68]], align 4
+// CK1-32-NEXT: [[TMP69:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK1-32-NEXT: [[TMP70:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK1-32-NEXT: [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-32-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 0
+// CK1-32-NEXT: store i32 2, ptr [[TMP71]], align 4
+// CK1-32-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 1
+// CK1-32-NEXT: store i32 1, ptr [[TMP72]], align 4
+// CK1-32-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 2
+// CK1-32-NEXT: store ptr [[TMP69]], ptr [[TMP73]], align 4
+// CK1-32-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 3
+// CK1-32-NEXT: store ptr [[TMP70]], ptr [[TMP74]], align 4
+// CK1-32-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 4
+// CK1-32-NEXT: store ptr @.offload_sizes.5, ptr [[TMP75]], align 4
+// CK1-32-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 5
+// CK1-32-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP76]], align 4
+// CK1-32-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 6
+// CK1-32-NEXT: store ptr null, ptr [[TMP77]], align 4
+// CK1-32-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 7
+// CK1-32-NEXT: store ptr null, ptr [[TMP78]], align 4
+// CK1-32-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 8
+// CK1-32-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK1-32-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 9
+// CK1-32-NEXT: store i64 0, ptr [[TMP80]], align 8
+// CK1-32-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 10
+// CK1-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP81]], align 4
+// CK1-32-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 11
+// CK1-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP82]], align 4
+// CK1-32-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 12
+// CK1-32-NEXT: store i32 0, ptr [[TMP83]], align 4
+// CK1-32-NEXT: [[TMP84:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55.region_id, ptr [[KERNEL_ARGS16]])
+// CK1-32-NEXT: [[TMP85:%.*]] = icmp ne i32 [[TMP84]], 0
+// CK1-32-NEXT: br i1 [[TMP85]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
+// CK1-32: omp_offload.failed17:
+// CK1-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55(ptr [[TMP65]]) #[[ATTR2]]
+// CK1-32-NEXT: br label [[OMP_OFFLOAD_CONT18]]
+// CK1-32: omp_offload.cont18:
+// CK1-32-NEXT: [[TMP86:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[TMP86]], ptr [[_TMP19]], align 4
+// CK1-32-NEXT: [[TMP87:%.*]] = load ptr, ptr [[_TMP19]], align 4
+// CK1-32-NEXT: [[TMP88:%.*]] = load ptr, ptr [[TMP87]], align 4
+// CK1-32-NEXT: [[TMP89:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP88]], ptr [[TMP89]], align 4
+// CK1-32-NEXT: [[TMP90:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP88]], ptr [[TMP90]], align 4
+// CK1-32-NEXT: [[TMP91:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0
+// CK1-32-NEXT: store ptr null, ptr [[TMP91]], align 4
+// CK1-32-NEXT: [[TMP92:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK1-32-NEXT: [[TMP93:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK1-32-NEXT: [[KERNEL_ARGS23:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-32-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 0
+// CK1-32-NEXT: store i32 2, ptr [[TMP94]], align 4
+// CK1-32-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 1
+// CK1-32-NEXT: store i32 1, ptr [[TMP95]], align 4
+// CK1-32-NEXT: [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 2
+// CK1-32-NEXT: store ptr [[TMP92]], ptr [[TMP96]], align 4
+// CK1-32-NEXT: [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 3
+// CK1-32-NEXT: store ptr [[TMP93]], ptr [[TMP97]], align 4
+// CK1-32-NEXT: [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 4
+// CK1-32-NEXT: store ptr @.offload_sizes.7, ptr [[TMP98]], align 4
+// CK1-32-NEXT: [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 5
+// CK1-32-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP99]], align 4
+// CK1-32-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 6
+// CK1-32-NEXT: store ptr null, ptr [[TMP100]], align 4
+// CK1-32-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 7
+// CK1-32-NEXT: store ptr null, ptr [[TMP101]], align 4
+// CK1-32-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 8
+// CK1-32-NEXT: store i64 0, ptr [[TMP102]], align 8
+// CK1-32-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 9
+// CK1-32-NEXT: store i64 0, ptr [[TMP103]], align 8
+// CK1-32-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 10
+// CK1-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP104]], align 4
+// CK1-32-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 11
+// CK1-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP105]], align 4
+// CK1-32-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 12
+// CK1-32-NEXT: store i32 0, ptr [[TMP106]], align 4
+// CK1-32-NEXT: [[TMP107:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61.region_id, ptr [[KERNEL_ARGS23]])
+// CK1-32-NEXT: [[TMP108:%.*]] = icmp ne i32 [[TMP107]], 0
+// CK1-32-NEXT: br i1 [[TMP108]], label [[OMP_OFFLOAD_FAILED24:%.*]], label [[OMP_OFFLOAD_CONT25:%.*]]
+// CK1-32: omp_offload.failed24:
+// CK1-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61(ptr [[TMP88]]) #[[ATTR2]]
+// CK1-32-NEXT: br label [[OMP_OFFLOAD_CONT25]]
+// CK1-32: omp_offload.cont25:
+// CK1-32-NEXT: [[TMP109:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[TMP109]], ptr [[_TMP26]], align 4
+// CK1-32-NEXT: [[TMP110:%.*]] = load ptr, ptr [[_TMP26]], align 4
+// CK1-32-NEXT: [[TMP111:%.*]] = load ptr, ptr [[TMP110]], align 4
+// CK1-32-NEXT: [[TMP112:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP111]], ptr [[TMP112]], align 4
+// CK1-32-NEXT: [[TMP113:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP111]], ptr [[TMP113]], align 4
+// CK1-32-NEXT: [[TMP114:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0
+// CK1-32-NEXT: store ptr null, ptr [[TMP114]], align 4
+// CK1-32-NEXT: [[TMP115:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK1-32-NEXT: [[TMP116:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK1-32-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-32-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 0
+// CK1-32-NEXT: store i32 2, ptr [[TMP117]], align 4
+// CK1-32-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 1
+// CK1-32-NEXT: store i32 1, ptr [[TMP118]], align 4
+// CK1-32-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 2
+// CK1-32-NEXT: store ptr [[TMP115]], ptr [[TMP119]], align 4
+// CK1-32-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 3
+// CK1-32-NEXT: store ptr [[TMP116]], ptr [[TMP120]], align 4
+// CK1-32-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 4
+// CK1-32-NEXT: store ptr @.offload_sizes.9, ptr [[TMP121]], align 4
+// CK1-32-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 5
+// CK1-32-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP122]], align 4
+// CK1-32-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 6
+// CK1-32-NEXT: store ptr null, ptr [[TMP123]], align 4
+// CK1-32-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 7
+// CK1-32-NEXT: store ptr null, ptr [[TMP124]], align 4
+// CK1-32-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 8
+// CK1-32-NEXT: store i64 0, ptr [[TMP125]], align 8
+// CK1-32-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 9
+// CK1-32-NEXT: store i64 0, ptr [[TMP126]], align 8
+// CK1-32-NEXT: [[TMP127:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 10
+// CK1-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP127]], align 4
+// CK1-32-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 11
+// CK1-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP128]], align 4
+// CK1-32-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 12
+// CK1-32-NEXT: store i32 0, ptr [[TMP129]], align 4
+// CK1-32-NEXT: [[TMP130:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67.region_id, ptr [[KERNEL_ARGS30]])
+// CK1-32-NEXT: [[TMP131:%.*]] = icmp ne i32 [[TMP130]], 0
+// CK1-32-NEXT: br i1 [[TMP131]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]]
+// CK1-32: omp_offload.failed31:
+// CK1-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67(ptr [[TMP111]]) #[[ATTR2]]
+// CK1-32-NEXT: br label [[OMP_OFFLOAD_CONT32]]
+// CK1-32: omp_offload.cont32:
+// CK1-32-NEXT: [[TMP132:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[TMP132]], ptr [[_TMP33]], align 4
+// CK1-32-NEXT: [[TMP133:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[TMP133]], ptr [[_TMP34]], align 4
+// CK1-32-NEXT: [[TMP134:%.*]] = load ptr, ptr [[_TMP33]], align 4
+// CK1-32-NEXT: [[TMP135:%.*]] = load ptr, ptr [[TMP134]], align 4
+// CK1-32-NEXT: [[TMP136:%.*]] = load ptr, ptr [[_TMP34]], align 4
+// CK1-32-NEXT: [[TMP137:%.*]] = load ptr, ptr [[TMP136]], align 4
+// CK1-32-NEXT: [[TMP138:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP135]], ptr [[TMP138]], align 4
+// CK1-32-NEXT: [[TMP139:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK1-32-NEXT: store ptr [[TMP135]], ptr [[TMP139]], align 4
+// CK1-32-NEXT: [[TMP140:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i32 0, i32 0
+// CK1-32-NEXT: store ptr null, ptr [[TMP140]], align 4
+// CK1-32-NEXT: [[TMP141:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 1
+// CK1-32-NEXT: store ptr [[TMP137]], ptr [[TMP141]], align 4
+// CK1-32-NEXT: [[TMP142:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 1
+// CK1-32-NEXT: store ptr [[TMP137]], ptr [[TMP142]], align 4
+// CK1-32-NEXT: [[TMP143:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i32 0, i32 1
+// CK1-32-NEXT: store ptr null, ptr [[TMP143]], align 4
+// CK1-32-NEXT: [[TMP144:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK1-32-NEXT: [[TMP145:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK1-32-NEXT: [[KERNEL_ARGS38:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK1-32-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 0
+// CK1-32-NEXT: store i32 2, ptr [[TMP146]], align 4
+// CK1-32-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 1
+// CK1-32-NEXT: store i32 2, ptr [[TMP147]], align 4
+// CK1-32-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 2
+// CK1-32-NEXT: store ptr [[TMP144]], ptr [[TMP148]], align 4
+// CK1-32-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 3
+// CK1-32-NEXT: store ptr [[TMP145]], ptr [[TMP149]], align 4
+// CK1-32-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 4
+// CK1-32-NEXT: store ptr @.offload_sizes.11, ptr [[TMP150]], align 4
+// CK1-32-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 5
+// CK1-32-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP151]], align 4
+// CK1-32-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 6
+// CK1-32-NEXT: store ptr null, ptr [[TMP152]], align 4
+// CK1-32-NEXT: [[TMP153:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 7
+// CK1-32-NEXT: store ptr null, ptr [[TMP153]], align 4
+// CK1-32-NEXT: [[TMP154:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 8
+// CK1-32-NEXT: store i64 0, ptr [[TMP154]], align 8
+// CK1-32-NEXT: [[TMP155:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 9
+// CK1-32-NEXT: store i64 0, ptr [[TMP155]], align 8
+// CK1-32-NEXT: [[TMP156:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 10
+// CK1-32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP156]], align 4
+// CK1-32-NEXT: [[TMP157:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 11
+// CK1-32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP157]], align 4
+// CK1-32-NEXT: [[TMP158:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 12
+// CK1-32-NEXT: store i32 0, ptr [[TMP158]], align 4
+// CK1-32-NEXT: [[TMP159:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74.region_id, ptr [[KERNEL_ARGS38]])
+// CK1-32-NEXT: [[TMP160:%.*]] = icmp ne i32 [[TMP159]], 0
+// CK1-32-NEXT: br i1 [[TMP160]], label [[OMP_OFFLOAD_FAILED39:%.*]], label [[OMP_OFFLOAD_CONT40:%.*]]
+// CK1-32: omp_offload.failed39:
+// CK1-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74(ptr [[TMP135]], ptr [[TMP137]]) #[[ATTR2]]
+// CK1-32-NEXT: br label [[OMP_OFFLOAD_CONT40]]
+// CK1-32: omp_offload.cont40:
+// CK1-32-NEXT: ret void
+// CK1-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37
+// CK1-32-SAME: (ptr noundef [[G:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK1-32-NEXT: entry:
+// CK1-32-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
+// CK1-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
+// CK1-32-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK1-32-NEXT: store ptr [[INCDEC_PTR]], ptr [[G_ADDR]], align 4
+// CK1-32-NEXT: ret void
+// CK1-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43
+// CK1-32-SAME: (ptr noundef [[L:%.*]]) #[[ATTR1]] {
+// CK1-32-NEXT: entry:
+// CK1-32-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 4
+// CK1-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[L_ADDR]], align 4
+// CK1-32-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i32 1
+// CK1-32-NEXT: store ptr [[INCDEC_PTR]], ptr [[L_ADDR]], align 4
+// CK1-32-NEXT: ret void
+// CK1-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49
+// CK1-32-SAME: (ptr noundef [[T:%.*]]) #[[ATTR1]] {
+// CK1-32-NEXT: entry:
+// CK1-32-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 4
+// CK1-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 4
+// CK1-32-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
+// CK1-32-NEXT: store ptr [[INCDEC_PTR]], ptr [[T_ADDR]], align 4
+// CK1-32-NEXT: ret void
+// CK1-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55
+// CK1-32-SAME: (ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK1-32-NEXT: entry:
+// CK1-32-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[LR_ADDR]], ptr [[TMP]], align 4
+// CK1-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK1-32-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK1-32-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 1
+// CK1-32-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK1-32-NEXT: ret void
+// CK1-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61
+// CK1-32-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK1-32-NEXT: entry:
+// CK1-32-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 4
+// CK1-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK1-32-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK1-32-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK1-32-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK1-32-NEXT: ret void
+// CK1-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67
+// CK1-32-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK1-32-NEXT: entry:
+// CK1-32-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 4
+// CK1-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK1-32-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK1-32-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK1-32-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK1-32-NEXT: ret void
+// CK1-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74
+// CK1-32-SAME: (ptr noundef [[TR:%.*]], ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK1-32-NEXT: entry:
+// CK1-32-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4
+// CK1-32-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 4
+// CK1-32-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 4
+// CK1-32-NEXT: store ptr [[LR_ADDR]], ptr [[_TMP1]], align 4
+// CK1-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK1-32-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK1-32-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK1-32-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK1-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 4
+// CK1-32-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CK1-32-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i32 1
+// CK1-32-NEXT: store ptr [[INCDEC_PTR2]], ptr [[TMP2]], align 4
+// CK1-32-NEXT: ret void
+// CK1-32-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK1-32-SAME: () #[[ATTR3:[0-9]+]] {
+// CK1-32-NEXT: entry:
+// CK1-32-NEXT: call void @__tgt_register_requires(i64 1)
+// CK1-32-NEXT: ret void
+// CK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK2-SAME: () #[[ATTR5:[0-9]+]] {
+// CK2-NEXT: entry:
+// CK2-NEXT: call void @__tgt_register_requires(i64 1)
+// CK2-NEXT: ret void
+// CK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK3-SAME: () #[[ATTR3:[0-9]+]] {
+// CK3-NEXT: entry:
+// CK3-NEXT: call void @__tgt_register_requires(i64 1)
+// CK3-NEXT: ret void
+// CK10-LABEL: define {{[^@]+}}@_Z3barRPfRPi
+// CK10-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK10-NEXT: entry:
+// CK10-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
+// CK10-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// CK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// CK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// CK10-NEXT: call void @_Z3fooIiEvRPfRPT_(ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP1]])
+// CK10-NEXT: ret void
+//
+//
+// CK10-LABEL: define {{[^@]+}}@_Z3fooIiEvRPfRPT_
+// CK10-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[LR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[TR:%.*]]) #[[ATTR0]] comdat {
+// CK10-NEXT: entry:
+// CK10-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[L:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[T:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK10-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK10-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[KERNEL_ARGS10:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK10-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK10-NEXT: [[_TMP19:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[KERNEL_ARGS23:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK10-NEXT: [[_TMP26:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x ptr], align 8
+// CK10-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK10-NEXT: [[_TMP33:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[_TMP34:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[DOTOFFLOAD_BASEPTRS35:%.*]] = alloca [2 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_PTRS36:%.*]] = alloca [2 x ptr], align 8
+// CK10-NEXT: [[DOTOFFLOAD_MAPPERS37:%.*]] = alloca [2 x ptr], align 8
+// CK10-NEXT: [[KERNEL_ARGS38:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK10-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 8
+// CK10-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK10-NEXT: [[TMP0:%.*]] = load ptr, ptr @g, align 8
+// CK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8
+// CK10-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 8
+// CK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CK10-NEXT: store ptr null, ptr [[TMP3]], align 8
+// CK10-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK10-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK10-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK10-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
+// CK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK10-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8
+// CK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK10-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 8
+// CK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK10-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 8
+// CK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK10-NEXT: store ptr null, ptr [[TMP12]], align 8
+// CK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK10-NEXT: store ptr null, ptr [[TMP13]], align 8
+// CK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK10-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK10-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK10-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK10-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK10-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37.region_id, ptr [[KERNEL_ARGS]])
+// CK10-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK10-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK10: omp_offload.failed:
+// CK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK10-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK10: omp_offload.cont:
+// CK10-NEXT: [[TMP21:%.*]] = load ptr, ptr [[L]], align 8
+// CK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP21]], ptr [[TMP22]], align 8
+// CK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP21]], ptr [[TMP23]], align 8
+// CK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
+// CK10-NEXT: store ptr null, ptr [[TMP24]], align 8
+// CK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0
+// CK10-NEXT: store i32 2, ptr [[TMP27]], align 4
+// CK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1
+// CK10-NEXT: store i32 1, ptr [[TMP28]], align 4
+// CK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2
+// CK10-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 8
+// CK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3
+// CK10-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 8
+// CK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4
+// CK10-NEXT: store ptr @.offload_sizes.1, ptr [[TMP31]], align 8
+// CK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5
+// CK10-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP32]], align 8
+// CK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6
+// CK10-NEXT: store ptr null, ptr [[TMP33]], align 8
+// CK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7
+// CK10-NEXT: store ptr null, ptr [[TMP34]], align 8
+// CK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8
+// CK10-NEXT: store i64 0, ptr [[TMP35]], align 8
+// CK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9
+// CK10-NEXT: store i64 0, ptr [[TMP36]], align 8
+// CK10-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10
+// CK10-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP37]], align 4
+// CK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11
+// CK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 4
+// CK10-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12
+// CK10-NEXT: store i32 0, ptr [[TMP39]], align 4
+// CK10-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43.region_id, ptr [[KERNEL_ARGS4]])
+// CK10-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
+// CK10-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
+// CK10: omp_offload.failed5:
+// CK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43(ptr [[TMP21]]) #[[ATTR2]]
+// CK10-NEXT: br label [[OMP_OFFLOAD_CONT6]]
+// CK10: omp_offload.cont6:
+// CK10-NEXT: [[TMP42:%.*]] = load ptr, ptr [[T]], align 8
+// CK10-NEXT: [[TMP43:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP42]], ptr [[TMP43]], align 8
+// CK10-NEXT: [[TMP44:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP42]], ptr [[TMP44]], align 8
+// CK10-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
+// CK10-NEXT: store ptr null, ptr [[TMP45]], align 8
+// CK10-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK10-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK10-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 0
+// CK10-NEXT: store i32 2, ptr [[TMP48]], align 4
+// CK10-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 1
+// CK10-NEXT: store i32 1, ptr [[TMP49]], align 4
+// CK10-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 2
+// CK10-NEXT: store ptr [[TMP46]], ptr [[TMP50]], align 8
+// CK10-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 3
+// CK10-NEXT: store ptr [[TMP47]], ptr [[TMP51]], align 8
+// CK10-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 4
+// CK10-NEXT: store ptr @.offload_sizes.3, ptr [[TMP52]], align 8
+// CK10-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 5
+// CK10-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP53]], align 8
+// CK10-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 6
+// CK10-NEXT: store ptr null, ptr [[TMP54]], align 8
+// CK10-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 7
+// CK10-NEXT: store ptr null, ptr [[TMP55]], align 8
+// CK10-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 8
+// CK10-NEXT: store i64 0, ptr [[TMP56]], align 8
+// CK10-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 9
+// CK10-NEXT: store i64 0, ptr [[TMP57]], align 8
+// CK10-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 10
+// CK10-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP58]], align 4
+// CK10-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 11
+// CK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP59]], align 4
+// CK10-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 12
+// CK10-NEXT: store i32 0, ptr [[TMP60]], align 4
+// CK10-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49.region_id, ptr [[KERNEL_ARGS10]])
+// CK10-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0
+// CK10-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
+// CK10: omp_offload.failed11:
+// CK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49(ptr [[TMP42]]) #[[ATTR2]]
+// CK10-NEXT: br label [[OMP_OFFLOAD_CONT12]]
+// CK10: omp_offload.cont12:
+// CK10-NEXT: [[TMP63:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// CK10-NEXT: store ptr [[TMP63]], ptr [[TMP]], align 8
+// CK10-NEXT: [[TMP64:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK10-NEXT: [[TMP65:%.*]] = load ptr, ptr [[TMP64]], align 8
+// CK10-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP65]], ptr [[TMP66]], align 8
+// CK10-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP65]], ptr [[TMP67]], align 8
+// CK10-NEXT: [[TMP68:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0
+// CK10-NEXT: store ptr null, ptr [[TMP68]], align 8
+// CK10-NEXT: [[TMP69:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK10-NEXT: [[TMP70:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK10-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 0
+// CK10-NEXT: store i32 2, ptr [[TMP71]], align 4
+// CK10-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 1
+// CK10-NEXT: store i32 1, ptr [[TMP72]], align 4
+// CK10-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 2
+// CK10-NEXT: store ptr [[TMP69]], ptr [[TMP73]], align 8
+// CK10-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 3
+// CK10-NEXT: store ptr [[TMP70]], ptr [[TMP74]], align 8
+// CK10-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 4
+// CK10-NEXT: store ptr @.offload_sizes.5, ptr [[TMP75]], align 8
+// CK10-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 5
+// CK10-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP76]], align 8
+// CK10-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 6
+// CK10-NEXT: store ptr null, ptr [[TMP77]], align 8
+// CK10-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 7
+// CK10-NEXT: store ptr null, ptr [[TMP78]], align 8
+// CK10-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 8
+// CK10-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK10-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 9
+// CK10-NEXT: store i64 0, ptr [[TMP80]], align 8
+// CK10-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 10
+// CK10-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP81]], align 4
+// CK10-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 11
+// CK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP82]], align 4
+// CK10-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 12
+// CK10-NEXT: store i32 0, ptr [[TMP83]], align 4
+// CK10-NEXT: [[TMP84:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55.region_id, ptr [[KERNEL_ARGS16]])
+// CK10-NEXT: [[TMP85:%.*]] = icmp ne i32 [[TMP84]], 0
+// CK10-NEXT: br i1 [[TMP85]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
+// CK10: omp_offload.failed17:
+// CK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55(ptr [[TMP65]]) #[[ATTR2]]
+// CK10-NEXT: br label [[OMP_OFFLOAD_CONT18]]
+// CK10: omp_offload.cont18:
+// CK10-NEXT: [[TMP86:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// CK10-NEXT: store ptr [[TMP86]], ptr [[_TMP19]], align 8
+// CK10-NEXT: [[TMP87:%.*]] = load ptr, ptr [[_TMP19]], align 8
+// CK10-NEXT: [[TMP88:%.*]] = load ptr, ptr [[TMP87]], align 8
+// CK10-NEXT: [[TMP89:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP88]], ptr [[TMP89]], align 8
+// CK10-NEXT: [[TMP90:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP88]], ptr [[TMP90]], align 8
+// CK10-NEXT: [[TMP91:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
+// CK10-NEXT: store ptr null, ptr [[TMP91]], align 8
+// CK10-NEXT: [[TMP92:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK10-NEXT: [[TMP93:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK10-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 0
+// CK10-NEXT: store i32 2, ptr [[TMP94]], align 4
+// CK10-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 1
+// CK10-NEXT: store i32 1, ptr [[TMP95]], align 4
+// CK10-NEXT: [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 2
+// CK10-NEXT: store ptr [[TMP92]], ptr [[TMP96]], align 8
+// CK10-NEXT: [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 3
+// CK10-NEXT: store ptr [[TMP93]], ptr [[TMP97]], align 8
+// CK10-NEXT: [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 4
+// CK10-NEXT: store ptr @.offload_sizes.7, ptr [[TMP98]], align 8
+// CK10-NEXT: [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 5
+// CK10-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP99]], align 8
+// CK10-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 6
+// CK10-NEXT: store ptr null, ptr [[TMP100]], align 8
+// CK10-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 7
+// CK10-NEXT: store ptr null, ptr [[TMP101]], align 8
+// CK10-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 8
+// CK10-NEXT: store i64 0, ptr [[TMP102]], align 8
+// CK10-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 9
+// CK10-NEXT: store i64 0, ptr [[TMP103]], align 8
+// CK10-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 10
+// CK10-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP104]], align 4
+// CK10-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 11
+// CK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP105]], align 4
+// CK10-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 12
+// CK10-NEXT: store i32 0, ptr [[TMP106]], align 4
+// CK10-NEXT: [[TMP107:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61.region_id, ptr [[KERNEL_ARGS23]])
+// CK10-NEXT: [[TMP108:%.*]] = icmp ne i32 [[TMP107]], 0
+// CK10-NEXT: br i1 [[TMP108]], label [[OMP_OFFLOAD_FAILED24:%.*]], label [[OMP_OFFLOAD_CONT25:%.*]]
+// CK10: omp_offload.failed24:
+// CK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61(ptr [[TMP88]]) #[[ATTR2]]
+// CK10-NEXT: br label [[OMP_OFFLOAD_CONT25]]
+// CK10: omp_offload.cont25:
+// CK10-NEXT: [[TMP109:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// CK10-NEXT: store ptr [[TMP109]], ptr [[_TMP26]], align 8
+// CK10-NEXT: [[TMP110:%.*]] = load ptr, ptr [[_TMP26]], align 8
+// CK10-NEXT: [[TMP111:%.*]] = load ptr, ptr [[TMP110]], align 8
+// CK10-NEXT: [[TMP112:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP111]], ptr [[TMP112]], align 8
+// CK10-NEXT: [[TMP113:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP111]], ptr [[TMP113]], align 8
+// CK10-NEXT: [[TMP114:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 0
+// CK10-NEXT: store ptr null, ptr [[TMP114]], align 8
+// CK10-NEXT: [[TMP115:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK10-NEXT: [[TMP116:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK10-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 0
+// CK10-NEXT: store i32 2, ptr [[TMP117]], align 4
+// CK10-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 1
+// CK10-NEXT: store i32 1, ptr [[TMP118]], align 4
+// CK10-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 2
+// CK10-NEXT: store ptr [[TMP115]], ptr [[TMP119]], align 8
+// CK10-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 3
+// CK10-NEXT: store ptr [[TMP116]], ptr [[TMP120]], align 8
+// CK10-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 4
+// CK10-NEXT: store ptr @.offload_sizes.9, ptr [[TMP121]], align 8
+// CK10-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 5
+// CK10-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP122]], align 8
+// CK10-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 6
+// CK10-NEXT: store ptr null, ptr [[TMP123]], align 8
+// CK10-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 7
+// CK10-NEXT: store ptr null, ptr [[TMP124]], align 8
+// CK10-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 8
+// CK10-NEXT: store i64 0, ptr [[TMP125]], align 8
+// CK10-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 9
+// CK10-NEXT: store i64 0, ptr [[TMP126]], align 8
+// CK10-NEXT: [[TMP127:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 10
+// CK10-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP127]], align 4
+// CK10-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 11
+// CK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP128]], align 4
+// CK10-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 12
+// CK10-NEXT: store i32 0, ptr [[TMP129]], align 4
+// CK10-NEXT: [[TMP130:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67.region_id, ptr [[KERNEL_ARGS30]])
+// CK10-NEXT: [[TMP131:%.*]] = icmp ne i32 [[TMP130]], 0
+// CK10-NEXT: br i1 [[TMP131]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]]
+// CK10: omp_offload.failed31:
+// CK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67(ptr [[TMP111]]) #[[ATTR2]]
+// CK10-NEXT: br label [[OMP_OFFLOAD_CONT32]]
+// CK10: omp_offload.cont32:
+// CK10-NEXT: [[TMP132:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// CK10-NEXT: store ptr [[TMP132]], ptr [[_TMP33]], align 8
+// CK10-NEXT: [[TMP133:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// CK10-NEXT: store ptr [[TMP133]], ptr [[_TMP34]], align 8
+// CK10-NEXT: [[TMP134:%.*]] = load ptr, ptr [[_TMP33]], align 8
+// CK10-NEXT: [[TMP135:%.*]] = load ptr, ptr [[TMP134]], align 8
+// CK10-NEXT: [[TMP136:%.*]] = load ptr, ptr [[_TMP34]], align 8
+// CK10-NEXT: [[TMP137:%.*]] = load ptr, ptr [[TMP136]], align 8
+// CK10-NEXT: [[TMP138:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP135]], ptr [[TMP138]], align 8
+// CK10-NEXT: [[TMP139:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK10-NEXT: store ptr [[TMP135]], ptr [[TMP139]], align 8
+// CK10-NEXT: [[TMP140:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i64 0, i64 0
+// CK10-NEXT: store ptr null, ptr [[TMP140]], align 8
+// CK10-NEXT: [[TMP141:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 1
+// CK10-NEXT: store ptr [[TMP137]], ptr [[TMP141]], align 8
+// CK10-NEXT: [[TMP142:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 1
+// CK10-NEXT: store ptr [[TMP137]], ptr [[TMP142]], align 8
+// CK10-NEXT: [[TMP143:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i64 0, i64 1
+// CK10-NEXT: store ptr null, ptr [[TMP143]], align 8
+// CK10-NEXT: [[TMP144:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK10-NEXT: [[TMP145:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK10-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 0
+// CK10-NEXT: store i32 2, ptr [[TMP146]], align 4
+// CK10-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 1
+// CK10-NEXT: store i32 2, ptr [[TMP147]], align 4
+// CK10-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 2
+// CK10-NEXT: store ptr [[TMP144]], ptr [[TMP148]], align 8
+// CK10-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 3
+// CK10-NEXT: store ptr [[TMP145]], ptr [[TMP149]], align 8
+// CK10-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 4
+// CK10-NEXT: store ptr @.offload_sizes.11, ptr [[TMP150]], align 8
+// CK10-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 5
+// CK10-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP151]], align 8
+// CK10-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 6
+// CK10-NEXT: store ptr null, ptr [[TMP152]], align 8
+// CK10-NEXT: [[TMP153:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 7
+// CK10-NEXT: store ptr null, ptr [[TMP153]], align 8
+// CK10-NEXT: [[TMP154:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 8
+// CK10-NEXT: store i64 0, ptr [[TMP154]], align 8
+// CK10-NEXT: [[TMP155:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 9
+// CK10-NEXT: store i64 0, ptr [[TMP155]], align 8
+// CK10-NEXT: [[TMP156:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 10
+// CK10-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP156]], align 4
+// CK10-NEXT: [[TMP157:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 11
+// CK10-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP157]], align 4
+// CK10-NEXT: [[TMP158:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 12
+// CK10-NEXT: store i32 0, ptr [[TMP158]], align 4
+// CK10-NEXT: [[TMP159:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74.region_id, ptr [[KERNEL_ARGS38]])
+// CK10-NEXT: [[TMP160:%.*]] = icmp ne i32 [[TMP159]], 0
+// CK10-NEXT: br i1 [[TMP160]], label [[OMP_OFFLOAD_FAILED39:%.*]], label [[OMP_OFFLOAD_CONT40:%.*]]
+// CK10: omp_offload.failed39:
+// CK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74(ptr [[TMP135]], ptr [[TMP137]]) #[[ATTR2]]
+// CK10-NEXT: br label [[OMP_OFFLOAD_CONT40]]
+// CK10: omp_offload.cont40:
+// CK10-NEXT: ret void
+//
+//
+// CK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37
+// CK10-SAME: (ptr noundef [[G:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK10-NEXT: entry:
+// CK10-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8
+// CK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8
+// CK10-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK10-NEXT: store ptr [[INCDEC_PTR]], ptr [[G_ADDR]], align 8
+// CK10-NEXT: ret void
+//
+//
+// CK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43
+// CK10-SAME: (ptr noundef [[L:%.*]]) #[[ATTR1]] {
+// CK10-NEXT: entry:
+// CK10-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
+// CK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[L_ADDR]], align 8
+// CK10-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i32 1
+// CK10-NEXT: store ptr [[INCDEC_PTR]], ptr [[L_ADDR]], align 8
+// CK10-NEXT: ret void
+//
+//
+// CK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49
+// CK10-SAME: (ptr noundef [[T:%.*]]) #[[ATTR1]] {
+// CK10-NEXT: entry:
+// CK10-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8
+// CK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8
+// CK10-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
+// CK10-NEXT: store ptr [[INCDEC_PTR]], ptr [[T_ADDR]], align 8
+// CK10-NEXT: ret void
+//
+//
+// CK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55
+// CK10-SAME: (ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK10-NEXT: entry:
+// CK10-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK10-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 8
+// CK10-NEXT: store ptr [[LR_ADDR]], ptr [[TMP]], align 8
+// CK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK10-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 1
+// CK10-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK10-NEXT: ret void
+//
+//
+// CK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61
+// CK10-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK10-NEXT: entry:
+// CK10-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK10-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK10-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 8
+// CK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK10-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK10-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK10-NEXT: ret void
+//
+//
+// CK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67
+// CK10-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK10-NEXT: entry:
+// CK10-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK10-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK10-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 8
+// CK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK10-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK10-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK10-NEXT: ret void
+//
+//
+// CK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74
+// CK10-SAME: (ptr noundef [[TR:%.*]], ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK10-NEXT: entry:
+// CK10-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK10-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
+// CK10-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK10-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 8
+// CK10-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 8
+// CK10-NEXT: store ptr [[LR_ADDR]], ptr [[_TMP1]], align 8
+// CK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK10-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK10-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8
+// CK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CK10-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i32 1
+// CK10-NEXT: store ptr [[INCDEC_PTR2]], ptr [[TMP2]], align 8
+// CK10-NEXT: ret void
+//
+//
+// CK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK10-SAME: () #[[ATTR3:[0-9]+]] {
+// CK10-NEXT: entry:
+// CK10-NEXT: call void @__tgt_register_requires(i64 1)
+// CK10-NEXT: ret void
+//
+//
+// CK11-LABEL: define {{[^@]+}}@_Z3barRPfRPi
+// CK11-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK11-NEXT: entry:
+// CK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
+// CK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// CK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// CK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// CK11-NEXT: call void @_Z3fooIiEvRPfRPT_(ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP1]])
+// CK11-NEXT: ret void
+//
+//
+// CK11-LABEL: define {{[^@]+}}@_Z3fooIiEvRPfRPT_
+// CK11-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[LR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[TR:%.*]]) #[[ATTR0]] comdat {
+// CK11-NEXT: entry:
+// CK11-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[L:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[T:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK11-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[KERNEL_ARGS10:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK11-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK11-NEXT: [[_TMP19:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[KERNEL_ARGS23:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK11-NEXT: [[_TMP26:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x ptr], align 8
+// CK11-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK11-NEXT: [[_TMP33:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[_TMP34:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[DOTOFFLOAD_BASEPTRS35:%.*]] = alloca [2 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_PTRS36:%.*]] = alloca [2 x ptr], align 8
+// CK11-NEXT: [[DOTOFFLOAD_MAPPERS37:%.*]] = alloca [2 x ptr], align 8
+// CK11-NEXT: [[KERNEL_ARGS38:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK11-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 8
+// CK11-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK11-NEXT: [[TMP0:%.*]] = load ptr, ptr @g, align 8
+// CK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8
+// CK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 8
+// CK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CK11-NEXT: store ptr null, ptr [[TMP3]], align 8
+// CK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK11-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK11-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK11-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
+// CK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK11-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8
+// CK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK11-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 8
+// CK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK11-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 8
+// CK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK11-NEXT: store ptr null, ptr [[TMP12]], align 8
+// CK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK11-NEXT: store ptr null, ptr [[TMP13]], align 8
+// CK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK11-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK11-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK11-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK11-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK11-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37.region_id, ptr [[KERNEL_ARGS]])
+// CK11-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK11-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK11: omp_offload.failed:
+// CK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK11: omp_offload.cont:
+// CK11-NEXT: [[TMP21:%.*]] = load ptr, ptr [[L]], align 8
+// CK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP21]], ptr [[TMP22]], align 8
+// CK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP21]], ptr [[TMP23]], align 8
+// CK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
+// CK11-NEXT: store ptr null, ptr [[TMP24]], align 8
+// CK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0
+// CK11-NEXT: store i32 2, ptr [[TMP27]], align 4
+// CK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1
+// CK11-NEXT: store i32 1, ptr [[TMP28]], align 4
+// CK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2
+// CK11-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 8
+// CK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3
+// CK11-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 8
+// CK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4
+// CK11-NEXT: store ptr @.offload_sizes.1, ptr [[TMP31]], align 8
+// CK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5
+// CK11-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP32]], align 8
+// CK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6
+// CK11-NEXT: store ptr null, ptr [[TMP33]], align 8
+// CK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7
+// CK11-NEXT: store ptr null, ptr [[TMP34]], align 8
+// CK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8
+// CK11-NEXT: store i64 0, ptr [[TMP35]], align 8
+// CK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9
+// CK11-NEXT: store i64 0, ptr [[TMP36]], align 8
+// CK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10
+// CK11-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP37]], align 4
+// CK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11
+// CK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 4
+// CK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12
+// CK11-NEXT: store i32 0, ptr [[TMP39]], align 4
+// CK11-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43.region_id, ptr [[KERNEL_ARGS4]])
+// CK11-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
+// CK11-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
+// CK11: omp_offload.failed5:
+// CK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43(ptr [[TMP21]]) #[[ATTR2]]
+// CK11-NEXT: br label [[OMP_OFFLOAD_CONT6]]
+// CK11: omp_offload.cont6:
+// CK11-NEXT: [[TMP42:%.*]] = load ptr, ptr [[T]], align 8
+// CK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP42]], ptr [[TMP43]], align 8
+// CK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP42]], ptr [[TMP44]], align 8
+// CK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
+// CK11-NEXT: store ptr null, ptr [[TMP45]], align 8
+// CK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 0
+// CK11-NEXT: store i32 2, ptr [[TMP48]], align 4
+// CK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 1
+// CK11-NEXT: store i32 1, ptr [[TMP49]], align 4
+// CK11-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 2
+// CK11-NEXT: store ptr [[TMP46]], ptr [[TMP50]], align 8
+// CK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 3
+// CK11-NEXT: store ptr [[TMP47]], ptr [[TMP51]], align 8
+// CK11-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 4
+// CK11-NEXT: store ptr @.offload_sizes.3, ptr [[TMP52]], align 8
+// CK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 5
+// CK11-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP53]], align 8
+// CK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 6
+// CK11-NEXT: store ptr null, ptr [[TMP54]], align 8
+// CK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 7
+// CK11-NEXT: store ptr null, ptr [[TMP55]], align 8
+// CK11-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 8
+// CK11-NEXT: store i64 0, ptr [[TMP56]], align 8
+// CK11-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 9
+// CK11-NEXT: store i64 0, ptr [[TMP57]], align 8
+// CK11-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 10
+// CK11-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP58]], align 4
+// CK11-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 11
+// CK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP59]], align 4
+// CK11-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 12
+// CK11-NEXT: store i32 0, ptr [[TMP60]], align 4
+// CK11-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49.region_id, ptr [[KERNEL_ARGS10]])
+// CK11-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0
+// CK11-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
+// CK11: omp_offload.failed11:
+// CK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49(ptr [[TMP42]]) #[[ATTR2]]
+// CK11-NEXT: br label [[OMP_OFFLOAD_CONT12]]
+// CK11: omp_offload.cont12:
+// CK11-NEXT: [[TMP63:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// CK11-NEXT: store ptr [[TMP63]], ptr [[TMP]], align 8
+// CK11-NEXT: [[TMP64:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK11-NEXT: [[TMP65:%.*]] = load ptr, ptr [[TMP64]], align 8
+// CK11-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP65]], ptr [[TMP66]], align 8
+// CK11-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP65]], ptr [[TMP67]], align 8
+// CK11-NEXT: [[TMP68:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0
+// CK11-NEXT: store ptr null, ptr [[TMP68]], align 8
+// CK11-NEXT: [[TMP69:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK11-NEXT: [[TMP70:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK11-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 0
+// CK11-NEXT: store i32 2, ptr [[TMP71]], align 4
+// CK11-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 1
+// CK11-NEXT: store i32 1, ptr [[TMP72]], align 4
+// CK11-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 2
+// CK11-NEXT: store ptr [[TMP69]], ptr [[TMP73]], align 8
+// CK11-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 3
+// CK11-NEXT: store ptr [[TMP70]], ptr [[TMP74]], align 8
+// CK11-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 4
+// CK11-NEXT: store ptr @.offload_sizes.5, ptr [[TMP75]], align 8
+// CK11-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 5
+// CK11-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP76]], align 8
+// CK11-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 6
+// CK11-NEXT: store ptr null, ptr [[TMP77]], align 8
+// CK11-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 7
+// CK11-NEXT: store ptr null, ptr [[TMP78]], align 8
+// CK11-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 8
+// CK11-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK11-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 9
+// CK11-NEXT: store i64 0, ptr [[TMP80]], align 8
+// CK11-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 10
+// CK11-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP81]], align 4
+// CK11-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 11
+// CK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP82]], align 4
+// CK11-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 12
+// CK11-NEXT: store i32 0, ptr [[TMP83]], align 4
+// CK11-NEXT: [[TMP84:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55.region_id, ptr [[KERNEL_ARGS16]])
+// CK11-NEXT: [[TMP85:%.*]] = icmp ne i32 [[TMP84]], 0
+// CK11-NEXT: br i1 [[TMP85]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
+// CK11: omp_offload.failed17:
+// CK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55(ptr [[TMP65]]) #[[ATTR2]]
+// CK11-NEXT: br label [[OMP_OFFLOAD_CONT18]]
+// CK11: omp_offload.cont18:
+// CK11-NEXT: [[TMP86:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// CK11-NEXT: store ptr [[TMP86]], ptr [[_TMP19]], align 8
+// CK11-NEXT: [[TMP87:%.*]] = load ptr, ptr [[_TMP19]], align 8
+// CK11-NEXT: [[TMP88:%.*]] = load ptr, ptr [[TMP87]], align 8
+// CK11-NEXT: [[TMP89:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP88]], ptr [[TMP89]], align 8
+// CK11-NEXT: [[TMP90:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP88]], ptr [[TMP90]], align 8
+// CK11-NEXT: [[TMP91:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
+// CK11-NEXT: store ptr null, ptr [[TMP91]], align 8
+// CK11-NEXT: [[TMP92:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK11-NEXT: [[TMP93:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK11-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 0
+// CK11-NEXT: store i32 2, ptr [[TMP94]], align 4
+// CK11-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 1
+// CK11-NEXT: store i32 1, ptr [[TMP95]], align 4
+// CK11-NEXT: [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 2
+// CK11-NEXT: store ptr [[TMP92]], ptr [[TMP96]], align 8
+// CK11-NEXT: [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 3
+// CK11-NEXT: store ptr [[TMP93]], ptr [[TMP97]], align 8
+// CK11-NEXT: [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 4
+// CK11-NEXT: store ptr @.offload_sizes.7, ptr [[TMP98]], align 8
+// CK11-NEXT: [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 5
+// CK11-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP99]], align 8
+// CK11-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 6
+// CK11-NEXT: store ptr null, ptr [[TMP100]], align 8
+// CK11-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 7
+// CK11-NEXT: store ptr null, ptr [[TMP101]], align 8
+// CK11-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 8
+// CK11-NEXT: store i64 0, ptr [[TMP102]], align 8
+// CK11-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 9
+// CK11-NEXT: store i64 0, ptr [[TMP103]], align 8
+// CK11-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 10
+// CK11-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP104]], align 4
+// CK11-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 11
+// CK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP105]], align 4
+// CK11-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 12
+// CK11-NEXT: store i32 0, ptr [[TMP106]], align 4
+// CK11-NEXT: [[TMP107:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61.region_id, ptr [[KERNEL_ARGS23]])
+// CK11-NEXT: [[TMP108:%.*]] = icmp ne i32 [[TMP107]], 0
+// CK11-NEXT: br i1 [[TMP108]], label [[OMP_OFFLOAD_FAILED24:%.*]], label [[OMP_OFFLOAD_CONT25:%.*]]
+// CK11: omp_offload.failed24:
+// CK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61(ptr [[TMP88]]) #[[ATTR2]]
+// CK11-NEXT: br label [[OMP_OFFLOAD_CONT25]]
+// CK11: omp_offload.cont25:
+// CK11-NEXT: [[TMP109:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// CK11-NEXT: store ptr [[TMP109]], ptr [[_TMP26]], align 8
+// CK11-NEXT: [[TMP110:%.*]] = load ptr, ptr [[_TMP26]], align 8
+// CK11-NEXT: [[TMP111:%.*]] = load ptr, ptr [[TMP110]], align 8
+// CK11-NEXT: [[TMP112:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP111]], ptr [[TMP112]], align 8
+// CK11-NEXT: [[TMP113:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP111]], ptr [[TMP113]], align 8
+// CK11-NEXT: [[TMP114:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 0
+// CK11-NEXT: store ptr null, ptr [[TMP114]], align 8
+// CK11-NEXT: [[TMP115:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK11-NEXT: [[TMP116:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK11-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 0
+// CK11-NEXT: store i32 2, ptr [[TMP117]], align 4
+// CK11-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 1
+// CK11-NEXT: store i32 1, ptr [[TMP118]], align 4
+// CK11-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 2
+// CK11-NEXT: store ptr [[TMP115]], ptr [[TMP119]], align 8
+// CK11-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 3
+// CK11-NEXT: store ptr [[TMP116]], ptr [[TMP120]], align 8
+// CK11-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 4
+// CK11-NEXT: store ptr @.offload_sizes.9, ptr [[TMP121]], align 8
+// CK11-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 5
+// CK11-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP122]], align 8
+// CK11-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 6
+// CK11-NEXT: store ptr null, ptr [[TMP123]], align 8
+// CK11-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 7
+// CK11-NEXT: store ptr null, ptr [[TMP124]], align 8
+// CK11-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 8
+// CK11-NEXT: store i64 0, ptr [[TMP125]], align 8
+// CK11-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 9
+// CK11-NEXT: store i64 0, ptr [[TMP126]], align 8
+// CK11-NEXT: [[TMP127:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 10
+// CK11-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP127]], align 4
+// CK11-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 11
+// CK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP128]], align 4
+// CK11-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 12
+// CK11-NEXT: store i32 0, ptr [[TMP129]], align 4
+// CK11-NEXT: [[TMP130:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67.region_id, ptr [[KERNEL_ARGS30]])
+// CK11-NEXT: [[TMP131:%.*]] = icmp ne i32 [[TMP130]], 0
+// CK11-NEXT: br i1 [[TMP131]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]]
+// CK11: omp_offload.failed31:
+// CK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67(ptr [[TMP111]]) #[[ATTR2]]
+// CK11-NEXT: br label [[OMP_OFFLOAD_CONT32]]
+// CK11: omp_offload.cont32:
+// CK11-NEXT: [[TMP132:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// CK11-NEXT: store ptr [[TMP132]], ptr [[_TMP33]], align 8
+// CK11-NEXT: [[TMP133:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// CK11-NEXT: store ptr [[TMP133]], ptr [[_TMP34]], align 8
+// CK11-NEXT: [[TMP134:%.*]] = load ptr, ptr [[_TMP33]], align 8
+// CK11-NEXT: [[TMP135:%.*]] = load ptr, ptr [[TMP134]], align 8
+// CK11-NEXT: [[TMP136:%.*]] = load ptr, ptr [[_TMP34]], align 8
+// CK11-NEXT: [[TMP137:%.*]] = load ptr, ptr [[TMP136]], align 8
+// CK11-NEXT: [[TMP138:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP135]], ptr [[TMP138]], align 8
+// CK11-NEXT: [[TMP139:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK11-NEXT: store ptr [[TMP135]], ptr [[TMP139]], align 8
+// CK11-NEXT: [[TMP140:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i64 0, i64 0
+// CK11-NEXT: store ptr null, ptr [[TMP140]], align 8
+// CK11-NEXT: [[TMP141:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 1
+// CK11-NEXT: store ptr [[TMP137]], ptr [[TMP141]], align 8
+// CK11-NEXT: [[TMP142:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 1
+// CK11-NEXT: store ptr [[TMP137]], ptr [[TMP142]], align 8
+// CK11-NEXT: [[TMP143:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i64 0, i64 1
+// CK11-NEXT: store ptr null, ptr [[TMP143]], align 8
+// CK11-NEXT: [[TMP144:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK11-NEXT: [[TMP145:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK11-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 0
+// CK11-NEXT: store i32 2, ptr [[TMP146]], align 4
+// CK11-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 1
+// CK11-NEXT: store i32 2, ptr [[TMP147]], align 4
+// CK11-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 2
+// CK11-NEXT: store ptr [[TMP144]], ptr [[TMP148]], align 8
+// CK11-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 3
+// CK11-NEXT: store ptr [[TMP145]], ptr [[TMP149]], align 8
+// CK11-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 4
+// CK11-NEXT: store ptr @.offload_sizes.11, ptr [[TMP150]], align 8
+// CK11-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 5
+// CK11-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP151]], align 8
+// CK11-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 6
+// CK11-NEXT: store ptr null, ptr [[TMP152]], align 8
+// CK11-NEXT: [[TMP153:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 7
+// CK11-NEXT: store ptr null, ptr [[TMP153]], align 8
+// CK11-NEXT: [[TMP154:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 8
+// CK11-NEXT: store i64 0, ptr [[TMP154]], align 8
+// CK11-NEXT: [[TMP155:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 9
+// CK11-NEXT: store i64 0, ptr [[TMP155]], align 8
+// CK11-NEXT: [[TMP156:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 10
+// CK11-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP156]], align 4
+// CK11-NEXT: [[TMP157:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 11
+// CK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP157]], align 4
+// CK11-NEXT: [[TMP158:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 12
+// CK11-NEXT: store i32 0, ptr [[TMP158]], align 4
+// CK11-NEXT: [[TMP159:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74.region_id, ptr [[KERNEL_ARGS38]])
+// CK11-NEXT: [[TMP160:%.*]] = icmp ne i32 [[TMP159]], 0
+// CK11-NEXT: br i1 [[TMP160]], label [[OMP_OFFLOAD_FAILED39:%.*]], label [[OMP_OFFLOAD_CONT40:%.*]]
+// CK11: omp_offload.failed39:
+// CK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74(ptr [[TMP135]], ptr [[TMP137]]) #[[ATTR2]]
+// CK11-NEXT: br label [[OMP_OFFLOAD_CONT40]]
+// CK11: omp_offload.cont40:
+// CK11-NEXT: ret void
+//
+//
+// CK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37
+// CK11-SAME: (ptr noundef [[G:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK11-NEXT: entry:
+// CK11-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8
+// CK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8
+// CK11-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK11-NEXT: store ptr [[INCDEC_PTR]], ptr [[G_ADDR]], align 8
+// CK11-NEXT: ret void
+//
+//
+// CK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43
+// CK11-SAME: (ptr noundef [[L:%.*]]) #[[ATTR1]] {
+// CK11-NEXT: entry:
+// CK11-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 8
+// CK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[L_ADDR]], align 8
+// CK11-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i32 1
+// CK11-NEXT: store ptr [[INCDEC_PTR]], ptr [[L_ADDR]], align 8
+// CK11-NEXT: ret void
+//
+//
+// CK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49
+// CK11-SAME: (ptr noundef [[T:%.*]]) #[[ATTR1]] {
+// CK11-NEXT: entry:
+// CK11-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8
+// CK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8
+// CK11-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
+// CK11-NEXT: store ptr [[INCDEC_PTR]], ptr [[T_ADDR]], align 8
+// CK11-NEXT: ret void
+//
+//
+// CK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55
+// CK11-SAME: (ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK11-NEXT: entry:
+// CK11-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK11-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 8
+// CK11-NEXT: store ptr [[LR_ADDR]], ptr [[TMP]], align 8
+// CK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK11-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 1
+// CK11-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK11-NEXT: ret void
+//
+//
+// CK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61
+// CK11-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK11-NEXT: entry:
+// CK11-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK11-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK11-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 8
+// CK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK11-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK11-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK11-NEXT: ret void
+//
+//
+// CK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67
+// CK11-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK11-NEXT: entry:
+// CK11-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK11-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK11-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 8
+// CK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK11-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK11-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK11-NEXT: ret void
+//
+//
+// CK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74
+// CK11-SAME: (ptr noundef [[TR:%.*]], ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK11-NEXT: entry:
+// CK11-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// CK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8
+// CK11-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// CK11-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 8
+// CK11-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 8
+// CK11-NEXT: store ptr [[LR_ADDR]], ptr [[_TMP1]], align 8
+// CK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
+// CK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
+// CK11-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK11-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8
+// CK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8
+// CK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CK11-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i32 1
+// CK11-NEXT: store ptr [[INCDEC_PTR2]], ptr [[TMP2]], align 8
+// CK11-NEXT: ret void
+//
+//
+// CK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK11-SAME: () #[[ATTR3:[0-9]+]] {
+// CK11-NEXT: entry:
+// CK11-NEXT: call void @__tgt_register_requires(i64 1)
+// CK11-NEXT: ret void
+//
+//
+// CK12-LABEL: define {{[^@]+}}@_Z3barRPfRPi
+// CK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK12-NEXT: entry:
+// CK12-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
+// CK12-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// CK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
+// CK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// CK12-NEXT: call void @_Z3fooIiEvRPfRPT_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]])
+// CK12-NEXT: ret void
+//
+//
+// CK12-LABEL: define {{[^@]+}}@_Z3fooIiEvRPfRPT_
+// CK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TR:%.*]]) #[[ATTR0]] comdat {
+// CK12-NEXT: entry:
+// CK12-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[L:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[T:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK12-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK12-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[KERNEL_ARGS10:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK12-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK12-NEXT: [[_TMP19:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[KERNEL_ARGS23:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK12-NEXT: [[_TMP26:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x ptr], align 4
+// CK12-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK12-NEXT: [[_TMP33:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[_TMP34:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[DOTOFFLOAD_BASEPTRS35:%.*]] = alloca [2 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_PTRS36:%.*]] = alloca [2 x ptr], align 4
+// CK12-NEXT: [[DOTOFFLOAD_MAPPERS37:%.*]] = alloca [2 x ptr], align 4
+// CK12-NEXT: [[KERNEL_ARGS38:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK12-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 4
+// CK12-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK12-NEXT: [[TMP0:%.*]] = load ptr, ptr @g, align 4
+// CK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 4
+// CK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 4
+// CK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CK12-NEXT: store ptr null, ptr [[TMP3]], align 4
+// CK12-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK12-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK12-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK12-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
+// CK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK12-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4
+// CK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK12-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 4
+// CK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK12-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 4
+// CK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK12-NEXT: store ptr null, ptr [[TMP12]], align 4
+// CK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK12-NEXT: store ptr null, ptr [[TMP13]], align 4
+// CK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK12-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK12-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK12-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK12-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK12-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK12-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37.region_id, ptr [[KERNEL_ARGS]])
+// CK12-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK12-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK12: omp_offload.failed:
+// CK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK12-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK12: omp_offload.cont:
+// CK12-NEXT: [[TMP21:%.*]] = load ptr, ptr [[L]], align 4
+// CK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP21]], ptr [[TMP22]], align 4
+// CK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP21]], ptr [[TMP23]], align 4
+// CK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0
+// CK12-NEXT: store ptr null, ptr [[TMP24]], align 4
+// CK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0
+// CK12-NEXT: store i32 2, ptr [[TMP27]], align 4
+// CK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1
+// CK12-NEXT: store i32 1, ptr [[TMP28]], align 4
+// CK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2
+// CK12-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 4
+// CK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3
+// CK12-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 4
+// CK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4
+// CK12-NEXT: store ptr @.offload_sizes.1, ptr [[TMP31]], align 4
+// CK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5
+// CK12-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP32]], align 4
+// CK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6
+// CK12-NEXT: store ptr null, ptr [[TMP33]], align 4
+// CK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7
+// CK12-NEXT: store ptr null, ptr [[TMP34]], align 4
+// CK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8
+// CK12-NEXT: store i64 0, ptr [[TMP35]], align 8
+// CK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9
+// CK12-NEXT: store i64 0, ptr [[TMP36]], align 8
+// CK12-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10
+// CK12-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP37]], align 4
+// CK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11
+// CK12-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 4
+// CK12-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12
+// CK12-NEXT: store i32 0, ptr [[TMP39]], align 4
+// CK12-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43.region_id, ptr [[KERNEL_ARGS4]])
+// CK12-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
+// CK12-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
+// CK12: omp_offload.failed5:
+// CK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43(ptr [[TMP21]]) #[[ATTR2]]
+// CK12-NEXT: br label [[OMP_OFFLOAD_CONT6]]
+// CK12: omp_offload.cont6:
+// CK12-NEXT: [[TMP42:%.*]] = load ptr, ptr [[T]], align 4
+// CK12-NEXT: [[TMP43:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP42]], ptr [[TMP43]], align 4
+// CK12-NEXT: [[TMP44:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP42]], ptr [[TMP44]], align 4
+// CK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0
+// CK12-NEXT: store ptr null, ptr [[TMP45]], align 4
+// CK12-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK12-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK12-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 0
+// CK12-NEXT: store i32 2, ptr [[TMP48]], align 4
+// CK12-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 1
+// CK12-NEXT: store i32 1, ptr [[TMP49]], align 4
+// CK12-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 2
+// CK12-NEXT: store ptr [[TMP46]], ptr [[TMP50]], align 4
+// CK12-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 3
+// CK12-NEXT: store ptr [[TMP47]], ptr [[TMP51]], align 4
+// CK12-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 4
+// CK12-NEXT: store ptr @.offload_sizes.3, ptr [[TMP52]], align 4
+// CK12-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 5
+// CK12-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP53]], align 4
+// CK12-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 6
+// CK12-NEXT: store ptr null, ptr [[TMP54]], align 4
+// CK12-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 7
+// CK12-NEXT: store ptr null, ptr [[TMP55]], align 4
+// CK12-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 8
+// CK12-NEXT: store i64 0, ptr [[TMP56]], align 8
+// CK12-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 9
+// CK12-NEXT: store i64 0, ptr [[TMP57]], align 8
+// CK12-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 10
+// CK12-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP58]], align 4
+// CK12-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 11
+// CK12-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP59]], align 4
+// CK12-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 12
+// CK12-NEXT: store i32 0, ptr [[TMP60]], align 4
+// CK12-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49.region_id, ptr [[KERNEL_ARGS10]])
+// CK12-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0
+// CK12-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
+// CK12: omp_offload.failed11:
+// CK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49(ptr [[TMP42]]) #[[ATTR2]]
+// CK12-NEXT: br label [[OMP_OFFLOAD_CONT12]]
+// CK12: omp_offload.cont12:
+// CK12-NEXT: [[TMP63:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// CK12-NEXT: store ptr [[TMP63]], ptr [[TMP]], align 4
+// CK12-NEXT: [[TMP64:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK12-NEXT: [[TMP65:%.*]] = load ptr, ptr [[TMP64]], align 4
+// CK12-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP65]], ptr [[TMP66]], align 4
+// CK12-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP65]], ptr [[TMP67]], align 4
+// CK12-NEXT: [[TMP68:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
+// CK12-NEXT: store ptr null, ptr [[TMP68]], align 4
+// CK12-NEXT: [[TMP69:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK12-NEXT: [[TMP70:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK12-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 0
+// CK12-NEXT: store i32 2, ptr [[TMP71]], align 4
+// CK12-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 1
+// CK12-NEXT: store i32 1, ptr [[TMP72]], align 4
+// CK12-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 2
+// CK12-NEXT: store ptr [[TMP69]], ptr [[TMP73]], align 4
+// CK12-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 3
+// CK12-NEXT: store ptr [[TMP70]], ptr [[TMP74]], align 4
+// CK12-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 4
+// CK12-NEXT: store ptr @.offload_sizes.5, ptr [[TMP75]], align 4
+// CK12-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 5
+// CK12-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP76]], align 4
+// CK12-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 6
+// CK12-NEXT: store ptr null, ptr [[TMP77]], align 4
+// CK12-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 7
+// CK12-NEXT: store ptr null, ptr [[TMP78]], align 4
+// CK12-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 8
+// CK12-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK12-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 9
+// CK12-NEXT: store i64 0, ptr [[TMP80]], align 8
+// CK12-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 10
+// CK12-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP81]], align 4
+// CK12-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 11
+// CK12-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP82]], align 4
+// CK12-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 12
+// CK12-NEXT: store i32 0, ptr [[TMP83]], align 4
+// CK12-NEXT: [[TMP84:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55.region_id, ptr [[KERNEL_ARGS16]])
+// CK12-NEXT: [[TMP85:%.*]] = icmp ne i32 [[TMP84]], 0
+// CK12-NEXT: br i1 [[TMP85]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
+// CK12: omp_offload.failed17:
+// CK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55(ptr [[TMP65]]) #[[ATTR2]]
+// CK12-NEXT: br label [[OMP_OFFLOAD_CONT18]]
+// CK12: omp_offload.cont18:
+// CK12-NEXT: [[TMP86:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// CK12-NEXT: store ptr [[TMP86]], ptr [[_TMP19]], align 4
+// CK12-NEXT: [[TMP87:%.*]] = load ptr, ptr [[_TMP19]], align 4
+// CK12-NEXT: [[TMP88:%.*]] = load ptr, ptr [[TMP87]], align 4
+// CK12-NEXT: [[TMP89:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP88]], ptr [[TMP89]], align 4
+// CK12-NEXT: [[TMP90:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP88]], ptr [[TMP90]], align 4
+// CK12-NEXT: [[TMP91:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0
+// CK12-NEXT: store ptr null, ptr [[TMP91]], align 4
+// CK12-NEXT: [[TMP92:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK12-NEXT: [[TMP93:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK12-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 0
+// CK12-NEXT: store i32 2, ptr [[TMP94]], align 4
+// CK12-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 1
+// CK12-NEXT: store i32 1, ptr [[TMP95]], align 4
+// CK12-NEXT: [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 2
+// CK12-NEXT: store ptr [[TMP92]], ptr [[TMP96]], align 4
+// CK12-NEXT: [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 3
+// CK12-NEXT: store ptr [[TMP93]], ptr [[TMP97]], align 4
+// CK12-NEXT: [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 4
+// CK12-NEXT: store ptr @.offload_sizes.7, ptr [[TMP98]], align 4
+// CK12-NEXT: [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 5
+// CK12-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP99]], align 4
+// CK12-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 6
+// CK12-NEXT: store ptr null, ptr [[TMP100]], align 4
+// CK12-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 7
+// CK12-NEXT: store ptr null, ptr [[TMP101]], align 4
+// CK12-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 8
+// CK12-NEXT: store i64 0, ptr [[TMP102]], align 8
+// CK12-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 9
+// CK12-NEXT: store i64 0, ptr [[TMP103]], align 8
+// CK12-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 10
+// CK12-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP104]], align 4
+// CK12-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 11
+// CK12-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP105]], align 4
+// CK12-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 12
+// CK12-NEXT: store i32 0, ptr [[TMP106]], align 4
+// CK12-NEXT: [[TMP107:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61.region_id, ptr [[KERNEL_ARGS23]])
+// CK12-NEXT: [[TMP108:%.*]] = icmp ne i32 [[TMP107]], 0
+// CK12-NEXT: br i1 [[TMP108]], label [[OMP_OFFLOAD_FAILED24:%.*]], label [[OMP_OFFLOAD_CONT25:%.*]]
+// CK12: omp_offload.failed24:
+// CK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61(ptr [[TMP88]]) #[[ATTR2]]
+// CK12-NEXT: br label [[OMP_OFFLOAD_CONT25]]
+// CK12: omp_offload.cont25:
+// CK12-NEXT: [[TMP109:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// CK12-NEXT: store ptr [[TMP109]], ptr [[_TMP26]], align 4
+// CK12-NEXT: [[TMP110:%.*]] = load ptr, ptr [[_TMP26]], align 4
+// CK12-NEXT: [[TMP111:%.*]] = load ptr, ptr [[TMP110]], align 4
+// CK12-NEXT: [[TMP112:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP111]], ptr [[TMP112]], align 4
+// CK12-NEXT: [[TMP113:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP111]], ptr [[TMP113]], align 4
+// CK12-NEXT: [[TMP114:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0
+// CK12-NEXT: store ptr null, ptr [[TMP114]], align 4
+// CK12-NEXT: [[TMP115:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK12-NEXT: [[TMP116:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK12-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 0
+// CK12-NEXT: store i32 2, ptr [[TMP117]], align 4
+// CK12-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 1
+// CK12-NEXT: store i32 1, ptr [[TMP118]], align 4
+// CK12-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 2
+// CK12-NEXT: store ptr [[TMP115]], ptr [[TMP119]], align 4
+// CK12-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 3
+// CK12-NEXT: store ptr [[TMP116]], ptr [[TMP120]], align 4
+// CK12-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 4
+// CK12-NEXT: store ptr @.offload_sizes.9, ptr [[TMP121]], align 4
+// CK12-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 5
+// CK12-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP122]], align 4
+// CK12-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 6
+// CK12-NEXT: store ptr null, ptr [[TMP123]], align 4
+// CK12-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 7
+// CK12-NEXT: store ptr null, ptr [[TMP124]], align 4
+// CK12-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 8
+// CK12-NEXT: store i64 0, ptr [[TMP125]], align 8
+// CK12-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 9
+// CK12-NEXT: store i64 0, ptr [[TMP126]], align 8
+// CK12-NEXT: [[TMP127:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 10
+// CK12-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP127]], align 4
+// CK12-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 11
+// CK12-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP128]], align 4
+// CK12-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 12
+// CK12-NEXT: store i32 0, ptr [[TMP129]], align 4
+// CK12-NEXT: [[TMP130:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67.region_id, ptr [[KERNEL_ARGS30]])
+// CK12-NEXT: [[TMP131:%.*]] = icmp ne i32 [[TMP130]], 0
+// CK12-NEXT: br i1 [[TMP131]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]]
+// CK12: omp_offload.failed31:
+// CK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67(ptr [[TMP111]]) #[[ATTR2]]
+// CK12-NEXT: br label [[OMP_OFFLOAD_CONT32]]
+// CK12: omp_offload.cont32:
+// CK12-NEXT: [[TMP132:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// CK12-NEXT: store ptr [[TMP132]], ptr [[_TMP33]], align 4
+// CK12-NEXT: [[TMP133:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// CK12-NEXT: store ptr [[TMP133]], ptr [[_TMP34]], align 4
+// CK12-NEXT: [[TMP134:%.*]] = load ptr, ptr [[_TMP33]], align 4
+// CK12-NEXT: [[TMP135:%.*]] = load ptr, ptr [[TMP134]], align 4
+// CK12-NEXT: [[TMP136:%.*]] = load ptr, ptr [[_TMP34]], align 4
+// CK12-NEXT: [[TMP137:%.*]] = load ptr, ptr [[TMP136]], align 4
+// CK12-NEXT: [[TMP138:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP135]], ptr [[TMP138]], align 4
+// CK12-NEXT: [[TMP139:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK12-NEXT: store ptr [[TMP135]], ptr [[TMP139]], align 4
+// CK12-NEXT: [[TMP140:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i32 0, i32 0
+// CK12-NEXT: store ptr null, ptr [[TMP140]], align 4
+// CK12-NEXT: [[TMP141:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 1
+// CK12-NEXT: store ptr [[TMP137]], ptr [[TMP141]], align 4
+// CK12-NEXT: [[TMP142:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 1
+// CK12-NEXT: store ptr [[TMP137]], ptr [[TMP142]], align 4
+// CK12-NEXT: [[TMP143:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i32 0, i32 1
+// CK12-NEXT: store ptr null, ptr [[TMP143]], align 4
+// CK12-NEXT: [[TMP144:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK12-NEXT: [[TMP145:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK12-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 0
+// CK12-NEXT: store i32 2, ptr [[TMP146]], align 4
+// CK12-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 1
+// CK12-NEXT: store i32 2, ptr [[TMP147]], align 4
+// CK12-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 2
+// CK12-NEXT: store ptr [[TMP144]], ptr [[TMP148]], align 4
+// CK12-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 3
+// CK12-NEXT: store ptr [[TMP145]], ptr [[TMP149]], align 4
+// CK12-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 4
+// CK12-NEXT: store ptr @.offload_sizes.11, ptr [[TMP150]], align 4
+// CK12-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 5
+// CK12-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP151]], align 4
+// CK12-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 6
+// CK12-NEXT: store ptr null, ptr [[TMP152]], align 4
+// CK12-NEXT: [[TMP153:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 7
+// CK12-NEXT: store ptr null, ptr [[TMP153]], align 4
+// CK12-NEXT: [[TMP154:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 8
+// CK12-NEXT: store i64 0, ptr [[TMP154]], align 8
+// CK12-NEXT: [[TMP155:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 9
+// CK12-NEXT: store i64 0, ptr [[TMP155]], align 8
+// CK12-NEXT: [[TMP156:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 10
+// CK12-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP156]], align 4
+// CK12-NEXT: [[TMP157:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 11
+// CK12-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP157]], align 4
+// CK12-NEXT: [[TMP158:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 12
+// CK12-NEXT: store i32 0, ptr [[TMP158]], align 4
+// CK12-NEXT: [[TMP159:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74.region_id, ptr [[KERNEL_ARGS38]])
+// CK12-NEXT: [[TMP160:%.*]] = icmp ne i32 [[TMP159]], 0
+// CK12-NEXT: br i1 [[TMP160]], label [[OMP_OFFLOAD_FAILED39:%.*]], label [[OMP_OFFLOAD_CONT40:%.*]]
+// CK12: omp_offload.failed39:
+// CK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74(ptr [[TMP135]], ptr [[TMP137]]) #[[ATTR2]]
+// CK12-NEXT: br label [[OMP_OFFLOAD_CONT40]]
+// CK12: omp_offload.cont40:
+// CK12-NEXT: ret void
+//
+//
+// CK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37
+// CK12-SAME: (ptr noundef [[G:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK12-NEXT: entry:
+// CK12-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
+// CK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
+// CK12-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK12-NEXT: store ptr [[INCDEC_PTR]], ptr [[G_ADDR]], align 4
+// CK12-NEXT: ret void
+//
+//
+// CK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43
+// CK12-SAME: (ptr noundef [[L:%.*]]) #[[ATTR1]] {
+// CK12-NEXT: entry:
+// CK12-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 4
+// CK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[L_ADDR]], align 4
+// CK12-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i32 1
+// CK12-NEXT: store ptr [[INCDEC_PTR]], ptr [[L_ADDR]], align 4
+// CK12-NEXT: ret void
+//
+//
+// CK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49
+// CK12-SAME: (ptr noundef [[T:%.*]]) #[[ATTR1]] {
+// CK12-NEXT: entry:
+// CK12-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 4
+// CK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 4
+// CK12-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
+// CK12-NEXT: store ptr [[INCDEC_PTR]], ptr [[T_ADDR]], align 4
+// CK12-NEXT: ret void
+//
+//
+// CK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55
+// CK12-SAME: (ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK12-NEXT: entry:
+// CK12-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK12-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 4
+// CK12-NEXT: store ptr [[LR_ADDR]], ptr [[TMP]], align 4
+// CK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK12-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 1
+// CK12-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK12-NEXT: ret void
+//
+//
+// CK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61
+// CK12-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK12-NEXT: entry:
+// CK12-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK12-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK12-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 4
+// CK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK12-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK12-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK12-NEXT: ret void
+//
+//
+// CK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67
+// CK12-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK12-NEXT: entry:
+// CK12-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK12-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK12-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 4
+// CK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK12-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK12-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK12-NEXT: ret void
+//
+//
+// CK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74
+// CK12-SAME: (ptr noundef [[TR:%.*]], ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK12-NEXT: entry:
+// CK12-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK12-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4
+// CK12-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK12-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 4
+// CK12-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 4
+// CK12-NEXT: store ptr [[LR_ADDR]], ptr [[_TMP1]], align 4
+// CK12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK12-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK12-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK12-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 4
+// CK12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CK12-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i32 1
+// CK12-NEXT: store ptr [[INCDEC_PTR2]], ptr [[TMP2]], align 4
+// CK12-NEXT: ret void
+//
+//
+// CK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK12-SAME: () #[[ATTR3:[0-9]+]] {
+// CK12-NEXT: entry:
+// CK12-NEXT: call void @__tgt_register_requires(i64 1)
+// CK12-NEXT: ret void
+//
+//
+// CK13-LABEL: define {{[^@]+}}@_Z3barRPfRPi
+// CK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK13-NEXT: entry:
+// CK13-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
+// CK13-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// CK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
+// CK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// CK13-NEXT: call void @_Z3fooIiEvRPfRPT_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]])
+// CK13-NEXT: ret void
+//
+//
+// CK13-LABEL: define {{[^@]+}}@_Z3fooIiEvRPfRPT_
+// CK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TR:%.*]]) #[[ATTR0]] comdat {
+// CK13-NEXT: entry:
+// CK13-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[L:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[T:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK13-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK13-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[KERNEL_ARGS10:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK13-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK13-NEXT: [[_TMP19:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[KERNEL_ARGS23:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK13-NEXT: [[_TMP26:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x ptr], align 4
+// CK13-NEXT: [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK13-NEXT: [[_TMP33:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[_TMP34:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[DOTOFFLOAD_BASEPTRS35:%.*]] = alloca [2 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_PTRS36:%.*]] = alloca [2 x ptr], align 4
+// CK13-NEXT: [[DOTOFFLOAD_MAPPERS37:%.*]] = alloca [2 x ptr], align 4
+// CK13-NEXT: [[KERNEL_ARGS38:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK13-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 4
+// CK13-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK13-NEXT: [[TMP0:%.*]] = load ptr, ptr @g, align 4
+// CK13-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 4
+// CK13-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 4
+// CK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CK13-NEXT: store ptr null, ptr [[TMP3]], align 4
+// CK13-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK13-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK13-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK13-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK13-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK13-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK13-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
+// CK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK13-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4
+// CK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK13-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 4
+// CK13-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK13-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 4
+// CK13-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK13-NEXT: store ptr null, ptr [[TMP12]], align 4
+// CK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK13-NEXT: store ptr null, ptr [[TMP13]], align 4
+// CK13-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK13-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK13-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK13-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK13-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK13-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK13-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37.region_id, ptr [[KERNEL_ARGS]])
+// CK13-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK13-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK13: omp_offload.failed:
+// CK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK13-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK13: omp_offload.cont:
+// CK13-NEXT: [[TMP21:%.*]] = load ptr, ptr [[L]], align 4
+// CK13-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP21]], ptr [[TMP22]], align 4
+// CK13-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP21]], ptr [[TMP23]], align 4
+// CK13-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0
+// CK13-NEXT: store ptr null, ptr [[TMP24]], align 4
+// CK13-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
+// CK13-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
+// CK13-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0
+// CK13-NEXT: store i32 2, ptr [[TMP27]], align 4
+// CK13-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1
+// CK13-NEXT: store i32 1, ptr [[TMP28]], align 4
+// CK13-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2
+// CK13-NEXT: store ptr [[TMP25]], ptr [[TMP29]], align 4
+// CK13-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3
+// CK13-NEXT: store ptr [[TMP26]], ptr [[TMP30]], align 4
+// CK13-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4
+// CK13-NEXT: store ptr @.offload_sizes.1, ptr [[TMP31]], align 4
+// CK13-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5
+// CK13-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP32]], align 4
+// CK13-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6
+// CK13-NEXT: store ptr null, ptr [[TMP33]], align 4
+// CK13-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7
+// CK13-NEXT: store ptr null, ptr [[TMP34]], align 4
+// CK13-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8
+// CK13-NEXT: store i64 0, ptr [[TMP35]], align 8
+// CK13-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9
+// CK13-NEXT: store i64 0, ptr [[TMP36]], align 8
+// CK13-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10
+// CK13-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP37]], align 4
+// CK13-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11
+// CK13-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP38]], align 4
+// CK13-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12
+// CK13-NEXT: store i32 0, ptr [[TMP39]], align 4
+// CK13-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43.region_id, ptr [[KERNEL_ARGS4]])
+// CK13-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
+// CK13-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
+// CK13: omp_offload.failed5:
+// CK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43(ptr [[TMP21]]) #[[ATTR2]]
+// CK13-NEXT: br label [[OMP_OFFLOAD_CONT6]]
+// CK13: omp_offload.cont6:
+// CK13-NEXT: [[TMP42:%.*]] = load ptr, ptr [[T]], align 4
+// CK13-NEXT: [[TMP43:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP42]], ptr [[TMP43]], align 4
+// CK13-NEXT: [[TMP44:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP42]], ptr [[TMP44]], align 4
+// CK13-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS9]], i32 0, i32 0
+// CK13-NEXT: store ptr null, ptr [[TMP45]], align 4
+// CK13-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
+// CK13-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
+// CK13-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 0
+// CK13-NEXT: store i32 2, ptr [[TMP48]], align 4
+// CK13-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 1
+// CK13-NEXT: store i32 1, ptr [[TMP49]], align 4
+// CK13-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 2
+// CK13-NEXT: store ptr [[TMP46]], ptr [[TMP50]], align 4
+// CK13-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 3
+// CK13-NEXT: store ptr [[TMP47]], ptr [[TMP51]], align 4
+// CK13-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 4
+// CK13-NEXT: store ptr @.offload_sizes.3, ptr [[TMP52]], align 4
+// CK13-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 5
+// CK13-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP53]], align 4
+// CK13-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 6
+// CK13-NEXT: store ptr null, ptr [[TMP54]], align 4
+// CK13-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 7
+// CK13-NEXT: store ptr null, ptr [[TMP55]], align 4
+// CK13-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 8
+// CK13-NEXT: store i64 0, ptr [[TMP56]], align 8
+// CK13-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 9
+// CK13-NEXT: store i64 0, ptr [[TMP57]], align 8
+// CK13-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 10
+// CK13-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP58]], align 4
+// CK13-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 11
+// CK13-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP59]], align 4
+// CK13-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS10]], i32 0, i32 12
+// CK13-NEXT: store i32 0, ptr [[TMP60]], align 4
+// CK13-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49.region_id, ptr [[KERNEL_ARGS10]])
+// CK13-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0
+// CK13-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]]
+// CK13: omp_offload.failed11:
+// CK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49(ptr [[TMP42]]) #[[ATTR2]]
+// CK13-NEXT: br label [[OMP_OFFLOAD_CONT12]]
+// CK13: omp_offload.cont12:
+// CK13-NEXT: [[TMP63:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// CK13-NEXT: store ptr [[TMP63]], ptr [[TMP]], align 4
+// CK13-NEXT: [[TMP64:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK13-NEXT: [[TMP65:%.*]] = load ptr, ptr [[TMP64]], align 4
+// CK13-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP65]], ptr [[TMP66]], align 4
+// CK13-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP65]], ptr [[TMP67]], align 4
+// CK13-NEXT: [[TMP68:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
+// CK13-NEXT: store ptr null, ptr [[TMP68]], align 4
+// CK13-NEXT: [[TMP69:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
+// CK13-NEXT: [[TMP70:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
+// CK13-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 0
+// CK13-NEXT: store i32 2, ptr [[TMP71]], align 4
+// CK13-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 1
+// CK13-NEXT: store i32 1, ptr [[TMP72]], align 4
+// CK13-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 2
+// CK13-NEXT: store ptr [[TMP69]], ptr [[TMP73]], align 4
+// CK13-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 3
+// CK13-NEXT: store ptr [[TMP70]], ptr [[TMP74]], align 4
+// CK13-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 4
+// CK13-NEXT: store ptr @.offload_sizes.5, ptr [[TMP75]], align 4
+// CK13-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 5
+// CK13-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP76]], align 4
+// CK13-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 6
+// CK13-NEXT: store ptr null, ptr [[TMP77]], align 4
+// CK13-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 7
+// CK13-NEXT: store ptr null, ptr [[TMP78]], align 4
+// CK13-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 8
+// CK13-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK13-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 9
+// CK13-NEXT: store i64 0, ptr [[TMP80]], align 8
+// CK13-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 10
+// CK13-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP81]], align 4
+// CK13-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 11
+// CK13-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP82]], align 4
+// CK13-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 12
+// CK13-NEXT: store i32 0, ptr [[TMP83]], align 4
+// CK13-NEXT: [[TMP84:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55.region_id, ptr [[KERNEL_ARGS16]])
+// CK13-NEXT: [[TMP85:%.*]] = icmp ne i32 [[TMP84]], 0
+// CK13-NEXT: br i1 [[TMP85]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
+// CK13: omp_offload.failed17:
+// CK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55(ptr [[TMP65]]) #[[ATTR2]]
+// CK13-NEXT: br label [[OMP_OFFLOAD_CONT18]]
+// CK13: omp_offload.cont18:
+// CK13-NEXT: [[TMP86:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// CK13-NEXT: store ptr [[TMP86]], ptr [[_TMP19]], align 4
+// CK13-NEXT: [[TMP87:%.*]] = load ptr, ptr [[_TMP19]], align 4
+// CK13-NEXT: [[TMP88:%.*]] = load ptr, ptr [[TMP87]], align 4
+// CK13-NEXT: [[TMP89:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP88]], ptr [[TMP89]], align 4
+// CK13-NEXT: [[TMP90:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP88]], ptr [[TMP90]], align 4
+// CK13-NEXT: [[TMP91:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0
+// CK13-NEXT: store ptr null, ptr [[TMP91]], align 4
+// CK13-NEXT: [[TMP92:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
+// CK13-NEXT: [[TMP93:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
+// CK13-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 0
+// CK13-NEXT: store i32 2, ptr [[TMP94]], align 4
+// CK13-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 1
+// CK13-NEXT: store i32 1, ptr [[TMP95]], align 4
+// CK13-NEXT: [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 2
+// CK13-NEXT: store ptr [[TMP92]], ptr [[TMP96]], align 4
+// CK13-NEXT: [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 3
+// CK13-NEXT: store ptr [[TMP93]], ptr [[TMP97]], align 4
+// CK13-NEXT: [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 4
+// CK13-NEXT: store ptr @.offload_sizes.7, ptr [[TMP98]], align 4
+// CK13-NEXT: [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 5
+// CK13-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP99]], align 4
+// CK13-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 6
+// CK13-NEXT: store ptr null, ptr [[TMP100]], align 4
+// CK13-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 7
+// CK13-NEXT: store ptr null, ptr [[TMP101]], align 4
+// CK13-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 8
+// CK13-NEXT: store i64 0, ptr [[TMP102]], align 8
+// CK13-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 9
+// CK13-NEXT: store i64 0, ptr [[TMP103]], align 8
+// CK13-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 10
+// CK13-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP104]], align 4
+// CK13-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 11
+// CK13-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP105]], align 4
+// CK13-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS23]], i32 0, i32 12
+// CK13-NEXT: store i32 0, ptr [[TMP106]], align 4
+// CK13-NEXT: [[TMP107:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61.region_id, ptr [[KERNEL_ARGS23]])
+// CK13-NEXT: [[TMP108:%.*]] = icmp ne i32 [[TMP107]], 0
+// CK13-NEXT: br i1 [[TMP108]], label [[OMP_OFFLOAD_FAILED24:%.*]], label [[OMP_OFFLOAD_CONT25:%.*]]
+// CK13: omp_offload.failed24:
+// CK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61(ptr [[TMP88]]) #[[ATTR2]]
+// CK13-NEXT: br label [[OMP_OFFLOAD_CONT25]]
+// CK13: omp_offload.cont25:
+// CK13-NEXT: [[TMP109:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// CK13-NEXT: store ptr [[TMP109]], ptr [[_TMP26]], align 4
+// CK13-NEXT: [[TMP110:%.*]] = load ptr, ptr [[_TMP26]], align 4
+// CK13-NEXT: [[TMP111:%.*]] = load ptr, ptr [[TMP110]], align 4
+// CK13-NEXT: [[TMP112:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP111]], ptr [[TMP112]], align 4
+// CK13-NEXT: [[TMP113:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP111]], ptr [[TMP113]], align 4
+// CK13-NEXT: [[TMP114:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0
+// CK13-NEXT: store ptr null, ptr [[TMP114]], align 4
+// CK13-NEXT: [[TMP115:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
+// CK13-NEXT: [[TMP116:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
+// CK13-NEXT: [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 0
+// CK13-NEXT: store i32 2, ptr [[TMP117]], align 4
+// CK13-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 1
+// CK13-NEXT: store i32 1, ptr [[TMP118]], align 4
+// CK13-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 2
+// CK13-NEXT: store ptr [[TMP115]], ptr [[TMP119]], align 4
+// CK13-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 3
+// CK13-NEXT: store ptr [[TMP116]], ptr [[TMP120]], align 4
+// CK13-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 4
+// CK13-NEXT: store ptr @.offload_sizes.9, ptr [[TMP121]], align 4
+// CK13-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 5
+// CK13-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP122]], align 4
+// CK13-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 6
+// CK13-NEXT: store ptr null, ptr [[TMP123]], align 4
+// CK13-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 7
+// CK13-NEXT: store ptr null, ptr [[TMP124]], align 4
+// CK13-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 8
+// CK13-NEXT: store i64 0, ptr [[TMP125]], align 8
+// CK13-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 9
+// CK13-NEXT: store i64 0, ptr [[TMP126]], align 8
+// CK13-NEXT: [[TMP127:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 10
+// CK13-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP127]], align 4
+// CK13-NEXT: [[TMP128:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 11
+// CK13-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP128]], align 4
+// CK13-NEXT: [[TMP129:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 12
+// CK13-NEXT: store i32 0, ptr [[TMP129]], align 4
+// CK13-NEXT: [[TMP130:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67.region_id, ptr [[KERNEL_ARGS30]])
+// CK13-NEXT: [[TMP131:%.*]] = icmp ne i32 [[TMP130]], 0
+// CK13-NEXT: br i1 [[TMP131]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]]
+// CK13: omp_offload.failed31:
+// CK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67(ptr [[TMP111]]) #[[ATTR2]]
+// CK13-NEXT: br label [[OMP_OFFLOAD_CONT32]]
+// CK13: omp_offload.cont32:
+// CK13-NEXT: [[TMP132:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// CK13-NEXT: store ptr [[TMP132]], ptr [[_TMP33]], align 4
+// CK13-NEXT: [[TMP133:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// CK13-NEXT: store ptr [[TMP133]], ptr [[_TMP34]], align 4
+// CK13-NEXT: [[TMP134:%.*]] = load ptr, ptr [[_TMP33]], align 4
+// CK13-NEXT: [[TMP135:%.*]] = load ptr, ptr [[TMP134]], align 4
+// CK13-NEXT: [[TMP136:%.*]] = load ptr, ptr [[_TMP34]], align 4
+// CK13-NEXT: [[TMP137:%.*]] = load ptr, ptr [[TMP136]], align 4
+// CK13-NEXT: [[TMP138:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP135]], ptr [[TMP138]], align 4
+// CK13-NEXT: [[TMP139:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK13-NEXT: store ptr [[TMP135]], ptr [[TMP139]], align 4
+// CK13-NEXT: [[TMP140:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i32 0, i32 0
+// CK13-NEXT: store ptr null, ptr [[TMP140]], align 4
+// CK13-NEXT: [[TMP141:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 1
+// CK13-NEXT: store ptr [[TMP137]], ptr [[TMP141]], align 4
+// CK13-NEXT: [[TMP142:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 1
+// CK13-NEXT: store ptr [[TMP137]], ptr [[TMP142]], align 4
+// CK13-NEXT: [[TMP143:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i32 0, i32 1
+// CK13-NEXT: store ptr null, ptr [[TMP143]], align 4
+// CK13-NEXT: [[TMP144:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
+// CK13-NEXT: [[TMP145:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
+// CK13-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 0
+// CK13-NEXT: store i32 2, ptr [[TMP146]], align 4
+// CK13-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 1
+// CK13-NEXT: store i32 2, ptr [[TMP147]], align 4
+// CK13-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 2
+// CK13-NEXT: store ptr [[TMP144]], ptr [[TMP148]], align 4
+// CK13-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 3
+// CK13-NEXT: store ptr [[TMP145]], ptr [[TMP149]], align 4
+// CK13-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 4
+// CK13-NEXT: store ptr @.offload_sizes.11, ptr [[TMP150]], align 4
+// CK13-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 5
+// CK13-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP151]], align 4
+// CK13-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 6
+// CK13-NEXT: store ptr null, ptr [[TMP152]], align 4
+// CK13-NEXT: [[TMP153:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 7
+// CK13-NEXT: store ptr null, ptr [[TMP153]], align 4
+// CK13-NEXT: [[TMP154:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 8
+// CK13-NEXT: store i64 0, ptr [[TMP154]], align 8
+// CK13-NEXT: [[TMP155:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 9
+// CK13-NEXT: store i64 0, ptr [[TMP155]], align 8
+// CK13-NEXT: [[TMP156:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 10
+// CK13-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP156]], align 4
+// CK13-NEXT: [[TMP157:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 11
+// CK13-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP157]], align 4
+// CK13-NEXT: [[TMP158:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 12
+// CK13-NEXT: store i32 0, ptr [[TMP158]], align 4
+// CK13-NEXT: [[TMP159:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74.region_id, ptr [[KERNEL_ARGS38]])
+// CK13-NEXT: [[TMP160:%.*]] = icmp ne i32 [[TMP159]], 0
+// CK13-NEXT: br i1 [[TMP160]], label [[OMP_OFFLOAD_FAILED39:%.*]], label [[OMP_OFFLOAD_CONT40:%.*]]
+// CK13: omp_offload.failed39:
+// CK13-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74(ptr [[TMP135]], ptr [[TMP137]]) #[[ATTR2]]
+// CK13-NEXT: br label [[OMP_OFFLOAD_CONT40]]
+// CK13: omp_offload.cont40:
+// CK13-NEXT: ret void
+//
+//
+// CK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l37
+// CK13-SAME: (ptr noundef [[G:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK13-NEXT: entry:
+// CK13-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
+// CK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
+// CK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK13-NEXT: store ptr [[INCDEC_PTR]], ptr [[G_ADDR]], align 4
+// CK13-NEXT: ret void
+//
+//
+// CK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l43
+// CK13-SAME: (ptr noundef [[L:%.*]]) #[[ATTR1]] {
+// CK13-NEXT: entry:
+// CK13-NEXT: [[L_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: store ptr [[L]], ptr [[L_ADDR]], align 4
+// CK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[L_ADDR]], align 4
+// CK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP0]], i32 1
+// CK13-NEXT: store ptr [[INCDEC_PTR]], ptr [[L_ADDR]], align 4
+// CK13-NEXT: ret void
+//
+//
+// CK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l49
+// CK13-SAME: (ptr noundef [[T:%.*]]) #[[ATTR1]] {
+// CK13-NEXT: entry:
+// CK13-NEXT: [[T_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 4
+// CK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 4
+// CK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1
+// CK13-NEXT: store ptr [[INCDEC_PTR]], ptr [[T_ADDR]], align 4
+// CK13-NEXT: ret void
+//
+//
+// CK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l55
+// CK13-SAME: (ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK13-NEXT: entry:
+// CK13-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK13-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 4
+// CK13-NEXT: store ptr [[LR_ADDR]], ptr [[TMP]], align 4
+// CK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 1
+// CK13-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK13-NEXT: ret void
+//
+//
+// CK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l61
+// CK13-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK13-NEXT: entry:
+// CK13-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK13-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK13-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 4
+// CK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK13-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK13-NEXT: ret void
+//
+//
+// CK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l67
+// CK13-SAME: (ptr noundef [[TR:%.*]]) #[[ATTR1]] {
+// CK13-NEXT: entry:
+// CK13-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK13-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK13-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 4
+// CK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK13-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK13-NEXT: ret void
+//
+//
+// CK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooIiEvRPfRPT__l74
+// CK13-SAME: (ptr noundef [[TR:%.*]], ptr noundef [[LR:%.*]]) #[[ATTR1]] {
+// CK13-NEXT: entry:
+// CK13-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// CK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4
+// CK13-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// CK13-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 4
+// CK13-NEXT: store ptr [[TR_ADDR]], ptr [[TMP]], align 4
+// CK13-NEXT: store ptr [[LR_ADDR]], ptr [[_TMP1]], align 4
+// CK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 4
+// CK13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
+// CK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 1
+// CK13-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 4
+// CK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 4
+// CK13-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CK13-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i32 1
+// CK13-NEXT: store ptr [[INCDEC_PTR2]], ptr [[TMP2]], align 4
+// CK13-NEXT: ret void
+//
+//
+// CK13-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK13-SAME: () #[[ATTR3:[0-9]+]] {
+// CK13-NEXT: entry:
+// CK13-NEXT: call void @__tgt_register_requires(i64 1)
+// CK13-NEXT: ret void
+//
+//
+// SIMD-ONLY00-LABEL: define {{[^@]+}}@_Z3barRPfRPi
+// SIMD-ONLY00-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY00-NEXT: entry:
+// SIMD-ONLY00-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY00-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY00-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
+// SIMD-ONLY00-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// SIMD-ONLY00-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// SIMD-ONLY00-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// SIMD-ONLY00-NEXT: call void @_Z3fooIiEvRPfRPT_(ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP1]])
+// SIMD-ONLY00-NEXT: ret void
+//
+//
+// SIMD-ONLY00-LABEL: define {{[^@]+}}@_Z3fooIiEvRPfRPT_
+// SIMD-ONLY00-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[LR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[TR:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY00-NEXT: entry:
+// SIMD-ONLY00-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY00-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY00-NEXT: [[L:%.*]] = alloca ptr, align 8
+// SIMD-ONLY00-NEXT: [[T:%.*]] = alloca ptr, align 8
+// SIMD-ONLY00-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// SIMD-ONLY00-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8
+// SIMD-ONLY00-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8
+// SIMD-ONLY00-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8
+// SIMD-ONLY00-NEXT: [[_TMP9:%.*]] = alloca ptr, align 8
+// SIMD-ONLY00-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: [[TMP0:%.*]] = load ptr, ptr @g, align 8
+// SIMD-ONLY00-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY00-NEXT: store ptr [[INCDEC_PTR]], ptr @g, align 8
+// SIMD-ONLY00-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L]], align 8
+// SIMD-ONLY00-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 1
+// SIMD-ONLY00-NEXT: store ptr [[INCDEC_PTR1]], ptr [[L]], align 8
+// SIMD-ONLY00-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T]], align 8
+// SIMD-ONLY00-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 1
+// SIMD-ONLY00-NEXT: store ptr [[INCDEC_PTR2]], ptr [[T]], align 8
+// SIMD-ONLY00-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8
+// SIMD-ONLY00-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
+// SIMD-ONLY00-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// SIMD-ONLY00-NEXT: [[INCDEC_PTR3:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i32 1
+// SIMD-ONLY00-NEXT: store ptr [[INCDEC_PTR3]], ptr [[TMP5]], align 8
+// SIMD-ONLY00-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: store ptr [[TMP7]], ptr [[_TMP4]], align 8
+// SIMD-ONLY00-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8
+// SIMD-ONLY00-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// SIMD-ONLY00-NEXT: [[INCDEC_PTR5:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i32 1
+// SIMD-ONLY00-NEXT: store ptr [[INCDEC_PTR5]], ptr [[TMP9]], align 8
+// SIMD-ONLY00-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: store ptr [[TMP11]], ptr [[_TMP6]], align 8
+// SIMD-ONLY00-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP6]], align 8
+// SIMD-ONLY00-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// SIMD-ONLY00-NEXT: [[INCDEC_PTR7:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i32 1
+// SIMD-ONLY00-NEXT: store ptr [[INCDEC_PTR7]], ptr [[TMP13]], align 8
+// SIMD-ONLY00-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: store ptr [[TMP15]], ptr [[_TMP8]], align 8
+// SIMD-ONLY00-NEXT: [[TMP16:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: store ptr [[TMP16]], ptr [[_TMP9]], align 8
+// SIMD-ONLY00-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: [[TMP18:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// SIMD-ONLY00-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP8]], align 8
+// SIMD-ONLY00-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// SIMD-ONLY00-NEXT: [[INCDEC_PTR10:%.*]] = getelementptr inbounds i32, ptr [[TMP20]], i32 1
+// SIMD-ONLY00-NEXT: store ptr [[INCDEC_PTR10]], ptr [[TMP19]], align 8
+// SIMD-ONLY00-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP9]], align 8
+// SIMD-ONLY00-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// SIMD-ONLY00-NEXT: [[INCDEC_PTR11:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 1
+// SIMD-ONLY00-NEXT: store ptr [[INCDEC_PTR11]], ptr [[TMP21]], align 8
+// SIMD-ONLY00-NEXT: ret void
+//
+//
+// SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z3barRPfRPi
+// SIMD-ONLY01-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY01-NEXT: entry:
+// SIMD-ONLY01-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY01-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY01-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
+// SIMD-ONLY01-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// SIMD-ONLY01-NEXT: call void @_Z3fooIiEvRPfRPT_(ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP1]])
+// SIMD-ONLY01-NEXT: ret void
+//
+//
+// SIMD-ONLY01-LABEL: define {{[^@]+}}@_Z3fooIiEvRPfRPT_
+// SIMD-ONLY01-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[LR:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[TR:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY01-NEXT: entry:
+// SIMD-ONLY01-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY01-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY01-NEXT: [[L:%.*]] = alloca ptr, align 8
+// SIMD-ONLY01-NEXT: [[T:%.*]] = alloca ptr, align 8
+// SIMD-ONLY01-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+// SIMD-ONLY01-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8
+// SIMD-ONLY01-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8
+// SIMD-ONLY01-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8
+// SIMD-ONLY01-NEXT: [[_TMP9:%.*]] = alloca ptr, align 8
+// SIMD-ONLY01-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load ptr, ptr @g, align 8
+// SIMD-ONLY01-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY01-NEXT: store ptr [[INCDEC_PTR]], ptr @g, align 8
+// SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L]], align 8
+// SIMD-ONLY01-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 1
+// SIMD-ONLY01-NEXT: store ptr [[INCDEC_PTR1]], ptr [[L]], align 8
+// SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T]], align 8
+// SIMD-ONLY01-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 1
+// SIMD-ONLY01-NEXT: store ptr [[INCDEC_PTR2]], ptr [[T]], align 8
+// SIMD-ONLY01-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8
+// SIMD-ONLY01-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
+// SIMD-ONLY01-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8
+// SIMD-ONLY01-NEXT: [[INCDEC_PTR3:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i32 1
+// SIMD-ONLY01-NEXT: store ptr [[INCDEC_PTR3]], ptr [[TMP5]], align 8
+// SIMD-ONLY01-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: store ptr [[TMP7]], ptr [[_TMP4]], align 8
+// SIMD-ONLY01-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8
+// SIMD-ONLY01-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8
+// SIMD-ONLY01-NEXT: [[INCDEC_PTR5:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i32 1
+// SIMD-ONLY01-NEXT: store ptr [[INCDEC_PTR5]], ptr [[TMP9]], align 8
+// SIMD-ONLY01-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: store ptr [[TMP11]], ptr [[_TMP6]], align 8
+// SIMD-ONLY01-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP6]], align 8
+// SIMD-ONLY01-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8
+// SIMD-ONLY01-NEXT: [[INCDEC_PTR7:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i32 1
+// SIMD-ONLY01-NEXT: store ptr [[INCDEC_PTR7]], ptr [[TMP13]], align 8
+// SIMD-ONLY01-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: store ptr [[TMP15]], ptr [[_TMP8]], align 8
+// SIMD-ONLY01-NEXT: [[TMP16:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: store ptr [[TMP16]], ptr [[_TMP9]], align 8
+// SIMD-ONLY01-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[TMP18:%.*]] = load ptr, ptr [[LR_ADDR]], align 8
+// SIMD-ONLY01-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP8]], align 8
+// SIMD-ONLY01-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8
+// SIMD-ONLY01-NEXT: [[INCDEC_PTR10:%.*]] = getelementptr inbounds i32, ptr [[TMP20]], i32 1
+// SIMD-ONLY01-NEXT: store ptr [[INCDEC_PTR10]], ptr [[TMP19]], align 8
+// SIMD-ONLY01-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP9]], align 8
+// SIMD-ONLY01-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8
+// SIMD-ONLY01-NEXT: [[INCDEC_PTR11:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 1
+// SIMD-ONLY01-NEXT: store ptr [[INCDEC_PTR11]], ptr [[TMP21]], align 8
+// SIMD-ONLY01-NEXT: ret void
+//
+//
+// SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z3barRPfRPi
+// SIMD-ONLY02-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY02-NEXT: entry:
+// SIMD-ONLY02-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY02-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY02-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// SIMD-ONLY02-NEXT: call void @_Z3fooIiEvRPfRPT_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]])
+// SIMD-ONLY02-NEXT: ret void
+//
+//
+// SIMD-ONLY02-LABEL: define {{[^@]+}}@_Z3fooIiEvRPfRPT_
+// SIMD-ONLY02-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TR:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY02-NEXT: entry:
+// SIMD-ONLY02-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY02-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY02-NEXT: [[L:%.*]] = alloca ptr, align 4
+// SIMD-ONLY02-NEXT: [[T:%.*]] = alloca ptr, align 4
+// SIMD-ONLY02-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// SIMD-ONLY02-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4
+// SIMD-ONLY02-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4
+// SIMD-ONLY02-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4
+// SIMD-ONLY02-NEXT: [[_TMP9:%.*]] = alloca ptr, align 4
+// SIMD-ONLY02-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load ptr, ptr @g, align 4
+// SIMD-ONLY02-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY02-NEXT: store ptr [[INCDEC_PTR]], ptr @g, align 4
+// SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L]], align 4
+// SIMD-ONLY02-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 1
+// SIMD-ONLY02-NEXT: store ptr [[INCDEC_PTR1]], ptr [[L]], align 4
+// SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T]], align 4
+// SIMD-ONLY02-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 1
+// SIMD-ONLY02-NEXT: store ptr [[INCDEC_PTR2]], ptr [[T]], align 4
+// SIMD-ONLY02-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4
+// SIMD-ONLY02-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
+// SIMD-ONLY02-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// SIMD-ONLY02-NEXT: [[INCDEC_PTR3:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i32 1
+// SIMD-ONLY02-NEXT: store ptr [[INCDEC_PTR3]], ptr [[TMP5]], align 4
+// SIMD-ONLY02-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store ptr [[TMP7]], ptr [[_TMP4]], align 4
+// SIMD-ONLY02-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 4
+// SIMD-ONLY02-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// SIMD-ONLY02-NEXT: [[INCDEC_PTR5:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i32 1
+// SIMD-ONLY02-NEXT: store ptr [[INCDEC_PTR5]], ptr [[TMP9]], align 4
+// SIMD-ONLY02-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store ptr [[TMP11]], ptr [[_TMP6]], align 4
+// SIMD-ONLY02-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP6]], align 4
+// SIMD-ONLY02-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// SIMD-ONLY02-NEXT: [[INCDEC_PTR7:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i32 1
+// SIMD-ONLY02-NEXT: store ptr [[INCDEC_PTR7]], ptr [[TMP13]], align 4
+// SIMD-ONLY02-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store ptr [[TMP15]], ptr [[_TMP8]], align 4
+// SIMD-ONLY02-NEXT: [[TMP16:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: store ptr [[TMP16]], ptr [[_TMP9]], align 4
+// SIMD-ONLY02-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP18:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// SIMD-ONLY02-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP8]], align 4
+// SIMD-ONLY02-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// SIMD-ONLY02-NEXT: [[INCDEC_PTR10:%.*]] = getelementptr inbounds i32, ptr [[TMP20]], i32 1
+// SIMD-ONLY02-NEXT: store ptr [[INCDEC_PTR10]], ptr [[TMP19]], align 4
+// SIMD-ONLY02-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP9]], align 4
+// SIMD-ONLY02-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// SIMD-ONLY02-NEXT: [[INCDEC_PTR11:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 1
+// SIMD-ONLY02-NEXT: store ptr [[INCDEC_PTR11]], ptr [[TMP21]], align 4
+// SIMD-ONLY02-NEXT: ret void
+//
+//
+// SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z3barRPfRPi
+// SIMD-ONLY03-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY03-NEXT: entry:
+// SIMD-ONLY03-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY03-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY03-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// SIMD-ONLY03-NEXT: call void @_Z3fooIiEvRPfRPT_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]])
+// SIMD-ONLY03-NEXT: ret void
+//
+//
+// SIMD-ONLY03-LABEL: define {{[^@]+}}@_Z3fooIiEvRPfRPT_
+// SIMD-ONLY03-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[LR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TR:%.*]]) #[[ATTR0]] comdat {
+// SIMD-ONLY03-NEXT: entry:
+// SIMD-ONLY03-NEXT: [[LR_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY03-NEXT: [[TR_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY03-NEXT: [[L:%.*]] = alloca ptr, align 4
+// SIMD-ONLY03-NEXT: [[T:%.*]] = alloca ptr, align 4
+// SIMD-ONLY03-NEXT: [[TMP:%.*]] = alloca ptr, align 4
+// SIMD-ONLY03-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4
+// SIMD-ONLY03-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4
+// SIMD-ONLY03-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4
+// SIMD-ONLY03-NEXT: [[_TMP9:%.*]] = alloca ptr, align 4
+// SIMD-ONLY03-NEXT: store ptr [[LR]], ptr [[LR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store ptr [[TR]], ptr [[TR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load ptr, ptr @g, align 4
+// SIMD-ONLY03-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY03-NEXT: store ptr [[INCDEC_PTR]], ptr @g, align 4
+// SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load ptr, ptr [[L]], align 4
+// SIMD-ONLY03-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 1
+// SIMD-ONLY03-NEXT: store ptr [[INCDEC_PTR1]], ptr [[L]], align 4
+// SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T]], align 4
+// SIMD-ONLY03-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 1
+// SIMD-ONLY03-NEXT: store ptr [[INCDEC_PTR2]], ptr [[T]], align 4
+// SIMD-ONLY03-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4
+// SIMD-ONLY03-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
+// SIMD-ONLY03-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4
+// SIMD-ONLY03-NEXT: [[INCDEC_PTR3:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i32 1
+// SIMD-ONLY03-NEXT: store ptr [[INCDEC_PTR3]], ptr [[TMP5]], align 4
+// SIMD-ONLY03-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store ptr [[TMP7]], ptr [[_TMP4]], align 4
+// SIMD-ONLY03-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 4
+// SIMD-ONLY03-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 4
+// SIMD-ONLY03-NEXT: [[INCDEC_PTR5:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i32 1
+// SIMD-ONLY03-NEXT: store ptr [[INCDEC_PTR5]], ptr [[TMP9]], align 4
+// SIMD-ONLY03-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store ptr [[TMP11]], ptr [[_TMP6]], align 4
+// SIMD-ONLY03-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP6]], align 4
+// SIMD-ONLY03-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 4
+// SIMD-ONLY03-NEXT: [[INCDEC_PTR7:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i32 1
+// SIMD-ONLY03-NEXT: store ptr [[INCDEC_PTR7]], ptr [[TMP13]], align 4
+// SIMD-ONLY03-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store ptr [[TMP15]], ptr [[_TMP8]], align 4
+// SIMD-ONLY03-NEXT: [[TMP16:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: store ptr [[TMP16]], ptr [[_TMP9]], align 4
+// SIMD-ONLY03-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP18:%.*]] = load ptr, ptr [[LR_ADDR]], align 4
+// SIMD-ONLY03-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP8]], align 4
+// SIMD-ONLY03-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 4
+// SIMD-ONLY03-NEXT: [[INCDEC_PTR10:%.*]] = getelementptr inbounds i32, ptr [[TMP20]], i32 1
+// SIMD-ONLY03-NEXT: store ptr [[INCDEC_PTR10]], ptr [[TMP19]], align 4
+// SIMD-ONLY03-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP9]], align 4
+// SIMD-ONLY03-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 4
+// SIMD-ONLY03-NEXT: [[INCDEC_PTR11:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i32 1
+// SIMD-ONLY03-NEXT: store ptr [[INCDEC_PTR11]], ptr [[TMP21]], align 4
+// SIMD-ONLY03-NEXT: ret void
+//
+//
+// CK20-LABEL: define {{[^@]+}}@_Z3barPd
+// CK20-SAME: (ptr noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK20-NEXT: entry:
+// CK20-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
+// CK20-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 8
+// CK20-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
+// CK20-NEXT: call void @_ZN2STIdEC1ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
+// CK20-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
+// CK20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8
+// CK20-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK20-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8
+// CK20-NEXT: ret void
+//
+//
+// CK20-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
+// CK20-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
+// CK20-NEXT: entry:
+// CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK20-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// CK20-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// CK20-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// CK20-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]])
+// CK20-NEXT: ret void
+//
+//
+// CK20-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
+// CK20-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 {
+// CK20-NEXT: entry:
+// CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK20-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
+// CK20-NEXT: [[LA:%.*]] = alloca ptr, align 8
+// CK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
+// CK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
+// CK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
+// CK20-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK20-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x ptr], align 8
+// CK20-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x ptr], align 8
+// CK20-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x ptr], align 8
+// CK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [2 x i64], align 8
+// CK20-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK20-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [3 x ptr], align 8
+// CK20-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [3 x ptr], align 8
+// CK20-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [3 x ptr], align 8
+// CK20-NEXT: [[DOTOFFLOAD_SIZES13:%.*]] = alloca [3 x i64], align 8
+// CK20-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK20-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
+// CK20-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: store ptr null, ptr [[LA]], align 8
+// CK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK20-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK20-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 8
+// CK20-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK20-NEXT: store ptr [[A]], ptr [[TMP1]], align 8
+// CK20-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CK20-NEXT: store ptr null, ptr [[TMP2]], align 8
+// CK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK20-NEXT: store i32 2, ptr [[TMP5]], align 4
+// CK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK20-NEXT: store i32 1, ptr [[TMP6]], align 4
+// CK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK20-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
+// CK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK20-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
+// CK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK20-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8
+// CK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK20-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8
+// CK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK20-NEXT: store ptr null, ptr [[TMP11]], align 8
+// CK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK20-NEXT: store ptr null, ptr [[TMP12]], align 8
+// CK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK20-NEXT: store i64 0, ptr [[TMP13]], align 8
+// CK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK20-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK20-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP15]], align 4
+// CK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK20-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
+// CK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK20-NEXT: store i32 0, ptr [[TMP17]], align 4
+// CK20-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112.region_id, ptr [[KERNEL_ARGS]])
+// CK20-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
+// CK20-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK20: omp_offload.failed:
+// CK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112(ptr [[THIS1]]) #[[ATTR3:[0-9]+]]
+// CK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK20: omp_offload.cont:
+// CK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK20-NEXT: [[TMP20:%.*]] = load ptr, ptr [[B]], align 8
+// CK20-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[B]], i32 1
+// CK20-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+// CK20-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[B]] to i64
+// CK20-NEXT: [[TMP24:%.*]] = sub i64 [[TMP22]], [[TMP23]]
+// CK20-NEXT: [[TMP25:%.*]] = sdiv exact i64 [[TMP24]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK20-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.1, i64 16, i1 false)
+// CK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK20-NEXT: store ptr [[THIS1]], ptr [[TMP26]], align 8
+// CK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK20-NEXT: store ptr [[B]], ptr [[TMP27]], align 8
+// CK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK20-NEXT: store i64 [[TMP25]], ptr [[TMP28]], align 8
+// CK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 0
+// CK20-NEXT: store ptr null, ptr [[TMP29]], align 8
+// CK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
+// CK20-NEXT: store ptr [[THIS1]], ptr [[TMP30]], align 8
+// CK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
+// CK20-NEXT: store ptr [[TMP20]], ptr [[TMP31]], align 8
+// CK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 1
+// CK20-NEXT: store ptr null, ptr [[TMP32]], align 8
+// CK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
+// CK20-NEXT: store i32 2, ptr [[TMP36]], align 4
+// CK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
+// CK20-NEXT: store i32 2, ptr [[TMP37]], align 4
+// CK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
+// CK20-NEXT: store ptr [[TMP33]], ptr [[TMP38]], align 8
+// CK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
+// CK20-NEXT: store ptr [[TMP34]], ptr [[TMP39]], align 8
+// CK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
+// CK20-NEXT: store ptr [[TMP35]], ptr [[TMP40]], align 8
+// CK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
+// CK20-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP41]], align 8
+// CK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
+// CK20-NEXT: store ptr null, ptr [[TMP42]], align 8
+// CK20-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
+// CK20-NEXT: store ptr null, ptr [[TMP43]], align 8
+// CK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
+// CK20-NEXT: store i64 0, ptr [[TMP44]], align 8
+// CK20-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
+// CK20-NEXT: store i64 0, ptr [[TMP45]], align 8
+// CK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
+// CK20-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP46]], align 4
+// CK20-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
+// CK20-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4
+// CK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
+// CK20-NEXT: store i32 0, ptr [[TMP48]], align 4
+// CK20-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118.region_id, ptr [[KERNEL_ARGS5]])
+// CK20-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
+// CK20-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CK20: omp_offload.failed6:
+// CK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118(ptr [[THIS1]]) #[[ATTR3]]
+// CK20-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CK20: omp_offload.cont7:
+// CK20-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
+// CK20-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK20-NEXT: [[TMP51:%.*]] = load ptr, ptr [[B9]], align 8
+// CK20-NEXT: [[TMP52:%.*]] = getelementptr ptr, ptr [[B9]], i32 1
+// CK20-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[TMP52]] to i64
+// CK20-NEXT: [[TMP54:%.*]] = ptrtoint ptr [[A8]] to i64
+// CK20-NEXT: [[TMP55:%.*]] = sub i64 [[TMP53]], [[TMP54]]
+// CK20-NEXT: [[TMP56:%.*]] = sdiv exact i64 [[TMP55]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK20-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES13]], ptr align 8 @.offload_sizes.3, i64 24, i1 false)
+// CK20-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK20-NEXT: store ptr [[THIS1]], ptr [[TMP57]], align 8
+// CK20-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK20-NEXT: store ptr [[A8]], ptr [[TMP58]], align 8
+// CK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK20-NEXT: store i64 [[TMP56]], ptr [[TMP59]], align 8
+// CK20-NEXT: [[TMP60:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
+// CK20-NEXT: store ptr null, ptr [[TMP60]], align 8
+// CK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
+// CK20-NEXT: store ptr [[THIS1]], ptr [[TMP61]], align 8
+// CK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
+// CK20-NEXT: store ptr [[A8]], ptr [[TMP62]], align 8
+// CK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
+// CK20-NEXT: store ptr null, ptr [[TMP63]], align 8
+// CK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 2
+// CK20-NEXT: store ptr [[THIS1]], ptr [[TMP64]], align 8
+// CK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 2
+// CK20-NEXT: store ptr [[TMP51]], ptr [[TMP65]], align 8
+// CK20-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 2
+// CK20-NEXT: store ptr null, ptr [[TMP66]], align 8
+// CK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK20-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK20-NEXT: [[TMP69:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK20-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
+// CK20-NEXT: store i32 2, ptr [[TMP70]], align 4
+// CK20-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
+// CK20-NEXT: store i32 3, ptr [[TMP71]], align 4
+// CK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
+// CK20-NEXT: store ptr [[TMP67]], ptr [[TMP72]], align 8
+// CK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
+// CK20-NEXT: store ptr [[TMP68]], ptr [[TMP73]], align 8
+// CK20-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
+// CK20-NEXT: store ptr [[TMP69]], ptr [[TMP74]], align 8
+// CK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
+// CK20-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP75]], align 8
+// CK20-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
+// CK20-NEXT: store ptr null, ptr [[TMP76]], align 8
+// CK20-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
+// CK20-NEXT: store ptr null, ptr [[TMP77]], align 8
+// CK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
+// CK20-NEXT: store i64 0, ptr [[TMP78]], align 8
+// CK20-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
+// CK20-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
+// CK20-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP80]], align 4
+// CK20-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
+// CK20-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP81]], align 4
+// CK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
+// CK20-NEXT: store i32 0, ptr [[TMP82]], align 4
+// CK20-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125.region_id, ptr [[KERNEL_ARGS14]])
+// CK20-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0
+// CK20-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
+// CK20: omp_offload.failed15:
+// CK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125(ptr [[THIS1]]) #[[ATTR3]]
+// CK20-NEXT: br label [[OMP_OFFLOAD_CONT16]]
+// CK20: omp_offload.cont16:
+// CK20-NEXT: ret void
+//
+//
+// CK20-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
+// CK20-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
+// CK20-NEXT: entry:
+// CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK20-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// CK20-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// CK20-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK20-NEXT: store ptr null, ptr [[A]], align 8
+// CK20-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// CK20-NEXT: store ptr [[TMP0]], ptr [[B2]], align 8
+// CK20-NEXT: ret void
+//
+//
+// CK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112
+// CK20-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] {
+// CK20-NEXT: entry:
+// CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK20-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK20-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8
+// CK20-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK20-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 8
+// CK20-NEXT: ret void
+//
+//
+// CK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118
+// CK20-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK20-NEXT: entry:
+// CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK20-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 1
+// CK20-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B]], align 8
+// CK20-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CK20-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 1
+// CK20-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP1]], align 8
+// CK20-NEXT: ret void
+//
+//
+// CK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125
+// CK20-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK20-NEXT: entry:
+// CK20-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK20-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK20-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8
+// CK20-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK20-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 8
+// CK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP0]], i32 0, i32 1
+// CK20-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B]], align 8
+// CK20-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CK20-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 1
+// CK20-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP2]], align 8
+// CK20-NEXT: ret void
+//
+//
+// CK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK20-SAME: () #[[ATTR5:[0-9]+]] {
+// CK20-NEXT: entry:
+// CK20-NEXT: call void @__tgt_register_requires(i64 1)
+// CK20-NEXT: ret void
+//
+//
+// CK21-LABEL: define {{[^@]+}}@_Z3barPd
+// CK21-SAME: (ptr noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK21-NEXT: entry:
+// CK21-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
+// CK21-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 8
+// CK21-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
+// CK21-NEXT: call void @_ZN2STIdEC1ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
+// CK21-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
+// CK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8
+// CK21-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK21-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8
+// CK21-NEXT: ret void
+//
+//
+// CK21-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
+// CK21-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
+// CK21-NEXT: entry:
+// CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// CK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// CK21-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// CK21-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]])
+// CK21-NEXT: ret void
+//
+//
+// CK21-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
+// CK21-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 {
+// CK21-NEXT: entry:
+// CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK21-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
+// CK21-NEXT: [[LA:%.*]] = alloca ptr, align 8
+// CK21-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
+// CK21-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
+// CK21-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
+// CK21-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK21-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x ptr], align 8
+// CK21-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x ptr], align 8
+// CK21-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x ptr], align 8
+// CK21-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [2 x i64], align 8
+// CK21-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK21-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [3 x ptr], align 8
+// CK21-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [3 x ptr], align 8
+// CK21-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [3 x ptr], align 8
+// CK21-NEXT: [[DOTOFFLOAD_SIZES13:%.*]] = alloca [3 x i64], align 8
+// CK21-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
+// CK21-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: store ptr null, ptr [[LA]], align 8
+// CK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK21-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK21-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 8
+// CK21-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK21-NEXT: store ptr [[A]], ptr [[TMP1]], align 8
+// CK21-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CK21-NEXT: store ptr null, ptr [[TMP2]], align 8
+// CK21-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK21-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK21-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK21-NEXT: store i32 2, ptr [[TMP5]], align 4
+// CK21-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK21-NEXT: store i32 1, ptr [[TMP6]], align 4
+// CK21-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK21-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
+// CK21-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK21-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
+// CK21-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK21-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8
+// CK21-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK21-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8
+// CK21-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK21-NEXT: store ptr null, ptr [[TMP11]], align 8
+// CK21-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK21-NEXT: store ptr null, ptr [[TMP12]], align 8
+// CK21-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK21-NEXT: store i64 0, ptr [[TMP13]], align 8
+// CK21-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK21-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK21-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK21-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP15]], align 4
+// CK21-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK21-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
+// CK21-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK21-NEXT: store i32 0, ptr [[TMP17]], align 4
+// CK21-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112.region_id, ptr [[KERNEL_ARGS]])
+// CK21-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
+// CK21-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK21: omp_offload.failed:
+// CK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112(ptr [[THIS1]]) #[[ATTR3:[0-9]+]]
+// CK21-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK21: omp_offload.cont:
+// CK21-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK21-NEXT: [[TMP20:%.*]] = load ptr, ptr [[B]], align 8
+// CK21-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[B]], i32 1
+// CK21-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+// CK21-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[B]] to i64
+// CK21-NEXT: [[TMP24:%.*]] = sub i64 [[TMP22]], [[TMP23]]
+// CK21-NEXT: [[TMP25:%.*]] = sdiv exact i64 [[TMP24]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK21-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.1, i64 16, i1 false)
+// CK21-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK21-NEXT: store ptr [[THIS1]], ptr [[TMP26]], align 8
+// CK21-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK21-NEXT: store ptr [[B]], ptr [[TMP27]], align 8
+// CK21-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK21-NEXT: store i64 [[TMP25]], ptr [[TMP28]], align 8
+// CK21-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 0
+// CK21-NEXT: store ptr null, ptr [[TMP29]], align 8
+// CK21-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
+// CK21-NEXT: store ptr [[THIS1]], ptr [[TMP30]], align 8
+// CK21-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
+// CK21-NEXT: store ptr [[TMP20]], ptr [[TMP31]], align 8
+// CK21-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 1
+// CK21-NEXT: store ptr null, ptr [[TMP32]], align 8
+// CK21-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK21-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK21-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK21-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
+// CK21-NEXT: store i32 2, ptr [[TMP36]], align 4
+// CK21-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
+// CK21-NEXT: store i32 2, ptr [[TMP37]], align 4
+// CK21-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
+// CK21-NEXT: store ptr [[TMP33]], ptr [[TMP38]], align 8
+// CK21-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
+// CK21-NEXT: store ptr [[TMP34]], ptr [[TMP39]], align 8
+// CK21-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
+// CK21-NEXT: store ptr [[TMP35]], ptr [[TMP40]], align 8
+// CK21-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
+// CK21-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP41]], align 8
+// CK21-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
+// CK21-NEXT: store ptr null, ptr [[TMP42]], align 8
+// CK21-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
+// CK21-NEXT: store ptr null, ptr [[TMP43]], align 8
+// CK21-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
+// CK21-NEXT: store i64 0, ptr [[TMP44]], align 8
+// CK21-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
+// CK21-NEXT: store i64 0, ptr [[TMP45]], align 8
+// CK21-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
+// CK21-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP46]], align 4
+// CK21-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
+// CK21-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4
+// CK21-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
+// CK21-NEXT: store i32 0, ptr [[TMP48]], align 4
+// CK21-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118.region_id, ptr [[KERNEL_ARGS5]])
+// CK21-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
+// CK21-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CK21: omp_offload.failed6:
+// CK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118(ptr [[THIS1]]) #[[ATTR3]]
+// CK21-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CK21: omp_offload.cont7:
+// CK21-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
+// CK21-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK21-NEXT: [[TMP51:%.*]] = load ptr, ptr [[B9]], align 8
+// CK21-NEXT: [[TMP52:%.*]] = getelementptr ptr, ptr [[B9]], i32 1
+// CK21-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[TMP52]] to i64
+// CK21-NEXT: [[TMP54:%.*]] = ptrtoint ptr [[A8]] to i64
+// CK21-NEXT: [[TMP55:%.*]] = sub i64 [[TMP53]], [[TMP54]]
+// CK21-NEXT: [[TMP56:%.*]] = sdiv exact i64 [[TMP55]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK21-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES13]], ptr align 8 @.offload_sizes.3, i64 24, i1 false)
+// CK21-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK21-NEXT: store ptr [[THIS1]], ptr [[TMP57]], align 8
+// CK21-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK21-NEXT: store ptr [[A8]], ptr [[TMP58]], align 8
+// CK21-NEXT: [[TMP59:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK21-NEXT: store i64 [[TMP56]], ptr [[TMP59]], align 8
+// CK21-NEXT: [[TMP60:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
+// CK21-NEXT: store ptr null, ptr [[TMP60]], align 8
+// CK21-NEXT: [[TMP61:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
+// CK21-NEXT: store ptr [[THIS1]], ptr [[TMP61]], align 8
+// CK21-NEXT: [[TMP62:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
+// CK21-NEXT: store ptr [[A8]], ptr [[TMP62]], align 8
+// CK21-NEXT: [[TMP63:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
+// CK21-NEXT: store ptr null, ptr [[TMP63]], align 8
+// CK21-NEXT: [[TMP64:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 2
+// CK21-NEXT: store ptr [[THIS1]], ptr [[TMP64]], align 8
+// CK21-NEXT: [[TMP65:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 2
+// CK21-NEXT: store ptr [[TMP51]], ptr [[TMP65]], align 8
+// CK21-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 2
+// CK21-NEXT: store ptr null, ptr [[TMP66]], align 8
+// CK21-NEXT: [[TMP67:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK21-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK21-NEXT: [[TMP69:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK21-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
+// CK21-NEXT: store i32 2, ptr [[TMP70]], align 4
+// CK21-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
+// CK21-NEXT: store i32 3, ptr [[TMP71]], align 4
+// CK21-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
+// CK21-NEXT: store ptr [[TMP67]], ptr [[TMP72]], align 8
+// CK21-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
+// CK21-NEXT: store ptr [[TMP68]], ptr [[TMP73]], align 8
+// CK21-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
+// CK21-NEXT: store ptr [[TMP69]], ptr [[TMP74]], align 8
+// CK21-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
+// CK21-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP75]], align 8
+// CK21-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
+// CK21-NEXT: store ptr null, ptr [[TMP76]], align 8
+// CK21-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
+// CK21-NEXT: store ptr null, ptr [[TMP77]], align 8
+// CK21-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
+// CK21-NEXT: store i64 0, ptr [[TMP78]], align 8
+// CK21-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
+// CK21-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK21-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
+// CK21-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP80]], align 4
+// CK21-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
+// CK21-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP81]], align 4
+// CK21-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
+// CK21-NEXT: store i32 0, ptr [[TMP82]], align 4
+// CK21-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125.region_id, ptr [[KERNEL_ARGS14]])
+// CK21-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0
+// CK21-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
+// CK21: omp_offload.failed15:
+// CK21-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125(ptr [[THIS1]]) #[[ATTR3]]
+// CK21-NEXT: br label [[OMP_OFFLOAD_CONT16]]
+// CK21: omp_offload.cont16:
+// CK21-NEXT: ret void
+//
+//
+// CK21-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
+// CK21-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
+// CK21-NEXT: entry:
+// CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK21-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// CK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// CK21-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK21-NEXT: store ptr null, ptr [[A]], align 8
+// CK21-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// CK21-NEXT: store ptr [[TMP0]], ptr [[B2]], align 8
+// CK21-NEXT: ret void
+//
+//
+// CK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112
+// CK21-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] {
+// CK21-NEXT: entry:
+// CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8
+// CK21-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK21-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 8
+// CK21-NEXT: ret void
+//
+//
+// CK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118
+// CK21-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK21-NEXT: entry:
+// CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 1
+// CK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B]], align 8
+// CK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// CK21-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 1
+// CK21-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP1]], align 8
+// CK21-NEXT: ret void
+//
+//
+// CK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125
+// CK21-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK21-NEXT: entry:
+// CK21-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// CK21-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// CK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK21-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8
+// CK21-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK21-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 8
+// CK21-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP0]], i32 0, i32 1
+// CK21-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B]], align 8
+// CK21-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8
+// CK21-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 1
+// CK21-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP2]], align 8
+// CK21-NEXT: ret void
+//
+//
+// CK21-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK21-SAME: () #[[ATTR5:[0-9]+]] {
+// CK21-NEXT: entry:
+// CK21-NEXT: call void @__tgt_register_requires(i64 1)
+// CK21-NEXT: ret void
+//
+//
+// CK22-LABEL: define {{[^@]+}}@_Z3barPd
+// CK22-SAME: (ptr noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK22-NEXT: entry:
+// CK22-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 4
+// CK22-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
+// CK22-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 4
+// CK22-NEXT: call void @_ZN2STIdEC1ERPd(ptr noundef nonnull align 4 dereferenceable(8) [[A]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG_ADDR]])
+// CK22-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 4 dereferenceable(8) [[A]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG_ADDR]])
+// CK22-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 4
+// CK22-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK22-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 4
+// CK22-NEXT: ret void
+//
+//
+// CK22-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
+// CK22-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
+// CK22-NEXT: entry:
+// CK22-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK22-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// CK22-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// CK22-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// CK22-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])
+// CK22-NEXT: ret void
+//
+//
+// CK22-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
+// CK22-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 {
+// CK22-NEXT: entry:
+// CK22-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK22-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 4
+// CK22-NEXT: [[LA:%.*]] = alloca ptr, align 4
+// CK22-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
+// CK22-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
+// CK22-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
+// CK22-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK22-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x ptr], align 4
+// CK22-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x ptr], align 4
+// CK22-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x ptr], align 4
+// CK22-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [2 x i64], align 4
+// CK22-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK22-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [3 x ptr], align 4
+// CK22-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [3 x ptr], align 4
+// CK22-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [3 x ptr], align 4
+// CK22-NEXT: [[DOTOFFLOAD_SIZES13:%.*]] = alloca [3 x i64], align 4
+// CK22-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK22-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 4
+// CK22-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: store ptr null, ptr [[LA]], align 4
+// CK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK22-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK22-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 4
+// CK22-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK22-NEXT: store ptr [[A]], ptr [[TMP1]], align 4
+// CK22-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CK22-NEXT: store ptr null, ptr [[TMP2]], align 4
+// CK22-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK22-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK22-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK22-NEXT: store i32 2, ptr [[TMP5]], align 4
+// CK22-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK22-NEXT: store i32 1, ptr [[TMP6]], align 4
+// CK22-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK22-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4
+// CK22-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK22-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
+// CK22-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK22-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 4
+// CK22-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK22-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 4
+// CK22-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK22-NEXT: store ptr null, ptr [[TMP11]], align 4
+// CK22-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK22-NEXT: store ptr null, ptr [[TMP12]], align 4
+// CK22-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK22-NEXT: store i64 0, ptr [[TMP13]], align 8
+// CK22-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK22-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK22-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK22-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP15]], align 4
+// CK22-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK22-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
+// CK22-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK22-NEXT: store i32 0, ptr [[TMP17]], align 4
+// CK22-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112.region_id, ptr [[KERNEL_ARGS]])
+// CK22-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
+// CK22-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK22: omp_offload.failed:
+// CK22-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112(ptr [[THIS1]]) #[[ATTR3:[0-9]+]]
+// CK22-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK22: omp_offload.cont:
+// CK22-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK22-NEXT: [[TMP20:%.*]] = load ptr, ptr [[B]], align 4
+// CK22-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[B]], i32 1
+// CK22-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+// CK22-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[B]] to i64
+// CK22-NEXT: [[TMP24:%.*]] = sub i64 [[TMP22]], [[TMP23]]
+// CK22-NEXT: [[TMP25:%.*]] = sdiv exact i64 [[TMP24]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK22-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.1, i32 16, i1 false)
+// CK22-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK22-NEXT: store ptr [[THIS1]], ptr [[TMP26]], align 4
+// CK22-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK22-NEXT: store ptr [[B]], ptr [[TMP27]], align 4
+// CK22-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK22-NEXT: store i64 [[TMP25]], ptr [[TMP28]], align 4
+// CK22-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
+// CK22-NEXT: store ptr null, ptr [[TMP29]], align 4
+// CK22-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
+// CK22-NEXT: store ptr [[THIS1]], ptr [[TMP30]], align 4
+// CK22-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
+// CK22-NEXT: store ptr [[TMP20]], ptr [[TMP31]], align 4
+// CK22-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
+// CK22-NEXT: store ptr null, ptr [[TMP32]], align 4
+// CK22-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK22-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK22-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK22-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
+// CK22-NEXT: store i32 2, ptr [[TMP36]], align 4
+// CK22-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
+// CK22-NEXT: store i32 2, ptr [[TMP37]], align 4
+// CK22-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
+// CK22-NEXT: store ptr [[TMP33]], ptr [[TMP38]], align 4
+// CK22-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
+// CK22-NEXT: store ptr [[TMP34]], ptr [[TMP39]], align 4
+// CK22-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
+// CK22-NEXT: store ptr [[TMP35]], ptr [[TMP40]], align 4
+// CK22-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
+// CK22-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP41]], align 4
+// CK22-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
+// CK22-NEXT: store ptr null, ptr [[TMP42]], align 4
+// CK22-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
+// CK22-NEXT: store ptr null, ptr [[TMP43]], align 4
+// CK22-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
+// CK22-NEXT: store i64 0, ptr [[TMP44]], align 8
+// CK22-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
+// CK22-NEXT: store i64 0, ptr [[TMP45]], align 8
+// CK22-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
+// CK22-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP46]], align 4
+// CK22-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
+// CK22-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4
+// CK22-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
+// CK22-NEXT: store i32 0, ptr [[TMP48]], align 4
+// CK22-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118.region_id, ptr [[KERNEL_ARGS5]])
+// CK22-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
+// CK22-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CK22: omp_offload.failed6:
+// CK22-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118(ptr [[THIS1]]) #[[ATTR3]]
+// CK22-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CK22: omp_offload.cont7:
+// CK22-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
+// CK22-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK22-NEXT: [[TMP51:%.*]] = load ptr, ptr [[B9]], align 4
+// CK22-NEXT: [[TMP52:%.*]] = getelementptr ptr, ptr [[B9]], i32 1
+// CK22-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[TMP52]] to i64
+// CK22-NEXT: [[TMP54:%.*]] = ptrtoint ptr [[A8]] to i64
+// CK22-NEXT: [[TMP55:%.*]] = sub i64 [[TMP53]], [[TMP54]]
+// CK22-NEXT: [[TMP56:%.*]] = sdiv exact i64 [[TMP55]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK22-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES13]], ptr align 4 @.offload_sizes.3, i32 24, i1 false)
+// CK22-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK22-NEXT: store ptr [[THIS1]], ptr [[TMP57]], align 4
+// CK22-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK22-NEXT: store ptr [[A8]], ptr [[TMP58]], align 4
+// CK22-NEXT: [[TMP59:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK22-NEXT: store i64 [[TMP56]], ptr [[TMP59]], align 4
+// CK22-NEXT: [[TMP60:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 0
+// CK22-NEXT: store ptr null, ptr [[TMP60]], align 4
+// CK22-NEXT: [[TMP61:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
+// CK22-NEXT: store ptr [[THIS1]], ptr [[TMP61]], align 4
+// CK22-NEXT: [[TMP62:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
+// CK22-NEXT: store ptr [[A8]], ptr [[TMP62]], align 4
+// CK22-NEXT: [[TMP63:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 1
+// CK22-NEXT: store ptr null, ptr [[TMP63]], align 4
+// CK22-NEXT: [[TMP64:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 2
+// CK22-NEXT: store ptr [[THIS1]], ptr [[TMP64]], align 4
+// CK22-NEXT: [[TMP65:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 2
+// CK22-NEXT: store ptr [[TMP51]], ptr [[TMP65]], align 4
+// CK22-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 2
+// CK22-NEXT: store ptr null, ptr [[TMP66]], align 4
+// CK22-NEXT: [[TMP67:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK22-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK22-NEXT: [[TMP69:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK22-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
+// CK22-NEXT: store i32 2, ptr [[TMP70]], align 4
+// CK22-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
+// CK22-NEXT: store i32 3, ptr [[TMP71]], align 4
+// CK22-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
+// CK22-NEXT: store ptr [[TMP67]], ptr [[TMP72]], align 4
+// CK22-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
+// CK22-NEXT: store ptr [[TMP68]], ptr [[TMP73]], align 4
+// CK22-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
+// CK22-NEXT: store ptr [[TMP69]], ptr [[TMP74]], align 4
+// CK22-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
+// CK22-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP75]], align 4
+// CK22-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
+// CK22-NEXT: store ptr null, ptr [[TMP76]], align 4
+// CK22-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
+// CK22-NEXT: store ptr null, ptr [[TMP77]], align 4
+// CK22-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
+// CK22-NEXT: store i64 0, ptr [[TMP78]], align 8
+// CK22-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
+// CK22-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK22-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
+// CK22-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP80]], align 4
+// CK22-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
+// CK22-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP81]], align 4
+// CK22-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
+// CK22-NEXT: store i32 0, ptr [[TMP82]], align 4
+// CK22-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125.region_id, ptr [[KERNEL_ARGS14]])
+// CK22-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0
+// CK22-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
+// CK22: omp_offload.failed15:
+// CK22-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125(ptr [[THIS1]]) #[[ATTR3]]
+// CK22-NEXT: br label [[OMP_OFFLOAD_CONT16]]
+// CK22: omp_offload.cont16:
+// CK22-NEXT: ret void
+//
+//
+// CK22-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
+// CK22-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
+// CK22-NEXT: entry:
+// CK22-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK22-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// CK22-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// CK22-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK22-NEXT: store ptr null, ptr [[A]], align 4
+// CK22-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK22-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// CK22-NEXT: store ptr [[TMP0]], ptr [[B2]], align 4
+// CK22-NEXT: ret void
+//
+//
+// CK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112
+// CK22-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] {
+// CK22-NEXT: entry:
+// CK22-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK22-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK22-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 4
+// CK22-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK22-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 4
+// CK22-NEXT: ret void
+//
+//
+// CK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118
+// CK22-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK22-NEXT: entry:
+// CK22-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK22-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 1
+// CK22-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B]], align 4
+// CK22-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CK22-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 1
+// CK22-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP1]], align 4
+// CK22-NEXT: ret void
+//
+//
+// CK22-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125
+// CK22-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK22-NEXT: entry:
+// CK22-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK22-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK22-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 4
+// CK22-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK22-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 4
+// CK22-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP0]], i32 0, i32 1
+// CK22-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B]], align 4
+// CK22-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CK22-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 1
+// CK22-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP2]], align 4
+// CK22-NEXT: ret void
+//
+//
+// CK22-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK22-SAME: () #[[ATTR5:[0-9]+]] {
+// CK22-NEXT: entry:
+// CK22-NEXT: call void @__tgt_register_requires(i64 1)
+// CK22-NEXT: ret void
+//
+//
+// CK23-LABEL: define {{[^@]+}}@_Z3barPd
+// CK23-SAME: (ptr noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+// CK23-NEXT: entry:
+// CK23-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 4
+// CK23-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
+// CK23-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 4
+// CK23-NEXT: call void @_ZN2STIdEC1ERPd(ptr noundef nonnull align 4 dereferenceable(8) [[A]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG_ADDR]])
+// CK23-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 4 dereferenceable(8) [[A]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG_ADDR]])
+// CK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 4
+// CK23-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// CK23-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 4
+// CK23-NEXT: ret void
+//
+//
+// CK23-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
+// CK23-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
+// CK23-NEXT: entry:
+// CK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// CK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// CK23-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// CK23-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])
+// CK23-NEXT: ret void
+//
+//
+// CK23-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
+// CK23-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 {
+// CK23-NEXT: entry:
+// CK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK23-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 4
+// CK23-NEXT: [[LA:%.*]] = alloca ptr, align 4
+// CK23-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
+// CK23-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
+// CK23-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
+// CK23-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK23-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x ptr], align 4
+// CK23-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x ptr], align 4
+// CK23-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x ptr], align 4
+// CK23-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [2 x i64], align 4
+// CK23-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK23-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [3 x ptr], align 4
+// CK23-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [3 x ptr], align 4
+// CK23-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [3 x ptr], align 4
+// CK23-NEXT: [[DOTOFFLOAD_SIZES13:%.*]] = alloca [3 x i64], align 4
+// CK23-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 4
+// CK23-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: store ptr null, ptr [[LA]], align 4
+// CK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK23-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK23-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 4
+// CK23-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK23-NEXT: store ptr [[A]], ptr [[TMP1]], align 4
+// CK23-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CK23-NEXT: store ptr null, ptr [[TMP2]], align 4
+// CK23-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK23-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK23-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK23-NEXT: store i32 2, ptr [[TMP5]], align 4
+// CK23-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK23-NEXT: store i32 1, ptr [[TMP6]], align 4
+// CK23-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK23-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4
+// CK23-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK23-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
+// CK23-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK23-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 4
+// CK23-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK23-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 4
+// CK23-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK23-NEXT: store ptr null, ptr [[TMP11]], align 4
+// CK23-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK23-NEXT: store ptr null, ptr [[TMP12]], align 4
+// CK23-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK23-NEXT: store i64 0, ptr [[TMP13]], align 8
+// CK23-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK23-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK23-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK23-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP15]], align 4
+// CK23-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK23-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
+// CK23-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK23-NEXT: store i32 0, ptr [[TMP17]], align 4
+// CK23-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112.region_id, ptr [[KERNEL_ARGS]])
+// CK23-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
+// CK23-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK23: omp_offload.failed:
+// CK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112(ptr [[THIS1]]) #[[ATTR3:[0-9]+]]
+// CK23-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK23: omp_offload.cont:
+// CK23-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK23-NEXT: [[TMP20:%.*]] = load ptr, ptr [[B]], align 4
+// CK23-NEXT: [[TMP21:%.*]] = getelementptr ptr, ptr [[B]], i32 1
+// CK23-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP21]] to i64
+// CK23-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[B]] to i64
+// CK23-NEXT: [[TMP24:%.*]] = sub i64 [[TMP22]], [[TMP23]]
+// CK23-NEXT: [[TMP25:%.*]] = sdiv exact i64 [[TMP24]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK23-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.1, i32 16, i1 false)
+// CK23-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK23-NEXT: store ptr [[THIS1]], ptr [[TMP26]], align 4
+// CK23-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK23-NEXT: store ptr [[B]], ptr [[TMP27]], align 4
+// CK23-NEXT: [[TMP28:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK23-NEXT: store i64 [[TMP25]], ptr [[TMP28]], align 4
+// CK23-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
+// CK23-NEXT: store ptr null, ptr [[TMP29]], align 4
+// CK23-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
+// CK23-NEXT: store ptr [[THIS1]], ptr [[TMP30]], align 4
+// CK23-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
+// CK23-NEXT: store ptr [[TMP20]], ptr [[TMP31]], align 4
+// CK23-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
+// CK23-NEXT: store ptr null, ptr [[TMP32]], align 4
+// CK23-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CK23-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CK23-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
+// CK23-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
+// CK23-NEXT: store i32 2, ptr [[TMP36]], align 4
+// CK23-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
+// CK23-NEXT: store i32 2, ptr [[TMP37]], align 4
+// CK23-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
+// CK23-NEXT: store ptr [[TMP33]], ptr [[TMP38]], align 4
+// CK23-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
+// CK23-NEXT: store ptr [[TMP34]], ptr [[TMP39]], align 4
+// CK23-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
+// CK23-NEXT: store ptr [[TMP35]], ptr [[TMP40]], align 4
+// CK23-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
+// CK23-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP41]], align 4
+// CK23-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
+// CK23-NEXT: store ptr null, ptr [[TMP42]], align 4
+// CK23-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
+// CK23-NEXT: store ptr null, ptr [[TMP43]], align 4
+// CK23-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
+// CK23-NEXT: store i64 0, ptr [[TMP44]], align 8
+// CK23-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
+// CK23-NEXT: store i64 0, ptr [[TMP45]], align 8
+// CK23-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
+// CK23-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP46]], align 4
+// CK23-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
+// CK23-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4
+// CK23-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
+// CK23-NEXT: store i32 0, ptr [[TMP48]], align 4
+// CK23-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118.region_id, ptr [[KERNEL_ARGS5]])
+// CK23-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
+// CK23-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CK23: omp_offload.failed6:
+// CK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118(ptr [[THIS1]]) #[[ATTR3]]
+// CK23-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CK23: omp_offload.cont7:
+// CK23-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
+// CK23-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK23-NEXT: [[TMP51:%.*]] = load ptr, ptr [[B9]], align 4
+// CK23-NEXT: [[TMP52:%.*]] = getelementptr ptr, ptr [[B9]], i32 1
+// CK23-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[TMP52]] to i64
+// CK23-NEXT: [[TMP54:%.*]] = ptrtoint ptr [[A8]] to i64
+// CK23-NEXT: [[TMP55:%.*]] = sub i64 [[TMP53]], [[TMP54]]
+// CK23-NEXT: [[TMP56:%.*]] = sdiv exact i64 [[TMP55]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64)
+// CK23-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES13]], ptr align 4 @.offload_sizes.3, i32 24, i1 false)
+// CK23-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK23-NEXT: store ptr [[THIS1]], ptr [[TMP57]], align 4
+// CK23-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK23-NEXT: store ptr [[A8]], ptr [[TMP58]], align 4
+// CK23-NEXT: [[TMP59:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK23-NEXT: store i64 [[TMP56]], ptr [[TMP59]], align 4
+// CK23-NEXT: [[TMP60:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 0
+// CK23-NEXT: store ptr null, ptr [[TMP60]], align 4
+// CK23-NEXT: [[TMP61:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
+// CK23-NEXT: store ptr [[THIS1]], ptr [[TMP61]], align 4
+// CK23-NEXT: [[TMP62:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
+// CK23-NEXT: store ptr [[A8]], ptr [[TMP62]], align 4
+// CK23-NEXT: [[TMP63:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 1
+// CK23-NEXT: store ptr null, ptr [[TMP63]], align 4
+// CK23-NEXT: [[TMP64:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 2
+// CK23-NEXT: store ptr [[THIS1]], ptr [[TMP64]], align 4
+// CK23-NEXT: [[TMP65:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 2
+// CK23-NEXT: store ptr [[TMP51]], ptr [[TMP65]], align 4
+// CK23-NEXT: [[TMP66:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 2
+// CK23-NEXT: store ptr null, ptr [[TMP66]], align 4
+// CK23-NEXT: [[TMP67:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
+// CK23-NEXT: [[TMP68:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
+// CK23-NEXT: [[TMP69:%.*]] = getelementptr inbounds [3 x i64], ptr [[DOTOFFLOAD_SIZES13]], i32 0, i32 0
+// CK23-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
+// CK23-NEXT: store i32 2, ptr [[TMP70]], align 4
+// CK23-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
+// CK23-NEXT: store i32 3, ptr [[TMP71]], align 4
+// CK23-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
+// CK23-NEXT: store ptr [[TMP67]], ptr [[TMP72]], align 4
+// CK23-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
+// CK23-NEXT: store ptr [[TMP68]], ptr [[TMP73]], align 4
+// CK23-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
+// CK23-NEXT: store ptr [[TMP69]], ptr [[TMP74]], align 4
+// CK23-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
+// CK23-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP75]], align 4
+// CK23-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
+// CK23-NEXT: store ptr null, ptr [[TMP76]], align 4
+// CK23-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
+// CK23-NEXT: store ptr null, ptr [[TMP77]], align 4
+// CK23-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
+// CK23-NEXT: store i64 0, ptr [[TMP78]], align 8
+// CK23-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
+// CK23-NEXT: store i64 0, ptr [[TMP79]], align 8
+// CK23-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
+// CK23-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP80]], align 4
+// CK23-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
+// CK23-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP81]], align 4
+// CK23-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
+// CK23-NEXT: store i32 0, ptr [[TMP82]], align 4
+// CK23-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125.region_id, ptr [[KERNEL_ARGS14]])
+// CK23-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0
+// CK23-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
+// CK23: omp_offload.failed15:
+// CK23-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125(ptr [[THIS1]]) #[[ATTR3]]
+// CK23-NEXT: br label [[OMP_OFFLOAD_CONT16]]
+// CK23: omp_offload.cont16:
+// CK23-NEXT: ret void
+//
+//
+// CK23-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
+// CK23-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
+// CK23-NEXT: entry:
+// CK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK23-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// CK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// CK23-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// CK23-NEXT: store ptr null, ptr [[A]], align 4
+// CK23-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// CK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// CK23-NEXT: store ptr [[TMP0]], ptr [[B2]], align 4
+// CK23-NEXT: ret void
+//
+//
+// CK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l112
+// CK23-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2:[0-9]+]] {
+// CK23-NEXT: entry:
+// CK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 4
+// CK23-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK23-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 4
+// CK23-NEXT: ret void
+//
+//
+// CK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l118
+// CK23-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK23-NEXT: entry:
+// CK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 1
+// CK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B]], align 4
+// CK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// CK23-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 1
+// CK23-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP1]], align 4
+// CK23-NEXT: ret void
+//
+//
+// CK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2STIdE3fooERPd_l125
+// CK23-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR2]] {
+// CK23-NEXT: entry:
+// CK23-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// CK23-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// CK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i32 0, i32 0
+// CK23-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 4
+// CK23-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i32 1
+// CK23-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 4
+// CK23-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP0]], i32 0, i32 1
+// CK23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B]], align 4
+// CK23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4
+// CK23-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 1
+// CK23-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP2]], align 4
+// CK23-NEXT: ret void
+//
+//
+// CK23-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK23-SAME: () #[[ATTR5:[0-9]+]] {
+// CK23-NEXT: entry:
+// CK23-NEXT: call void @__tgt_register_requires(i64 1)
+// CK23-NEXT: ret void
+//
+//
+// SIMD-ONLY10-LABEL: define {{[^@]+}}@_Z3barPd
+// SIMD-ONLY10-SAME: (ptr noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY10-NEXT: entry:
+// SIMD-ONLY10-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY10-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 8
+// SIMD-ONLY10-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
+// SIMD-ONLY10-NEXT: call void @_ZN2STIdEC1ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
+// SIMD-ONLY10-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
+// SIMD-ONLY10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8
+// SIMD-ONLY10-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY10-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8
+// SIMD-ONLY10-NEXT: ret void
+//
+//
+// SIMD-ONLY10-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
+// SIMD-ONLY10-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
+// SIMD-ONLY10-NEXT: entry:
+// SIMD-ONLY10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY10-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY10-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// SIMD-ONLY10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// SIMD-ONLY10-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]])
+// SIMD-ONLY10-NEXT: ret void
+//
+//
+// SIMD-ONLY10-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
+// SIMD-ONLY10-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY10-NEXT: entry:
+// SIMD-ONLY10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY10-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY10-NEXT: [[LA:%.*]] = alloca ptr, align 8
+// SIMD-ONLY10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY10-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
+// SIMD-ONLY10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY10-NEXT: store ptr null, ptr [[LA]], align 8
+// SIMD-ONLY10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A]], align 8
+// SIMD-ONLY10-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY10-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 8
+// SIMD-ONLY10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B]], align 8
+// SIMD-ONLY10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// SIMD-ONLY10-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 1
+// SIMD-ONLY10-NEXT: store ptr [[INCDEC_PTR2]], ptr [[TMP1]], align 8
+// SIMD-ONLY10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A3]], align 8
+// SIMD-ONLY10-NEXT: [[INCDEC_PTR4:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 1
+// SIMD-ONLY10-NEXT: store ptr [[INCDEC_PTR4]], ptr [[A3]], align 8
+// SIMD-ONLY10-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B5]], align 8
+// SIMD-ONLY10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// SIMD-ONLY10-NEXT: [[INCDEC_PTR6:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i32 1
+// SIMD-ONLY10-NEXT: store ptr [[INCDEC_PTR6]], ptr [[TMP4]], align 8
+// SIMD-ONLY10-NEXT: ret void
+//
+//
+// SIMD-ONLY10-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
+// SIMD-ONLY10-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
+// SIMD-ONLY10-NEXT: entry:
+// SIMD-ONLY10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY10-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY10-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// SIMD-ONLY10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY10-NEXT: store ptr null, ptr [[A]], align 8
+// SIMD-ONLY10-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// SIMD-ONLY10-NEXT: store ptr [[TMP0]], ptr [[B2]], align 8
+// SIMD-ONLY10-NEXT: ret void
+//
+//
+// SIMD-ONLY11-LABEL: define {{[^@]+}}@_Z3barPd
+// SIMD-ONLY11-SAME: (ptr noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY11-NEXT: entry:
+// SIMD-ONLY11-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY11-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 8
+// SIMD-ONLY11-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
+// SIMD-ONLY11-NEXT: call void @_ZN2STIdEC1ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
+// SIMD-ONLY11-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 8 dereferenceable(16) [[A]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG_ADDR]])
+// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 8
+// SIMD-ONLY11-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY11-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 8
+// SIMD-ONLY11-NEXT: ret void
+//
+//
+// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
+// SIMD-ONLY11-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
+// SIMD-ONLY11-NEXT: entry:
+// SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// SIMD-ONLY11-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP0]])
+// SIMD-ONLY11-NEXT: ret void
+//
+//
+// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
+// SIMD-ONLY11-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY11-NEXT: entry:
+// SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY11-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY11-NEXT: [[LA:%.*]] = alloca ptr, align 8
+// SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY11-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 8
+// SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY11-NEXT: store ptr null, ptr [[LA]], align 8
+// SIMD-ONLY11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A]], align 8
+// SIMD-ONLY11-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY11-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 8
+// SIMD-ONLY11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B]], align 8
+// SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8
+// SIMD-ONLY11-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 1
+// SIMD-ONLY11-NEXT: store ptr [[INCDEC_PTR2]], ptr [[TMP1]], align 8
+// SIMD-ONLY11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A3]], align 8
+// SIMD-ONLY11-NEXT: [[INCDEC_PTR4:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 1
+// SIMD-ONLY11-NEXT: store ptr [[INCDEC_PTR4]], ptr [[A3]], align 8
+// SIMD-ONLY11-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B5]], align 8
+// SIMD-ONLY11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8
+// SIMD-ONLY11-NEXT: [[INCDEC_PTR6:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i32 1
+// SIMD-ONLY11-NEXT: store ptr [[INCDEC_PTR6]], ptr [[TMP4]], align 8
+// SIMD-ONLY11-NEXT: ret void
+//
+//
+// SIMD-ONLY11-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
+// SIMD-ONLY11-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
+// SIMD-ONLY11-NEXT: entry:
+// SIMD-ONLY11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
+// SIMD-ONLY11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
+// SIMD-ONLY11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
+// SIMD-ONLY11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY11-NEXT: store ptr null, ptr [[A]], align 8
+// SIMD-ONLY11-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
+// SIMD-ONLY11-NEXT: store ptr [[TMP0]], ptr [[B2]], align 8
+// SIMD-ONLY11-NEXT: ret void
+//
+//
+// SIMD-ONLY12-LABEL: define {{[^@]+}}@_Z3barPd
+// SIMD-ONLY12-SAME: (ptr noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY12-NEXT: entry:
+// SIMD-ONLY12-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY12-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
+// SIMD-ONLY12-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 4
+// SIMD-ONLY12-NEXT: call void @_ZN2STIdEC1ERPd(ptr noundef nonnull align 4 dereferenceable(8) [[A]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG_ADDR]])
+// SIMD-ONLY12-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 4 dereferenceable(8) [[A]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG_ADDR]])
+// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY12-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 4
+// SIMD-ONLY12-NEXT: ret void
+//
+//
+// SIMD-ONLY12-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
+// SIMD-ONLY12-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
+// SIMD-ONLY12-NEXT: entry:
+// SIMD-ONLY12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY12-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// SIMD-ONLY12-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])
+// SIMD-ONLY12-NEXT: ret void
+//
+//
+// SIMD-ONLY12-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
+// SIMD-ONLY12-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY12-NEXT: entry:
+// SIMD-ONLY12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY12-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY12-NEXT: [[LA:%.*]] = alloca ptr, align 4
+// SIMD-ONLY12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store ptr null, ptr [[LA]], align 4
+// SIMD-ONLY12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A]], align 4
+// SIMD-ONLY12-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY12-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 4
+// SIMD-ONLY12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B]], align 4
+// SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// SIMD-ONLY12-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 1
+// SIMD-ONLY12-NEXT: store ptr [[INCDEC_PTR2]], ptr [[TMP1]], align 4
+// SIMD-ONLY12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY12-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A3]], align 4
+// SIMD-ONLY12-NEXT: [[INCDEC_PTR4:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 1
+// SIMD-ONLY12-NEXT: store ptr [[INCDEC_PTR4]], ptr [[A3]], align 4
+// SIMD-ONLY12-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY12-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B5]], align 4
+// SIMD-ONLY12-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// SIMD-ONLY12-NEXT: [[INCDEC_PTR6:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i32 1
+// SIMD-ONLY12-NEXT: store ptr [[INCDEC_PTR6]], ptr [[TMP4]], align 4
+// SIMD-ONLY12-NEXT: ret void
+//
+//
+// SIMD-ONLY12-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
+// SIMD-ONLY12-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
+// SIMD-ONLY12-NEXT: entry:
+// SIMD-ONLY12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY12-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY12-NEXT: store ptr null, ptr [[A]], align 4
+// SIMD-ONLY12-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// SIMD-ONLY12-NEXT: store ptr [[TMP0]], ptr [[B2]], align 4
+// SIMD-ONLY12-NEXT: ret void
+//
+//
+// SIMD-ONLY13-LABEL: define {{[^@]+}}@_Z3barPd
+// SIMD-ONLY13-SAME: (ptr noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY13-NEXT: entry:
+// SIMD-ONLY13-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY13-NEXT: [[A:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
+// SIMD-ONLY13-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 4
+// SIMD-ONLY13-NEXT: call void @_ZN2STIdEC1ERPd(ptr noundef nonnull align 4 dereferenceable(8) [[A]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG_ADDR]])
+// SIMD-ONLY13-NEXT: call void @_ZN2STIdE3fooERPd(ptr noundef nonnull align 4 dereferenceable(8) [[A]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG_ADDR]])
+// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARG_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY13-NEXT: store ptr [[INCDEC_PTR]], ptr [[ARG_ADDR]], align 4
+// SIMD-ONLY13-NEXT: ret void
+//
+//
+// SIMD-ONLY13-LABEL: define {{[^@]+}}@_ZN2STIdEC1ERPd
+// SIMD-ONLY13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
+// SIMD-ONLY13-NEXT: entry:
+// SIMD-ONLY13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY13-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// SIMD-ONLY13-NEXT: call void @_ZN2STIdEC2ERPd(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]])
+// SIMD-ONLY13-NEXT: ret void
+//
+//
+// SIMD-ONLY13-LABEL: define {{[^@]+}}@_ZN2STIdE3fooERPd
+// SIMD-ONLY13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARG:%.*]]) #[[ATTR0]] comdat align 2 {
+// SIMD-ONLY13-NEXT: entry:
+// SIMD-ONLY13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY13-NEXT: [[ARG_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY13-NEXT: [[LA:%.*]] = alloca ptr, align 4
+// SIMD-ONLY13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store ptr [[ARG]], ptr [[ARG_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store ptr null, ptr [[LA]], align 4
+// SIMD-ONLY13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A]], align 4
+// SIMD-ONLY13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i32 1
+// SIMD-ONLY13-NEXT: store ptr [[INCDEC_PTR]], ptr [[A]], align 4
+// SIMD-ONLY13-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load ptr, ptr [[B]], align 4
+// SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 4
+// SIMD-ONLY13-NEXT: [[INCDEC_PTR2:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i32 1
+// SIMD-ONLY13-NEXT: store ptr [[INCDEC_PTR2]], ptr [[TMP1]], align 4
+// SIMD-ONLY13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY13-NEXT: [[TMP3:%.*]] = load ptr, ptr [[A3]], align 4
+// SIMD-ONLY13-NEXT: [[INCDEC_PTR4:%.*]] = getelementptr inbounds double, ptr [[TMP3]], i32 1
+// SIMD-ONLY13-NEXT: store ptr [[INCDEC_PTR4]], ptr [[A3]], align 4
+// SIMD-ONLY13-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B5]], align 4
+// SIMD-ONLY13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4
+// SIMD-ONLY13-NEXT: [[INCDEC_PTR6:%.*]] = getelementptr inbounds double, ptr [[TMP5]], i32 1
+// SIMD-ONLY13-NEXT: store ptr [[INCDEC_PTR6]], ptr [[TMP4]], align 4
+// SIMD-ONLY13-NEXT: ret void
+//
+//
+// SIMD-ONLY13-LABEL: define {{[^@]+}}@_ZN2STIdEC2ERPd
+// SIMD-ONLY13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
+// SIMD-ONLY13-NEXT: entry:
+// SIMD-ONLY13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY13-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
+// SIMD-ONLY13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
+// SIMD-ONLY13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
+// SIMD-ONLY13-NEXT: store ptr null, ptr [[A]], align 4
+// SIMD-ONLY13-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
+// SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// SIMD-ONLY13-NEXT: store ptr [[TMP0]], ptr [[B2]], align 4
+// SIMD-ONLY13-NEXT: ret void
+//
+//
+// CK30-LABEL: define {{[^@]+}}@_Z3barv
+// CK30-SAME: () #[[ATTR0:[0-9]+]] {
+// CK30-NEXT: entry:
+// CK30-NEXT: [[PTR:%.*]] = alloca ptr, align 64
+// CK30-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
+// CK30-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
+// CK30-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
+// CK30-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK30-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR]], align 64
+// CK30-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK30-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8
+// CK30-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK30-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 8
+// CK30-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CK30-NEXT: store ptr null, ptr [[TMP3]], align 8
+// CK30-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK30-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK30-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK30-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK30-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK30-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK30-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK30-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
+// CK30-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK30-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8
+// CK30-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK30-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 8
+// CK30-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK30-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 8
+// CK30-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK30-NEXT: store ptr null, ptr [[TMP12]], align 8
+// CK30-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK30-NEXT: store ptr null, ptr [[TMP13]], align 8
+// CK30-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK30-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK30-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK30-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK30-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK30-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK30-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK30-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK30-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK30-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK30-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159.region_id, ptr [[KERNEL_ARGS]])
+// CK30-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK30-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK30: omp_offload.failed:
+// CK30-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK30-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK30: omp_offload.cont:
+// CK30-NEXT: ret void
+//
+//
+// CK30-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159
+// CK30-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK30-NEXT: entry:
+// CK30-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
+// CK30-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
+// CK30-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
+// CK30-NEXT: store double 0.000000e+00, ptr [[TMP0]], align 8
+// CK30-NEXT: ret void
+//
+//
+// CK30-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK30-SAME: () #[[ATTR3:[0-9]+]] {
+// CK30-NEXT: entry:
+// CK30-NEXT: call void @__tgt_register_requires(i64 1)
+// CK30-NEXT: ret void
+//
+//
+// CK31-LABEL: define {{[^@]+}}@_Z3barv
+// CK31-SAME: () #[[ATTR0:[0-9]+]] {
+// CK31-NEXT: entry:
+// CK31-NEXT: [[PTR:%.*]] = alloca ptr, align 64
+// CK31-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
+// CK31-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
+// CK31-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
+// CK31-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK31-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR]], align 64
+// CK31-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK31-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8
+// CK31-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK31-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 8
+// CK31-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CK31-NEXT: store ptr null, ptr [[TMP3]], align 8
+// CK31-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK31-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK31-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK31-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK31-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK31-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK31-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK31-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
+// CK31-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK31-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 8
+// CK31-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK31-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 8
+// CK31-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK31-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 8
+// CK31-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK31-NEXT: store ptr null, ptr [[TMP12]], align 8
+// CK31-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK31-NEXT: store ptr null, ptr [[TMP13]], align 8
+// CK31-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK31-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK31-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK31-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK31-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK31-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK31-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK31-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK31-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK31-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK31-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159.region_id, ptr [[KERNEL_ARGS]])
+// CK31-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK31-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK31: omp_offload.failed:
+// CK31-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK31-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK31: omp_offload.cont:
+// CK31-NEXT: ret void
+//
+//
+// CK31-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159
+// CK31-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK31-NEXT: entry:
+// CK31-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
+// CK31-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
+// CK31-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
+// CK31-NEXT: store double 0.000000e+00, ptr [[TMP0]], align 8
+// CK31-NEXT: ret void
+//
+//
+// CK31-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK31-SAME: () #[[ATTR3:[0-9]+]] {
+// CK31-NEXT: entry:
+// CK31-NEXT: call void @__tgt_register_requires(i64 1)
+// CK31-NEXT: ret void
+//
+//
+// CK32-LABEL: define {{[^@]+}}@_Z3barv
+// CK32-SAME: () #[[ATTR0:[0-9]+]] {
+// CK32-NEXT: entry:
+// CK32-NEXT: [[PTR:%.*]] = alloca ptr, align 64
+// CK32-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
+// CK32-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
+// CK32-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
+// CK32-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR]], align 64
+// CK32-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK32-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 4
+// CK32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK32-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 4
+// CK32-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CK32-NEXT: store ptr null, ptr [[TMP3]], align 4
+// CK32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK32-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK32-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK32-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK32-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK32-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
+// CK32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK32-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4
+// CK32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK32-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 4
+// CK32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK32-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 4
+// CK32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK32-NEXT: store ptr null, ptr [[TMP12]], align 4
+// CK32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK32-NEXT: store ptr null, ptr [[TMP13]], align 4
+// CK32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK32-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK32-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK32-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK32-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK32-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK32-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK32-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK32-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK32-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159.region_id, ptr [[KERNEL_ARGS]])
+// CK32-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK32-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK32: omp_offload.failed:
+// CK32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK32-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK32: omp_offload.cont:
+// CK32-NEXT: ret void
+//
+//
+// CK32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159
+// CK32-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK32-NEXT: entry:
+// CK32-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4
+// CK32-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4
+// CK32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4
+// CK32-NEXT: store double 0.000000e+00, ptr [[TMP0]], align 4
+// CK32-NEXT: ret void
+//
+//
+// CK32-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK32-SAME: () #[[ATTR3:[0-9]+]] {
+// CK32-NEXT: entry:
+// CK32-NEXT: call void @__tgt_register_requires(i64 1)
+// CK32-NEXT: ret void
+//
+//
+// CK33-LABEL: define {{[^@]+}}@_Z3barv
+// CK33-SAME: () #[[ATTR0:[0-9]+]] {
+// CK33-NEXT: entry:
+// CK33-NEXT: [[PTR:%.*]] = alloca ptr, align 64
+// CK33-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
+// CK33-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
+// CK33-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
+// CK33-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
+// CK33-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR]], align 64
+// CK33-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK33-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 4
+// CK33-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK33-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 4
+// CK33-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CK33-NEXT: store ptr null, ptr [[TMP3]], align 4
+// CK33-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CK33-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CK33-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CK33-NEXT: store i32 2, ptr [[TMP6]], align 4
+// CK33-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CK33-NEXT: store i32 1, ptr [[TMP7]], align 4
+// CK33-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CK33-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
+// CK33-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CK33-NEXT: store ptr [[TMP5]], ptr [[TMP9]], align 4
+// CK33-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CK33-NEXT: store ptr @.offload_sizes, ptr [[TMP10]], align 4
+// CK33-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CK33-NEXT: store ptr @.offload_maptypes, ptr [[TMP11]], align 4
+// CK33-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CK33-NEXT: store ptr null, ptr [[TMP12]], align 4
+// CK33-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CK33-NEXT: store ptr null, ptr [[TMP13]], align 4
+// CK33-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CK33-NEXT: store i64 0, ptr [[TMP14]], align 8
+// CK33-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CK33-NEXT: store i64 0, ptr [[TMP15]], align 8
+// CK33-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CK33-NEXT: store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP16]], align 4
+// CK33-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CK33-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
+// CK33-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CK33-NEXT: store i32 0, ptr [[TMP18]], align 4
+// CK33-NEXT: [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159.region_id, ptr [[KERNEL_ARGS]])
+// CK33-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
+// CK33-NEXT: br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CK33: omp_offload.failed:
+// CK33-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CK33-NEXT: br label [[OMP_OFFLOAD_CONT]]
+// CK33: omp_offload.cont:
+// CK33-NEXT: ret void
+//
+//
+// CK33-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barv_l159
+// CK33-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR1:[0-9]+]] {
+// CK33-NEXT: entry:
+// CK33-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 4
+// CK33-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 4
+// CK33-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 4
+// CK33-NEXT: store double 0.000000e+00, ptr [[TMP0]], align 4
+// CK33-NEXT: ret void
+//
+//
+// CK33-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
+// CK33-SAME: () #[[ATTR3:[0-9]+]] {
+// CK33-NEXT: entry:
+// CK33-NEXT: call void @__tgt_register_requires(i64 1)
+// CK33-NEXT: ret void
+//
+//
+// SIMD-ONLY20-LABEL: define {{[^@]+}}@_Z3barv
+// SIMD-ONLY20-SAME: () #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY20-NEXT: entry:
+// SIMD-ONLY20-NEXT: [[PTR:%.*]] = alloca ptr, align 64
+// SIMD-ONLY20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR]], align 64
+// SIMD-ONLY20-NEXT: store double 0.000000e+00, ptr [[TMP0]], align 8
+// SIMD-ONLY20-NEXT: ret void
+//
+//
+// SIMD-ONLY21-LABEL: define {{[^@]+}}@_Z3barv
+// SIMD-ONLY21-SAME: () #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY21-NEXT: entry:
+// SIMD-ONLY21-NEXT: [[PTR:%.*]] = alloca ptr, align 64
+// SIMD-ONLY21-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR]], align 64
+// SIMD-ONLY21-NEXT: store double 0.000000e+00, ptr [[TMP0]], align 8
+// SIMD-ONLY21-NEXT: ret void
+//
+//
+// SIMD-ONLY22-LABEL: define {{[^@]+}}@_Z3barv
+// SIMD-ONLY22-SAME: () #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY22-NEXT: entry:
+// SIMD-ONLY22-NEXT: [[PTR:%.*]] = alloca ptr, align 64
+// SIMD-ONLY22-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR]], align 64
+// SIMD-ONLY22-NEXT: store double 0.000000e+00, ptr [[TMP0]], align 4
+// SIMD-ONLY22-NEXT: ret void
+//
+//
+// SIMD-ONLY23-LABEL: define {{[^@]+}}@_Z3barv
+// SIMD-ONLY23-SAME: () #[[ATTR0:[0-9]+]] {
+// SIMD-ONLY23-NEXT: entry:
+// SIMD-ONLY23-NEXT: [[PTR:%.*]] = alloca ptr, align 64
+// SIMD-ONLY23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR]], align 64
+// SIMD-ONLY23-NEXT: store double 0.000000e+00, ptr [[TMP0]], align 4
+// SIMD-ONLY23-NEXT: ret void
+//
diff --git a/clang/test/OpenMP/teams_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_firstprivate_codegen.cpp
index c1617e16b402c..e8f9512114f7f 100644
--- a/clang/test/OpenMP/teams_firstprivate_codegen.cpp
+++ b/clang/test/OpenMP/teams_firstprivate_codegen.cpp
@@ -168,46 +168,42 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
-// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK1-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK1-NEXT: entry:
-// CHECK1-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
-// CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128
+// CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8
-// CHECK1-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8
+// CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK1-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128
+// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4
+// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
-// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.omp_outlined., ptr [[G1]], i64 [[TMP3]])
+// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.omp_outlined., i64 [[TMP1]], i64 [[TMP3]])
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
-// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2]] {
+// CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK1-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8
+// CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8
-// CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128
// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK1-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8
+// CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
// CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8
-// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK1-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128
-// CHECK1-NEXT: store i32 1, ptr [[G1]], align 128
+// CHECK1-NEXT: store i32 1, ptr [[G_ADDR]], align 4
// CHECK1-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4
-// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
-// CHECK1-NEXT: store ptr [[G1]], ptr [[TMP2]], align 8
-// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
-// CHECK1-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP3]], align 8
+// CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
+// CHECK1-NEXT: store ptr [[G_ADDR]], ptr [[TMP0]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
+// CHECK1-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP1]], align 8
// CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr nonnull align 8 dereferenceable(16) [[REF_TMP]])
// CHECK1-NEXT: ret void
//
@@ -230,46 +226,42 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
-// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
+// CHECK3-SAME: (i32 [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK3-NEXT: entry:
-// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
+// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128
+// CHECK3-NEXT: [[G_CASTED:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[G]], ptr [[G_ADDR]], align 4
// CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
-// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK3-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128
+// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[G_CASTED]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
-// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.omp_outlined., ptr [[G1]], i32 [[TMP3]])
+// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.omp_outlined., i32 [[TMP1]], i32 [[TMP3]])
// CHECK3-NEXT: ret void
//
//
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
-// CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2]] {
+// CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
+// CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128
// CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[G]], ptr [[G_ADDR]], align 4
// CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4
-// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK3-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128
-// CHECK3-NEXT: store i32 1, ptr [[G1]], align 128
+// CHECK3-NEXT: store i32 1, ptr [[G_ADDR]], align 4
// CHECK3-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
-// CHECK3-NEXT: store ptr [[G1]], ptr [[TMP2]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
-// CHECK3-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP3]], align 4
+// CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
+// CHECK3-NEXT: store ptr [[G_ADDR]], ptr [[TMP0]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
+// CHECK3-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP1]], align 4
// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr nonnull align 4 dereferenceable(8) [[REF_TMP]])
// CHECK3-NEXT: ret void
//
@@ -637,14 +629,16 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128
// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128
// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128
+// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
// CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
// CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
-// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 8
-// CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 8
-// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 8
-// CHECK9-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK9-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i64, align 8
+// CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x ptr], align 8
+// CHECK9-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x ptr], align 8
+// CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x ptr], align 8
+// CHECK9-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])
// CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 128
// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
@@ -653,121 +647,127 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2)
// CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3)
-// CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
-// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[TMP0]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
-// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[TMP1]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
-// CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
-// CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP3]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
-// CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 8
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
-// CHECK9-NEXT: store ptr null, ptr [[TMP5]], align 8
-// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
-// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP6]], align 8
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
-// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP7]], align 8
-// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
-// CHECK9-NEXT: store ptr null, ptr [[TMP8]], align 8
-// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
-// CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP9]], align 8
-// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
-// CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP10]], align 8
-// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
-// CHECK9-NEXT: store ptr null, ptr [[TMP11]], align 8
-// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
-// CHECK9-NEXT: store i32 2, ptr [[TMP14]], align 4
-// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
-// CHECK9-NEXT: store i32 4, ptr [[TMP15]], align 4
-// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
-// CHECK9-NEXT: store ptr [[TMP12]], ptr [[TMP16]], align 8
-// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
-// CHECK9-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 8
-// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
-// CHECK9-NEXT: store ptr @.offload_sizes.5, ptr [[TMP18]], align 8
-// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
-// CHECK9-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP19]], align 8
-// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
-// CHECK9-NEXT: store ptr null, ptr [[TMP20]], align 8
-// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
-// CHECK9-NEXT: store ptr null, ptr [[TMP21]], align 8
-// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
-// CHECK9-NEXT: store i64 0, ptr [[TMP22]], align 8
-// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
-// CHECK9-NEXT: store i64 0, ptr [[TMP23]], align 8
-// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
-// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP24]], align 4
-// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
-// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4
-// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
-// CHECK9-NEXT: store i32 0, ptr [[TMP26]], align 4
-// CHECK9-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, ptr [[KERNEL_ARGS]])
-// CHECK9-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
-// CHECK9-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128
+// CHECK9-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
+// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8
+// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
+// CHECK9-NEXT: store ptr null, ptr [[TMP4]], align 8
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 8
+// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP6]], align 8
+// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
+// CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8
+// CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP8]], align 8
+// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP9]], align 8
+// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
+// CHECK9-NEXT: store ptr null, ptr [[TMP10]], align 8
+// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP11]], align 8
+// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP12]], align 8
+// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
+// CHECK9-NEXT: store ptr null, ptr [[TMP13]], align 8
+// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK9-NEXT: store i32 2, ptr [[TMP16]], align 4
+// CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK9-NEXT: store i32 4, ptr [[TMP17]], align 4
+// CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK9-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8
+// CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK9-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8
+// CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK9-NEXT: store ptr @.offload_sizes.5, ptr [[TMP20]], align 8
+// CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK9-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP21]], align 8
+// CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK9-NEXT: store ptr null, ptr [[TMP22]], align 8
+// CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK9-NEXT: store ptr null, ptr [[TMP23]], align 8
+// CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK9-NEXT: store i64 0, ptr [[TMP24]], align 8
+// CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK9-NEXT: store i64 0, ptr [[TMP25]], align 8
+// CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
+// CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
+// CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK9-NEXT: store i32 0, ptr [[TMP28]], align 4
+// CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, ptr [[KERNEL_ARGS]])
+// CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
+// CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK9: omp_offload.failed:
-// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) #[[ATTR4]]
+// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i64 [[TMP1]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) #[[ATTR4]]
// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK9: omp_offload.cont:
-// CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
-// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[TMP29]], align 8
-// CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
-// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[TMP30]], align 8
-// CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0
-// CHECK9-NEXT: store ptr null, ptr [[TMP31]], align 8
-// CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0
-// CHECK9-NEXT: store i32 2, ptr [[TMP34]], align 4
-// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1
-// CHECK9-NEXT: store i32 1, ptr [[TMP35]], align 4
-// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2
-// CHECK9-NEXT: store ptr [[TMP32]], ptr [[TMP36]], align 8
-// CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3
-// CHECK9-NEXT: store ptr [[TMP33]], ptr [[TMP37]], align 8
-// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4
-// CHECK9-NEXT: store ptr @.offload_sizes.8, ptr [[TMP38]], align 8
-// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5
-// CHECK9-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP39]], align 8
-// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6
-// CHECK9-NEXT: store ptr null, ptr [[TMP40]], align 8
-// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7
-// CHECK9-NEXT: store ptr null, ptr [[TMP41]], align 8
-// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8
-// CHECK9-NEXT: store i64 0, ptr [[TMP42]], align 8
-// CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9
-// CHECK9-NEXT: store i64 0, ptr [[TMP43]], align 8
-// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10
-// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP44]], align 4
-// CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11
-// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP45]], align 4
-// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12
-// CHECK9-NEXT: store i32 0, ptr [[TMP46]], align 4
-// CHECK9-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS4]])
-// CHECK9-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0
-// CHECK9-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
-// CHECK9: omp_offload.failed5:
-// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(ptr [[T_VAR]]) #[[ATTR4]]
-// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]]
-// CHECK9: omp_offload.cont6:
+// CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[T_VAR]], align 128
+// CHECK9-NEXT: store i32 [[TMP31]], ptr [[T_VAR_CASTED1]], align 4
+// CHECK9-NEXT: [[TMP32:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 8
+// CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK9-NEXT: store i64 [[TMP32]], ptr [[TMP33]], align 8
+// CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK9-NEXT: store i64 [[TMP32]], ptr [[TMP34]], align 8
+// CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 0
+// CHECK9-NEXT: store ptr null, ptr [[TMP35]], align 8
+// CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
+// CHECK9-NEXT: store i32 2, ptr [[TMP38]], align 4
+// CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
+// CHECK9-NEXT: store i32 1, ptr [[TMP39]], align 4
+// CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
+// CHECK9-NEXT: store ptr [[TMP36]], ptr [[TMP40]], align 8
+// CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
+// CHECK9-NEXT: store ptr [[TMP37]], ptr [[TMP41]], align 8
+// CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
+// CHECK9-NEXT: store ptr @.offload_sizes.8, ptr [[TMP42]], align 8
+// CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
+// CHECK9-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP43]], align 8
+// CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
+// CHECK9-NEXT: store ptr null, ptr [[TMP44]], align 8
+// CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
+// CHECK9-NEXT: store ptr null, ptr [[TMP45]], align 8
+// CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
+// CHECK9-NEXT: store i64 0, ptr [[TMP46]], align 8
+// CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
+// CHECK9-NEXT: store i64 0, ptr [[TMP47]], align 8
+// CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
+// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP48]], align 4
+// CHECK9-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
+// CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP49]], align 4
+// CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
+// CHECK9-NEXT: store i32 0, ptr [[TMP50]], align 4
+// CHECK9-NEXT: [[TMP51:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS5]])
+// CHECK9-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0
+// CHECK9-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CHECK9: omp_offload.failed6:
+// CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i64 [[TMP32]]) #[[ATTR4]]
+// CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CHECK9: omp_offload.cont7:
// CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
+// CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK9: arraydestroy.body:
-// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP49]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP53]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
-// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
-// CHECK9: arraydestroy.done7:
+// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK9: arraydestroy.done8:
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
-// CHECK9-NEXT: [[TMP50:%.*]] = load i32, ptr [[RETVAL]], align 4
-// CHECK9-NEXT: ret i32 [[TMP50]]
+// CHECK9-NEXT: [[TMP54:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK9-NEXT: ret i32 [[TMP54]]
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
@@ -877,89 +877,85 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75
-// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
+// CHECK9-SAME: (i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
// CHECK9-NEXT: entry:
-// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
-// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
+// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
+// CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
// CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 128
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @.omp_outlined..4, ptr [[TMP1]], ptr [[T_VAR1]], ptr [[TMP2]], ptr [[TMP3]])
+// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
+// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
+// CHECK9-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
+// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @.omp_outlined..4, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]])
// CHECK9-NEXT: ret void
//
//
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
-// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
+// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
-// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
-// CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128
-// CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128
+// CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128
+// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128
// CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
-// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
-// CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
+// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
+// CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
-// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
+// CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
// CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
// CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 128
-// CHECK9-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 128
-// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC2]], ptr align 128 [[TMP0]], i64 8, i1 false)
-// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
-// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
-// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
+// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i64 8, i1 false)
+// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
+// CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
+// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK9: omp.arraycpy.body:
-// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])
// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])
// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
// CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
-// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
-// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
-// CHECK9: omp.arraycpy.done4:
-// CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
-// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR5]], ptr nonnull align 4 dereferenceable(4) [[TMP3]], ptr [[AGG_TMP6]])
-// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
-// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR1]], align 128
-// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0
-// CHECK9-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 128
-// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0
-// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX7]], ptr align 128 [[VAR5]], i64 4, i1 false)
-// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
-// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
-// CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2
+// CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
+// CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK9: omp.arraycpy.done3:
+// CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
+// CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])
+// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
+// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
+// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0
+// CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128
+// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i64 0, i64 0
+// CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i64 4, i1 false)
+// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]
+// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
+// CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2
// CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK9: arraydestroy.body:
-// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
-// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
-// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
-// CHECK9: arraydestroy.done9:
+// CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
+// CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK9: arraydestroy.done8:
// CHECK9-NEXT: ret void
//
//
@@ -989,31 +985,27 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
-// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] {
+// CHECK9-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] {
// CHECK9-NEXT: entry:
-// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
-// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR1]], align 128
-// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..7, ptr [[T_VAR1]])
+// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
+// CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
+// CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
+// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
+// CHECK9-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
+// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
+// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..7, i64 [[TMP1]])
// CHECK9-NEXT: ret void
//
//
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7
-// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] {
+// CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
+// CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
-// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR1]], align 128
+// CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
// CHECK9-NEXT: ret void
//
//
@@ -1438,14 +1430,16 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128
// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128
// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128
+// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
// CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
// CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
-// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 4
-// CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 4
-// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 4
-// CHECK11-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
+// CHECK11-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4
+// CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x ptr], align 4
+// CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x ptr], align 4
+// CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x ptr], align 4
+// CHECK11-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
// CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]])
// CHECK11-NEXT: store i32 0, ptr [[T_VAR]], align 128
// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
@@ -1454,121 +1448,127 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
// CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
// CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3)
-// CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
-// CHECK11-NEXT: store ptr [[T_VAR]], ptr [[TMP0]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
-// CHECK11-NEXT: store ptr [[T_VAR]], ptr [[TMP1]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
-// CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
-// CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP3]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
-// CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 4
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
-// CHECK11-NEXT: store ptr null, ptr [[TMP5]], align 4
-// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
-// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP6]], align 4
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
-// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP7]], align 4
-// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
-// CHECK11-NEXT: store ptr null, ptr [[TMP8]], align 4
-// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
-// CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP9]], align 4
-// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
-// CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP10]], align 4
-// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
-// CHECK11-NEXT: store ptr null, ptr [[TMP11]], align 4
-// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
-// CHECK11-NEXT: store i32 2, ptr [[TMP14]], align 4
-// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
-// CHECK11-NEXT: store i32 4, ptr [[TMP15]], align 4
-// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
-// CHECK11-NEXT: store ptr [[TMP12]], ptr [[TMP16]], align 4
-// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
-// CHECK11-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 4
-// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
-// CHECK11-NEXT: store ptr @.offload_sizes.5, ptr [[TMP18]], align 4
-// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
-// CHECK11-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP19]], align 4
-// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
-// CHECK11-NEXT: store ptr null, ptr [[TMP20]], align 4
-// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
-// CHECK11-NEXT: store ptr null, ptr [[TMP21]], align 4
-// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
-// CHECK11-NEXT: store i64 0, ptr [[TMP22]], align 8
-// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
-// CHECK11-NEXT: store i64 0, ptr [[TMP23]], align 8
-// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
-// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP24]], align 4
-// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
-// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP25]], align 4
-// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
-// CHECK11-NEXT: store i32 0, ptr [[TMP26]], align 4
-// CHECK11-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, ptr [[KERNEL_ARGS]])
-// CHECK11-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
-// CHECK11-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
+// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128
+// CHECK11-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
+// CHECK11-NEXT: store ptr null, ptr [[TMP4]], align 4
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
+// CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 4
+// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
+// CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP6]], align 4
+// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
+// CHECK11-NEXT: store ptr null, ptr [[TMP7]], align 4
+// CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
+// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP8]], align 4
+// CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
+// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP9]], align 4
+// CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
+// CHECK11-NEXT: store ptr null, ptr [[TMP10]], align 4
+// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
+// CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP11]], align 4
+// CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
+// CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP12]], align 4
+// CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
+// CHECK11-NEXT: store ptr null, ptr [[TMP13]], align 4
+// CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
+// CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
+// CHECK11-NEXT: store i32 2, ptr [[TMP16]], align 4
+// CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
+// CHECK11-NEXT: store i32 4, ptr [[TMP17]], align 4
+// CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
+// CHECK11-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4
+// CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
+// CHECK11-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4
+// CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
+// CHECK11-NEXT: store ptr @.offload_sizes.5, ptr [[TMP20]], align 4
+// CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
+// CHECK11-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP21]], align 4
+// CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
+// CHECK11-NEXT: store ptr null, ptr [[TMP22]], align 4
+// CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
+// CHECK11-NEXT: store ptr null, ptr [[TMP23]], align 4
+// CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
+// CHECK11-NEXT: store i64 0, ptr [[TMP24]], align 8
+// CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
+// CHECK11-NEXT: store i64 0, ptr [[TMP25]], align 8
+// CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
+// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
+// CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
+// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
+// CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
+// CHECK11-NEXT: store i32 0, ptr [[TMP28]], align 4
+// CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, ptr [[KERNEL_ARGS]])
+// CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
+// CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
// CHECK11: omp_offload.failed:
-// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) #[[ATTR4]]
+// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32 [[TMP1]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) #[[ATTR4]]
// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
// CHECK11: omp_offload.cont:
-// CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
-// CHECK11-NEXT: store ptr [[T_VAR]], ptr [[TMP29]], align 4
-// CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
-// CHECK11-NEXT: store ptr [[T_VAR]], ptr [[TMP30]], align 4
-// CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0
-// CHECK11-NEXT: store ptr null, ptr [[TMP31]], align 4
-// CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0
-// CHECK11-NEXT: store i32 2, ptr [[TMP34]], align 4
-// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1
-// CHECK11-NEXT: store i32 1, ptr [[TMP35]], align 4
-// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2
-// CHECK11-NEXT: store ptr [[TMP32]], ptr [[TMP36]], align 4
-// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3
-// CHECK11-NEXT: store ptr [[TMP33]], ptr [[TMP37]], align 4
-// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4
-// CHECK11-NEXT: store ptr @.offload_sizes.8, ptr [[TMP38]], align 4
-// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5
-// CHECK11-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP39]], align 4
-// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6
-// CHECK11-NEXT: store ptr null, ptr [[TMP40]], align 4
-// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7
-// CHECK11-NEXT: store ptr null, ptr [[TMP41]], align 4
-// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8
-// CHECK11-NEXT: store i64 0, ptr [[TMP42]], align 8
-// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 9
-// CHECK11-NEXT: store i64 0, ptr [[TMP43]], align 8
-// CHECK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 10
-// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP44]], align 4
-// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 11
-// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP45]], align 4
-// CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 12
-// CHECK11-NEXT: store i32 0, ptr [[TMP46]], align 4
-// CHECK11-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS4]])
-// CHECK11-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0
-// CHECK11-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
-// CHECK11: omp_offload.failed5:
-// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(ptr [[T_VAR]]) #[[ATTR4]]
-// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]]
-// CHECK11: omp_offload.cont6:
+// CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[T_VAR]], align 128
+// CHECK11-NEXT: store i32 [[TMP31]], ptr [[T_VAR_CASTED1]], align 4
+// CHECK11-NEXT: [[TMP32:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4
+// CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK11-NEXT: store i32 [[TMP32]], ptr [[TMP33]], align 4
+// CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK11-NEXT: store i32 [[TMP32]], ptr [[TMP34]], align 4
+// CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
+// CHECK11-NEXT: store ptr null, ptr [[TMP35]], align 4
+// CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
+// CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
+// CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0
+// CHECK11-NEXT: store i32 2, ptr [[TMP38]], align 4
+// CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1
+// CHECK11-NEXT: store i32 1, ptr [[TMP39]], align 4
+// CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2
+// CHECK11-NEXT: store ptr [[TMP36]], ptr [[TMP40]], align 4
+// CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3
+// CHECK11-NEXT: store ptr [[TMP37]], ptr [[TMP41]], align 4
+// CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4
+// CHECK11-NEXT: store ptr @.offload_sizes.8, ptr [[TMP42]], align 4
+// CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5
+// CHECK11-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP43]], align 4
+// CHECK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6
+// CHECK11-NEXT: store ptr null, ptr [[TMP44]], align 4
+// CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7
+// CHECK11-NEXT: store ptr null, ptr [[TMP45]], align 4
+// CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8
+// CHECK11-NEXT: store i64 0, ptr [[TMP46]], align 8
+// CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9
+// CHECK11-NEXT: store i64 0, ptr [[TMP47]], align 8
+// CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10
+// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP48]], align 4
+// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11
+// CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP49]], align 4
+// CHECK11-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12
+// CHECK11-NEXT: store i32 0, ptr [[TMP50]], align 4
+// CHECK11-NEXT: [[TMP51:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS5]])
+// CHECK11-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0
+// CHECK11-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
+// CHECK11: omp_offload.failed6:
+// CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32 [[TMP32]]) #[[ATTR4]]
+// CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]]
+// CHECK11: omp_offload.cont7:
// CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
+// CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK11: arraydestroy.body:
-// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP49]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP53]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
-// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
-// CHECK11: arraydestroy.done7:
+// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK11: arraydestroy.done8:
// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
-// CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[RETVAL]], align 4
-// CHECK11-NEXT: ret i32 [[TMP50]]
+// CHECK11-NEXT: [[TMP54:%.*]] = load i32, ptr [[RETVAL]], align 4
+// CHECK11-NEXT: ret i32 [[TMP54]]
//
//
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
@@ -1678,89 +1678,85 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75
-// CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
+// CHECK11-SAME: (i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
// CHECK11-NEXT: entry:
-// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4
+// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
-// CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
-// CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
+// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
+// CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
// CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
// CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 128
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @.omp_outlined..4, ptr [[TMP1]], ptr [[T_VAR1]], ptr [[TMP2]], ptr [[TMP3]])
+// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @.omp_outlined..4, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]])
// CHECK11-NEXT: ret void
//
//
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
-// CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
+// CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
// CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
-// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4
+// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
-// CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
-// CHECK11-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128
-// CHECK11-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128
+// CHECK11-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128
+// CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128
// CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
-// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
-// CHECK11-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
+// CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128
+// CHECK11-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
-// CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
// CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
// CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 128
-// CHECK11-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 128
-// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC2]], ptr align 128 [[TMP0]], i32 8, i1 false)
-// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
-// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
-// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
+// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
+// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i32 8, i1 false)
+// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
+// CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
+// CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
+// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
// CHECK11: omp.arraycpy.body:
-// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
+// CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
// CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]])
// CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]])
// CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]]
// CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
// CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
-// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
-// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
-// CHECK11: omp.arraycpy.done4:
-// CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
-// CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR5]], ptr nonnull align 4 dereferenceable(4) [[TMP3]], ptr [[AGG_TMP6]])
-// CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]]
-// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR1]], align 128
-// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 0
-// CHECK11-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 128
-// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
-// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX7]], ptr align 128 [[VAR5]], i32 4, i1 false)
-// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
-// CHECK11-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
-// CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i32 2
+// CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
+// CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
+// CHECK11: omp.arraycpy.done3:
+// CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
+// CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]])
+// CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]]
+// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
+// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0
+// CHECK11-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128
+// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
+// CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i32 4, i1 false)
+// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]]
+// CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0
+// CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i32 2
// CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
// CHECK11: arraydestroy.body:
-// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
+// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
// CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
-// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
-// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
-// CHECK11: arraydestroy.done9:
+// CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
+// CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
+// CHECK11: arraydestroy.done8:
// CHECK11-NEXT: ret void
//
//
@@ -1790,31 +1786,27 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) {
//
//
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81
-// CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] {
+// CHECK11-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] {
// CHECK11-NEXT: entry:
-// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4
-// CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
-// CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR1]], align 128
-// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..7, ptr [[T_VAR1]])
+// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
+// CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
+// CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
+// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
+// CHECK11-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
+// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
+// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..7, i32 [[TMP1]])
// CHECK11-NEXT: ret void
//
//
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7
-// CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] {
+// CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] {
// CHECK11-NEXT: entry:
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4
-// CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128
+// CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
-// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128
-// CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR1]], align 128
+// CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
// CHECK11-NEXT: ret void
//
//
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