[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Andrzej Warzynski via Phabricator via cfe-commits]

awarzynski added inline comments.


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Comment at: flang/test/Driver/code-gen-rv64.f90:12
+
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
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sunshaoce wrote:
> awarzynski wrote:
> > awarzynski wrote:
> > > For those of us less familiar with RISC-V - could you explain what's significant about this line? For example, [[ https://github.com/llvm/llvm-project/blob/0aac9a2875bad4f065367e4a6553fad78605f895/flang/test/Driver/code-gen-aarch64.f90#L18 | here ]] it is made clear that with the right triple used, one should see a `ret` instruction within the main function (`_QQmain`). In here, I just see a "magic" number :)
> > Follow-up questions - what's "Flags" and why "0x5"? Is there any online documentation that you can refer to here?
> You can refer: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0/riscv-abi.pdf  `8.1. File Header` `e_flags` section
Thanks - and could you add a note in the test that explains where the "magic" 0x5 comes from?


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Comment at: flang/test/Driver/target-cpu-features.f90:33
 ! RUN: -o /dev/null -S %s 2>&1 | FileCheck %s -check-prefix=CHECK-INVALID-CPU
 
 ! RUN: %flang_fc1 -triple aarch64-linux-gnu -target-feature +superspeed \
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sunshaoce wrote:
> Without `REQUIRES` line, test will be failed here.
> 
> Due to this patch has little to do with CPU-feature, I think we can only add `code-gen-rv64.f90`. How about that?
This line verifies the driver diagnostics, i.e. it's very different to what other lines test in this file. You can safely move it to a dedicated file, e.g. "target-cpu-features-invalid.f90".


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  https://reviews.llvm.org/D145883/new/

https://reviews.llvm.org/D145883