[PATCH] D145883: [Flang][RISCV] Emit target features for RISC-V

[Andrzej Warzynski via Phabricator via cfe-commits]

awarzynski added inline comments.


================
Comment at: flang/test/Driver/code-gen-rv64.f90:2
+! Test -emit-obj (RISC-V 64)
+
+! RUN: rm -f %t.o
----------------
Missing `REQUIRES: ` - this test won't work unless the RISC-V backend is available. 


================
Comment at: flang/test/Driver/code-gen-rv64.f90:12
+
+! CHECK: Flags: 0x5, RVC, double-float ABI
+end program
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awarzynski wrote:
> For those of us less familiar with RISC-V - could you explain what's significant about this line? For example, [[ https://github.com/llvm/llvm-project/blob/0aac9a2875bad4f065367e4a6553fad78605f895/flang/test/Driver/code-gen-aarch64.f90#L18 | here ]] it is made clear that with the right triple used, one should see a `ret` instruction within the main function (`_QQmain`). In here, I just see a "magic" number :)
Follow-up questions - what's "Flags" and why "0x5"? Is there any online documentation that you can refer to here?


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https://reviews.llvm.org/D145883