[PATCH] D145794: [clang-format] Recognize Verilog always blocks

[sstwcw via Phabricator via cfe-commits]

sstwcw created this revision.
sstwcw added reviewers: HazardyKnusperkeks, MyDeveloperDay, owenpan, rymiel.
sstwcw added a project: clang-format.
Herald added a project: All.
sstwcw requested review of this revision.
Herald added a project: clang.
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The small `Coverage` test was added because we added the space rule
about 2 at signs along with the rule about onely 1 of it.  We have not
fully covered covergroup yet.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145794

Files:
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/lib/Format/UnwrappedLineParser.cpp
  clang/lib/Format/UnwrappedLineParser.h
  clang/unittests/Format/FormatTestVerilog.cpp

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