[PATCH] D144169: [WebAssembly] Fix simd bit shift intrinsics codegen

[JunMa via Phabricator via cfe-commits]

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According to github.com/WebAssembly/simd/blob/main/proposals/simd/SIMD.md,
the shift count of bit shift instructions is taken modulo lane width.
This patch adds such operation.

Fixes PR#60655


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144169

Files:
  clang/lib/Headers/wasm_simd128.h
  clang/test/Headers/wasm.c

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