[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

[Philip Reames via Phabricator via cfe-commits]

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This change adds the definition of the two extensions, but does not either a) make any instruction conditional on them or b) enabled the extensions by default.  (The *instructions* do remain enabled by default per ISA version 2.0 which is our current default.)

This is meant to be a building block towards something like https://reviews.llvm.org/D141666, and in the meantime, address one of the most surprising of the current user experience warts.  The current behavior of rejecting the extensions at the command line despite emitting code which appears to use them is surprising to anyone not deeply versed in the details of this situation.

Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA. These instructions were grouped into a set of new extensions (these), but were no longer required by the base ISA. This change is described in “Preface to Document Version 20190608-Base-Ratified” from the specification document.

As LLVM currently implements only version 2.0 of the base specification, accepting these extensions at the command line introduces a configuration which doesn't actually match any spec version.  It's a pretty harmless variant since the 2.0 extension definitions, to my knowledge, exactly match the text from the 2.0 I text before they were moved into standalone extensions in 2.1 of I.  (The version numbering in that sentence is a tad confusing to say the least.  Hopefully I got it right.)

If we decide we don't want to accept this variant, the other obvious near term option would be to detect and error with a more helpful error message.

Worth noting is that we're setting precedent here.  There's at least one other case I know of which is analogous (counters), and others may come up in the future.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143953

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

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