[PATCH] D143825: [clang-format] Put ports on separate lines in Verilog module headers

[sstwcw via Phabricator via cfe-commits]

sstwcw created this revision.
sstwcw added reviewers: HazardyKnusperkeks, MyDeveloperDay, curdeius, owenpan, rymiel.
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sstwcw requested review of this revision.
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New:

  module mh1
      (input var int in1,
       input var in2, in3,
       output tagged_st out);
  endmodule

Old:

  module mh1
      (input var int in1, input var in2, in3, output tagged_st out);
  endmodule

`getNextNonComment` was modified to return a non-const pointer because
we needed to use it that way in `verilogGroupDecl`.

The comment on line 2620 was a typo.  We corrected it while modifying
the function.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143825

Files:
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/unittests/Format/FormatTestVerilog.cpp

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