[PATCH] D142891: [clang-format] Recognize Verilog non-blocking assignment

[sstwcw via Phabricator via cfe-commits]

sstwcw marked an inline comment as done.
sstwcw added inline comments.


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Comment at: clang/lib/Format/WhitespaceManager.cpp:839-846
         return Style.AlignConsecutiveAssignments.AlignCompound
                    ? C.Tok->getPrecedence() == prec::Assignment
-                   : C.Tok->is(tok::equal);
+                   : C.Tok->is(tok::equal) ||
+                         // In Verilog the '<=' is not a compound assignment,
+                         // thus it is aligned even when the AlignCompound
+                         // option is not set.
+                         (Style.isVerilog() && C.Tok->is(tok::lessequal) &&
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HazardyKnusperkeks wrote:
> Do you need the extra case, or could you just activate `AlignCompound`?
> 
> If you do, can you please add parens, the precedence of `?` and `:` in combination with `||` is at least for me not 100% clear.
If I get you right, you are suggesting that `AlignCompound: false` is there only for backward compatibility, and we can make it default to true since we don't have to maintain backward compatibility for new things.  I prefer consistency.


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  https://reviews.llvm.org/D142891/new/

https://reviews.llvm.org/D142891