[clang] 42c36da - [RISCV] Add MC support of RISCV Zcb Extension
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Thu Jan 26 12:54:15 PST 2023
Author: WuXinlong
Date: 2023-01-26T12:54:00-08:00
New Revision: 42c36da9c99b84ca7bc843a27ff0da29f5bf8a74
URL: https://github.com/llvm/llvm-project/commit/42c36da9c99b84ca7bc843a27ff0da29f5bf8a74
DIFF: https://github.com/llvm/llvm-project/commit/42c36da9c99b84ca7bc843a27ff0da29f5bf8a74.diff
LOG: [RISCV] Add MC support of RISCV Zcb Extension
This patch add the instructions of Zcb extension.
Instructions in zcb extensions shorten part of bit manipulation instructions.
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D131141
Added:
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
llvm/test/MC/RISCV/rv32zcb-invalid.s
llvm/test/MC/RISCV/rv32zcb-valid.s
llvm/test/MC/RISCV/rv64zcb-valid.s
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Removed:
################################################################################
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 91ab4219ea344..2e264369e1bff 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -44,6 +44,8 @@
// CHECK-NOT: __riscv_svpbmt
// CHECK-NOT: __riscv_svinval
// CHECK-NOT: __riscv_xventanacondops
+// CHECK-NOT: __riscv_zca
+// CHECK-NOT: __riscv_zcb
// CHECK-NOT: __riscv_zcd
// CHECK-NOT: __riscv_zcf
// CHECK-NOT: __riscv_h
@@ -464,6 +466,19 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADVDOT-EXT %s
// CHECK-XTHEADVDOT-EXT: __riscv_xtheadvdot 1000000{{$}}
+// RUN: %clang -target riscv32 -march=rv32izca0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izca0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s
+// CHECK-ZCA-EXT: __riscv_zca 70000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32izcb0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izcb0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s
+// CHECK-ZCB-EXT: __riscv_zca 70000{{$}}
+// CHECK-ZCB-EXT: __riscv_zcb 70000{{$}}
+
// RUN: %clang -target riscv32 -march=rv32izcd0p70 -menable-experimental-extensions \
// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
// RUN: %clang -target riscv64 -march=rv64izcd0p70 -menable-experimental-extensions \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 9db22bbf9b5a8..18d848a174358 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -144,6 +144,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zcf``
LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.
+``experimental-zcb``
+ LLVM implements the `0.70 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV>`_.
+
``experimental-zihintntl``
LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`_.
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index b3f6867ca2806..71ff2cb3b9166 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -100,6 +100,8 @@ Changes to the PowerPC Backend
Changes to the RISC-V Backend
-----------------------------
+* Assembler support for the Zcb extension was added.
+
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 1b1bff023d2f2..4122f5892c068 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -115,6 +115,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zihintntl", RISCVExtensionVersion{0, 2}},
{"zca", RISCVExtensionVersion{0, 70}},
+ {"zcb", RISCVExtensionVersion{0, 70}},
{"zcd", RISCVExtensionVersion{0, 70}},
{"zcf", RISCVExtensionVersion{0, 70}},
{"zvfh", RISCVExtensionVersion{0, 1}},
@@ -826,6 +827,7 @@ static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
static const char *ImpliedExtsZvfh[] = {"zve32f"};
static const char *ImpliedExtsXTHeadVdot[] = {"v"};
+static const char *ImpliedExtsZcb[] = {"zca"};
struct ImpliedExtsEntry {
StringLiteral Name;
@@ -842,6 +844,7 @@ struct ImpliedExtsEntry {
static constexpr ImpliedExtsEntry ImpliedExts[] = {
{{"v"}, {ImpliedExtsV}},
{{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
+ {{"zcb"}, {ImpliedExtsZcb}},
{{"zdinx"}, {ImpliedExtsZdinx}},
{{"zfh"}, {ImpliedExtsZfh}},
{{"zfhmin"}, {ImpliedExtsZfhmin}},
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 9752e398bd991..059cb2f613c7e 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -618,6 +618,16 @@ struct RISCVOperand : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
}
+ bool isUImm2Lsb0() const {
+ if (!isImm())
+ return false;
+ int64_t Imm;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm && isShiftedUInt<1, 1>(Imm) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
bool isUImm7Lsb00() const {
if (!isImm())
return false;
@@ -1151,6 +1161,9 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
case Match_InvalidUImm2:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1);
+ case Match_InvalidUImm2Lsb0:
+ return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 2,
+ "immediate must be one of");
case Match_InvalidUImm3:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1);
case Match_InvalidUImm5:
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 2cf2045c17199..005dac5d13ed0 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -43,7 +43,8 @@ enum {
InstFormatCA = 14,
InstFormatCB = 15,
InstFormatCJ = 16,
- InstFormatOther = 17,
+ InstFormatCSZN = 17,
+ InstFormatOther = 18,
InstFormatMask = 31,
InstFormatShift = 0,
@@ -234,6 +235,7 @@ namespace RISCVOp {
enum OperandType : unsigned {
OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
+ OPERAND_UIMM2_LSB0,
OPERAND_UIMM3,
OPERAND_UIMM4,
OPERAND_UIMM5,
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index be8834fd4c2f5..796f3399cf538 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -299,6 +299,14 @@ def HasStdExtCOrZca
"'Zca' (part of the C extension, excluding "
"compressed floating point loads/stores)">;
+def FeatureExtZcb
+ : SubtargetFeature<"experimental-zcb", "HasStdExtZcb", "true",
+ "'Zcb' (Compressed basic bit manipulation instructions)",
+ [FeatureExtZca]>;
+def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
+ AssemblerPredicate<(all_of FeatureExtZcb),
+ "'Zcb' (Compressed basic bit manipulation instructions)">;
+
def FeatureExtZcd
: SubtargetFeature<"experimental-zcd", "HasStdExtZcd", "true",
"'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 3a494a5e3b58b..5105e9fd77229 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -47,7 +47,8 @@ def InstFormatCS : InstFormat<13>;
def InstFormatCA : InstFormat<14>;
def InstFormatCB : InstFormat<15>;
def InstFormatCJ : InstFormat<16>;
-def InstFormatOther : InstFormat<17>;
+def InstFormatCSZN : InstFormat<17>;
+def InstFormatOther : InstFormat<18>;
class RISCVVConstraint<bits<3> val> {
bits<3> Value = val;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 690bec5181e2a..f3da5ef22038d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -157,3 +157,14 @@ class RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
let Inst{2} = offset{4};
let Inst{1-0} = opcode;
}
+
+class RVInst16CSZN<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs,
+ dag ins, string opcodestr, string argstr>
+ : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSZN>{
+ bits<3> rd;
+
+ let Inst{15-10} = funct6;
+ let Inst{9-7} = rd;
+ let Inst{6-2} = funct5;
+ let Inst{1-0} = opcode;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 6494c9a2cd9dc..75311e313a8cf 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1620,6 +1620,12 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
CASE_OPERAND_UIMM(4)
CASE_OPERAND_UIMM(5)
CASE_OPERAND_UIMM(7)
+ CASE_OPERAND_UIMM(12)
+ CASE_OPERAND_UIMM(20)
+ // clang-format on
+ case RISCVOp::OPERAND_UIMM2_LSB0:
+ Ok = isShiftedUInt<1, 1>(Imm);
+ break;
case RISCVOp::OPERAND_UIMM7_LSB00:
Ok = isShiftedUInt<5, 2>(Imm);
break;
@@ -1629,9 +1635,6 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_UIMM8_LSB000:
Ok = isShiftedUInt<5, 3>(Imm);
break;
- CASE_OPERAND_UIMM(12)
- CASE_OPERAND_UIMM(20)
- // clang-format on
case RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO:
Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0);
break;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index c699a94943d82..5bb7beeff5597 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -191,11 +191,17 @@ def uimmlog2xlen : Operand<XLenVT>, ImmLeaf<XLenVT, [{
let OperandNamespace = "RISCVOp";
}
-def uimm2 : Operand<XLenVT> {
+def uimm2 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]> {
let ParserMatchClass = UImmAsmOperand<2>;
let DecoderMethod = "decodeUImmOperand<2>";
let OperandType = "OPERAND_UIMM2";
let OperandNamespace = "RISCVOp";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isUInt<2>(Imm);
+ }];
}
def uimm3 : Operand<XLenVT> {
@@ -1853,6 +1859,7 @@ include "RISCVInstrInfoF.td"
include "RISCVInstrInfoD.td"
include "RISCVInstrInfoC.td"
include "RISCVInstrInfoZb.td"
+include "RISCVInstrInfoZc.td"
include "RISCVInstrInfoZk.td"
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZfh.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
new file mode 100644
index 0000000000000..40ca23aad59ee
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -0,0 +1,180 @@
+//===-- RISCVInstrInfoZc.td - RISC-V 'Zc*' instructions ----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions from the 'Zc*' compressed
+/// instruction extensions, version 0.70.4.
+/// This version is still experimental as the 'Zc*' extensions haven't been
+/// ratified yet.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def uimm2_lsb0 : Operand<XLenVT>,
+ ImmLeaf<XLenVT, [{return isShiftedUInt<1, 1>(Imm);}]> {
+ let ParserMatchClass = UImmAsmOperand<2, "Lsb0">;
+ let EncoderMethod = "getImmOpValue";
+ let DecoderMethod = "decodeUImmOperand<2>";
+ let OperandType = "OPERAND_UIMM2_LSB0";
+ let OperandNamespace = "RISCVOp";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isShiftedUInt<1, 1>(Imm);
+ }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVZcArith_r<bits<5> funct5, string OpcodeStr> :
+ RVInst16CSZN<0b100111, funct5, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd),
+ OpcodeStr, "$rd"> {
+ let Constraints = "$rd = $rd_wb";
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in
+def C_ZEXT_W : RVZcArith_r<0b11100 , "c.zext.w">,
+ Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
+
+let Predicates = [HasStdExtZcb, HasStdExtZbb] in {
+def C_ZEXT_H : RVZcArith_r<0b11010 , "c.zext.h">,
+ Sched<[WriteIALU, ReadIALU]>;
+def C_SEXT_B : RVZcArith_r<0b11001 , "c.sext.b">,
+ Sched<[WriteIALU, ReadIALU]>;
+def C_SEXT_H : RVZcArith_r<0b11011 , "c.sext.h">,
+ Sched<[WriteIALU, ReadIALU]>;
+}
+
+let Predicates = [HasStdExtZcb] in
+def C_ZEXT_B : RVZcArith_r<0b11000 , "c.zext.b">,
+ Sched<[WriteIALU, ReadIALU]>;
+
+let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in
+def C_MUL : CA_ALU<0b100111, 0b10, "c.mul", GPRC>,
+ Sched<[WriteIMul, ReadIMul, ReadIMul]>;
+
+let Predicates = [HasStdExtZcb] in {
+def C_NOT : RVZcArith_r<0b11101 , "c.not">,
+ Sched<[WriteIALU, ReadIALU]>;
+
+def C_LBU : CLoad_ri<0b100, "c.lbu", GPRC, uimm2>,
+ Sched<[WriteLDB, ReadMemBase]> {
+ bits<2> imm;
+
+ let Inst{12-10} = 0b000;
+ let Inst{6-5} = imm{0,1};
+}
+
+def C_LHU : CLoad_ri<0b100, "c.lhu", GPRC, uimm2_lsb0>,
+ Sched<[WriteLDH, ReadMemBase]> {
+ bits<2> imm;
+
+ let Inst{12-10} = 0b001;
+ let Inst{6} = 0b0;
+ let Inst{5} = imm{1};
+}
+
+def C_LH : CLoad_ri<0b100, "c.lh", GPRC, uimm2_lsb0>,
+ Sched<[WriteLDH, ReadMemBase]> {
+ bits<2> imm;
+
+ let Inst{12-10} = 0b001;
+ let Inst{6} = 0b1;
+ let Inst{5} = imm{1};
+}
+
+def C_SB : CStore_rri<0b100, "c.sb", GPRC, uimm2>,
+ Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
+ bits<2> imm;
+
+ let Inst{12-10} = 0b010;
+ let Inst{6-5} = imm{0,1};
+}
+
+def C_SH : CStore_rri<0b100, "c.sh", GPRC, uimm2_lsb0>,
+ Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {
+ bits<2> imm;
+
+ let Inst{12-10} = 0b011;
+ let Inst{6} = 0b1;
+ let Inst{5} = imm{1};
+}
+}
+
+let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in{
+def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
+ (C_MUL GPRC:$rs1, GPRC:$rs2)>;
+let isCompressOnly = true in
+def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
+ (C_MUL GPRC:$rs1, GPRC:$rs2)>;
+} // Predicates = [HasStdExtZcb, HasStdExtMOrZmmul]
+
+let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
+def : CompressPat<(SEXT_B GPRC:$rs1, GPRC:$rs1),
+ (C_SEXT_B GPRC:$rs1, GPRC:$rs1)>;
+def : CompressPat<(SEXT_H GPRC:$rs1, GPRC:$rs1),
+ (C_SEXT_H GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb, HasStdExtZbb]
+
+let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
+def : CompressPat<(ZEXT_H_RV32 GPRC:$rs1, GPRC:$rs1),
+ (C_ZEXT_H GPRC:$rs1, GPRC:$rs1)>;
+def : CompressPat<(ZEXT_H_RV64 GPRC:$rs1, GPRC:$rs1),
+ (C_ZEXT_H GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb, HasStdExtZbb]
+
+let Predicates = [HasStdExtZcb] in{
+def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, 255),
+ (C_ZEXT_B GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb]
+
+let Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64] in{
+def : CompressPat<(ADD_UW GPRC:$rs1, GPRC:$rs1, X0),
+ (C_ZEXT_W GPRC:$rs1, GPRC:$rs1)>;
+} // Predicates = [HasStdExtZcb, HasStdExtZba, IsRV64]
+
+let Predicates = [HasStdExtZcb] in{
+def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1),
+ (C_NOT GPRC:$rs1, GPRC:$rs1)>;
+}
+
+let Predicates = [HasStdExtZcb] in{
+def : CompressPat<(LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm),
+ (C_LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm)>;
+def : CompressPat<(LHU GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm),
+ (C_LHU GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
+def : CompressPat<(LH GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm),
+ (C_LH GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
+def : CompressPat<(SB GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm),
+ (C_SB GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm)>;
+def : CompressPat<(SH GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm),
+ (C_SH GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
+}// Predicates = [HasStdExtZcb]
+
+
+//===----------------------------------------------------------------------===//
+// Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZcb] in {
+def : InstAlias<"c.lbu $rd, (${rs1})",(C_LBU GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.lhu $rd, (${rs1})",(C_LHU GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.lh $rd, (${rs1})", (C_LH GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.sb $rd, (${rs1})", (C_SB GPRC:$rd, GPRC:$rs1, 0)>;
+def : InstAlias<"c.sh $rd, (${rs1})", (C_SH GPRC:$rd, GPRC:$rs1, 0)>;
+}
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 664bc0ed368cd..d19149a2fe45a 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -41,6 +41,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefix=RV32SVPBMT %s
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefix=RV32ZCB %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
@@ -87,6 +88,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefix=RV64ZCB %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
@@ -129,6 +131,7 @@
; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
+; RV32ZCB: .attribute 5, "rv32i2p0_zca0p70_zcb0p70"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -175,6 +178,7 @@
; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70"
+; RV64ZCB: .attribute 5, "rv64i2p0_zca0p70_zcb0p70"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index af34567929d60..27ea6f498af45 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -179,6 +179,9 @@
.attribute arch, "rv32izca0p70"
# CHECK: attribute 5, "rv32i2p0_zca0p70"
+.attribute arch, "rv32izcb0p70"
+# CHECK: attribute 5, "rv32i2p0_zca0p70_zcb0p70"
+
.attribute arch, "rv32izawrs1p0"
# CHECK: attribute 5, "rv32i2p0_zawrs1p0"
diff --git a/llvm/test/MC/RISCV/rv32zcb-invalid.s b/llvm/test/MC/RISCV/rv32zcb-invalid.s
new file mode 100644
index 0000000000000..9ffb0291887e0
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zcb-invalid.s
@@ -0,0 +1,19 @@
+# RUN: not llvm-mc -triple=riscv32 -mattr=experimental-zcb -riscv-no-aliases -show-encoding %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=experimental-zcb -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s
+
+# CHECK-ERROR: error: immediate must be an integer in the range [0, 3]
+c.lbu a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be one of [0, 2]
+c.lhu a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be one of [0, 2]
+c.lh a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be an integer in the range [0, 3]
+c.sb a5, 10(a4)
+
+# CHECK-ERROR: error: immediate must be one of [0, 2]
+c.sh a5, 10(a4)
diff --git a/llvm/test/MC/RISCV/rv32zcb-valid.s b/llvm/test/MC/RISCV/rv32zcb-valid.s
new file mode 100644
index 0000000000000..88f891e3edb9e
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zcb-valid.s
@@ -0,0 +1,140 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+m,+zbb,+zba,+experimental-zcb -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+m,+zbb,+zba,+experimental-zcb < %s \
+# RUN: | llvm-objdump --mattr=+m,+zbb,+zba,+experimental-zcb -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb < %s \
+# RUN: | llvm-objdump --mattr=+m,+zbb,+zba,experimental-zcb -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: c.zext.b s0
+# CHECK-ASM: encoding: [0x61,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.zext.b s0
+
+# CHECK-ASM-AND-OBJ: c.sext.b s0
+# CHECK-ASM: encoding: [0x65,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation), 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.sext.b s0
+
+# CHECK-ASM-AND-OBJ: c.zext.h s0
+# CHECK-ASM: encoding: [0x69,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation), 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.zext.h s0
+
+# CHECK-ASM-AND-OBJ: c.sext.h s0
+# CHECK-ASM: encoding: [0x6d,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation), 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.sext.h s0
+
+# CHECK-ASM-AND-OBJ: c.not s0
+# CHECK-ASM: encoding: [0x75,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.not s0
+
+# CHECK-ASM-AND-OBJ: c.mul s0, s1
+# CHECK-ASM: encoding: [0x45,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'M' (Integer Multiplication and Division) or 'Zmmul' (Integer Multiplication), 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.mul s0, s1
+
+# CHECK-ASM-AND-OBJ: c.lbu a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x83]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.lbu a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lhu a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x87]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.lhu a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lh a5, 2(a4)
+# CHECK-ASM: encoding: [0x7c,0x87]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.lh a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.sb a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x8b]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.sb a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.sh a5, 2(a4)
+# CHECK-ASM: encoding: [0x7c,0x8f]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+c.sh a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.mul s0, s1
+# CHECK-ASM: encoding: [0x45,0x9c]
+mul s0, s1, s0
+
+# CHECK-ASM-AND-OBJ: c.mul s0, s1
+# CHECK-ASM: encoding: [0x45,0x9c]
+mul s0, s0, s1
+
+# CHECK-ASM-AND-OBJ: c.sext.b s0
+# CHECK-ASM: encoding: [0x65,0x9c]
+sext.b s0, s0
+
+# CHECK-ASM-AND-OBJ: c.sext.h s0
+# CHECK-ASM: encoding: [0x6d,0x9c]
+sext.h s0, s0
+
+# CHECK-ASM-AND-OBJ: c.zext.h s0
+# CHECK-ASM: encoding: [0x69,0x9c]
+zext.h s0, s0
+
+# CHECK-ASM-AND-OBJ: c.zext.b s0
+# CHECK-ASM: encoding: [0x61,0x9c]
+andi s0, s0, 255
+
+# CHECK-ASM-AND-OBJ: c.not s0
+# CHECK-ASM: encoding: [0x75,0x9c]
+xori s0, s0, -1
+
+# CHECK-ASM-AND-OBJ: c.lh a5, 2(a4)
+# CHECK-ASM: encoding: [0x7c,0x87]
+lh a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lbu a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x83]
+lbu a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lhu a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x87]
+lhu a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.sb a5, 2(a4)
+# CHECK-ASM: encoding: [0x3c,0x8b]
+sb a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.sh a5, 2(a4)
+# CHECK-ASM: encoding: [0x7c,0x8f]
+sh a5, 2(a4)
+
+# CHECK-ASM-AND-OBJ: c.lbu s0, 0(s1)
+# CHECK-ASM: encoding: [0x80,0x80]
+c.lbu s0, (s1)
+
+# CHECK-ASM-AND-OBJ: c.lhu s0, 0(s1)
+# CHECK-ASM: encoding: [0x80,0x84]
+c.lhu s0, (s1)
+
+# CHECK-ASM-AND-OBJ: c.lh s0, 0(s1)
+# CHECK-ASM: encoding: [0xc0,0x84]
+c.lh s0, (s1)
+
+# CHECK-ASM-AND-OBJ: c.sb s0, 0(s1)
+# CHECK-ASM: encoding: [0x80,0x88]
+c.sb s0, (s1)
+
+# CHECK-ASM-AND-OBJ: c.sh s0, 0(s1)
+# CHECK-ASM: encoding: [0xc0,0x8c]
+c.sh s0, (s1)
diff --git a/llvm/test/MC/RISCV/rv64zcb-valid.s b/llvm/test/MC/RISCV/rv64zcb-valid.s
new file mode 100644
index 0000000000000..c41997f52244e
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zcb-valid.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+m,+zbb,+zba,+experimental-zcb < %s \
+# RUN: | llvm-objdump --mattr=+m,+zbb,+zba,experimental-zcb -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+m,+zbb,+zba,+experimental-zcb \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-RV64 %s
+
+# CHECK-ASM-AND-OBJ: c.zext.w s0
+# CHECK-ASM: encoding: [0x71,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zba' (Address Generation Instructions), 'Zcb' (Compressed basic bit manipulation instructions){{$}}
+# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+c.zext.w s0
+
+# CHECK-ASM-AND-OBJ: c.zext.w s0
+# CHECK-ASM: encoding: [0x71,0x9c]
+add.uw s0, s0, zero
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