[clang] 1a803e0 - [12/15][Clang][RISCV][NFC] Refine the way to check for Policy in riscv_vector_builtin_cg.inc
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Tue Jan 24 08:28:07 PST 2023
Author: eopXD
Date: 2023-01-24T08:28:01-08:00
New Revision: 1a803e0b2ad7ea9cfe7fc832210f537fce3f5a51
URL: https://github.com/llvm/llvm-project/commit/1a803e0b2ad7ea9cfe7fc832210f537fce3f5a51
DIFF: https://github.com/llvm/llvm-project/commit/1a803e0b2ad7ea9cfe7fc832210f537fce3f5a51.diff
LOG: [12/15][Clang][RISCV][NFC] Refine the way to check for Policy in riscv_vector_builtin_cg.inc
The current way creates a fallacy that checking for
`PolicyAttrs == TAIL_AGNOSTIC` is implicitly equivalant to
`TAIL_AGNOSTIC_MASK_UNDISTURBED`. This works under the assumption that
an unmasked intrinsic has a policy of TAMU. The expression here is
mis-leading and will not be correct when the default policy is not
TAMU.
As this patch-set targets to change the default policy from TAMU to
TAMA, this commit is necessary before changing the default.
This is the 12th commit of a patch-set that aims to change the default policy
for RVV intrinsics from TAMU to TAMA.
Please refer to the cover letter in the 1st commit (D141573) for an
overview.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D141789
Added:
Modified:
clang/include/clang/Basic/riscv_vector.td
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/CodeGen/CGBuiltin.cpp
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index b72eee6ccd18..c63cba9aa459 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -467,10 +467,10 @@ let UnMaskedPolicyScheme = HasPassthruOperand,
ManualCodegen = [{
if (IsMasked) {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- if (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+ if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
} else {
- if (PolicyAttrs == TAIL_AGNOSTIC)
+ if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
}
@@ -649,12 +649,12 @@ multiclass RVVVLEFFBuiltin<list<string> types> {
if (IsMasked) {
// Move mask to right before vl.
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- if (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+ if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
IntrinsicTypes = {ResultType, Ops[4]->getType()};
} else {
- if (PolicyAttrs == TAIL_AGNOSTIC)
+ if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
IntrinsicTypes = {ResultType, Ops[3]->getType()};
}
@@ -939,8 +939,8 @@ multiclass RVVUnitStridedSegLoad<string op> {
SmallVector<llvm::Value*, 12> Operands;
// Please refer to comment under 'defvar NFList' in this file
- if ((IsMasked && PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) ||
- (!IsMasked && PolicyAttrs == TAIL_AGNOSTIC))
+ if ((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
+ (!IsMasked && PolicyAttrs & RVV_VTA))
Operands.append(NF, llvm::PoisonValue::get(ResultType));
else {
if (IsMasked)
@@ -949,8 +949,8 @@ multiclass RVVUnitStridedSegLoad<string op> {
Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF);
}
unsigned PtrOperandIdx = IsMasked ?
- (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) ? NF + 1 : 2 * NF + 1 :
- (PolicyAttrs == TAIL_AGNOSTIC) ? NF : 2 * NF;
+ ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ? NF + 1 : 2 * NF + 1 :
+ (PolicyAttrs & RVV_VTA) ? NF : 2 * NF;
Value *PtrOperand = Ops[PtrOperandIdx];
Value *VLOperand = Ops[PtrOperandIdx + 1];
Operands.push_back(PtrOperand);
@@ -1004,8 +1004,8 @@ multiclass RVVUnitStridedSegLoadFF<string op> {
SmallVector<llvm::Value*, 12> Operands;
// Please refer to comment under 'defvar NFList' in this file
- if ((IsMasked && PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) ||
- (!IsMasked && PolicyAttrs == TAIL_AGNOSTIC))
+ if ((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
+ (!IsMasked && PolicyAttrs & RVV_VTA))
Operands.append(NF, llvm::PoisonValue::get(ResultType));
else {
if (IsMasked)
@@ -1014,8 +1014,8 @@ multiclass RVVUnitStridedSegLoadFF<string op> {
Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF);
}
unsigned PtrOperandIdx = IsMasked ?
- (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) ? NF + 1 : 2 * NF + 1 :
- (PolicyAttrs == TAIL_AGNOSTIC) ? NF : 2 * NF;
+ ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ? NF + 1 : 2 * NF + 1 :
+ (PolicyAttrs & RVV_VTA) ? NF : 2 * NF;
Value *PtrOperand = Ops[PtrOperandIdx];
Value *NewVLOperand = Ops[PtrOperandIdx + 1];
Value *VLOperand = Ops[PtrOperandIdx + 2];
@@ -1071,8 +1071,8 @@ multiclass RVVStridedSegLoad<string op> {
SmallVector<llvm::Value*, 12> Operands;
// Please refer to comment under 'defvar NFList' in this file
- if ((IsMasked && PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) ||
- (!IsMasked && PolicyAttrs == TAIL_AGNOSTIC))
+ if ((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
+ (!IsMasked && PolicyAttrs & RVV_VTA))
Operands.append(NF, llvm::PoisonValue::get(ResultType));
else {
if (IsMasked)
@@ -1081,8 +1081,8 @@ multiclass RVVStridedSegLoad<string op> {
Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF);
}
unsigned PtrOperandIdx = IsMasked ?
- (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) ? NF + 1 : 2 * NF + 1 :
- (PolicyAttrs == TAIL_AGNOSTIC) ? NF : 2 * NF;
+ ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ? NF + 1 : 2 * NF + 1 :
+ (PolicyAttrs & RVV_VTA) ? NF : 2 * NF;
Value *PtrOperand = Ops[PtrOperandIdx];
Value *StrideOperand = Ops[PtrOperandIdx + 1];
Value *VLOperand = Ops[PtrOperandIdx + 2];
@@ -1133,8 +1133,8 @@ multiclass RVVIndexedSegLoad<string op> {
SmallVector<llvm::Value*, 12> Operands;
// Please refer to comment under 'defvar NFList' in this file
- if ((IsMasked && PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) ||
- (!IsMasked && PolicyAttrs == TAIL_AGNOSTIC))
+ if ((IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
+ (!IsMasked && PolicyAttrs & RVV_VTA))
Operands.append(NF, llvm::PoisonValue::get(ResultType));
else {
if (IsMasked)
@@ -1143,8 +1143,8 @@ multiclass RVVIndexedSegLoad<string op> {
Operands.append(Ops.begin() + NF, Ops.begin() + 2 * NF);
}
unsigned PtrOperandIdx = IsMasked ?
- (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC) ? NF + 1 : 2 * NF + 1 :
- (PolicyAttrs == TAIL_AGNOSTIC) ? NF : 2 * NF;
+ ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ? NF + 1 : 2 * NF + 1 :
+ (PolicyAttrs & RVV_VTA) ? NF : 2 * NF;
Value *PtrOperand = Ops[PtrOperandIdx];
Value *IndexOperand = Ops[PtrOperandIdx + 1];
Value *VLOperand = Ops[PtrOperandIdx + 2];
@@ -1333,10 +1333,10 @@ multiclass RVVPseudoUnaryBuiltin<string IR, string type_range> {
{
if (IsMasked) {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- if (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+ if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
} else {
- if (PolicyAttrs == TAIL_AGNOSTIC)
+ if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
}
auto ElemTy = cast<llvm::VectorType>(ResultType)->getElementType();
@@ -1366,10 +1366,10 @@ multiclass RVVPseudoVNotBuiltin<string IR, string type_range> {
{
if (IsMasked) {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- if (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+ if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
} else {
- if (PolicyAttrs == TAIL_AGNOSTIC)
+ if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
}
auto ElemTy = cast<llvm::VectorType>(ResultType)->getElementType();
@@ -1421,7 +1421,7 @@ multiclass RVVPseudoVFUnaryBuiltin<string IR, string type_range> {
{
if (IsMasked) {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- if (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+ if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
Ops.insert(Ops.begin() + 2, Ops[1]);
Ops.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
@@ -1430,7 +1430,7 @@ multiclass RVVPseudoVFUnaryBuiltin<string IR, string type_range> {
Ops[2]->getType(),
Ops.back()->getType()};
} else {
- if (PolicyAttrs == TAIL_AGNOSTIC)
+ if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
// op1, po2, vl
IntrinsicTypes = {ResultType,
@@ -1456,10 +1456,10 @@ multiclass RVVPseudoVWCVTBuiltin<string IR, string MName, string type_range,
{
if (IsMasked) {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- if (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+ if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
} else {
- if (PolicyAttrs == TAIL_AGNOSTIC)
+ if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
}
auto ElemTy = cast<llvm::VectorType>(ResultType)->getElementType();
@@ -1498,10 +1498,10 @@ multiclass RVVPseudoVNCVTBuiltin<string IR, string MName, string type_range,
{
if (IsMasked) {
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- if (PolicyAttrs == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+ if ((PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA))
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
} else {
- if (PolicyAttrs == TAIL_AGNOSTIC)
+ if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
}
Ops.insert(Ops.begin() + 2, llvm::Constant::getNullValue(Ops.back()->getType()));
@@ -1901,7 +1901,7 @@ let HasMasked = false,
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
// insert poison passthru
- if (PolicyAttrs == TAIL_AGNOSTIC)
+ if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops.back()->getType()};
}] in {
@@ -2043,7 +2043,7 @@ let HasMasked = false,
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
// insert poison passthru
- if (PolicyAttrs == TAIL_AGNOSTIC)
+ if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
IntrinsicTypes = {ResultType, Ops[2]->getType(), Ops.back()->getType()};
}] in {
@@ -2240,7 +2240,7 @@ let HasMasked = false,
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
// insert poison passthru
- if (PolicyAttrs == TAIL_AGNOSTIC)
+ if (PolicyAttrs & RVV_VTA)
Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
IntrinsicTypes = {ResultType, Ops.back()->getType()};
}] in {
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index e3dd4d262969..545ae0ba1780 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -426,12 +426,11 @@ class RVVIntrinsic {
return PolicyAttrs;
}
unsigned getPolicyAttrsBits() const {
- // Return following value.
- // constexpr unsigned TAIL_UNDISTURBED = 0;
- // constexpr unsigned TAIL_AGNOSTIC = 1;
- // constexpr unsigned TAIL_AGNOSTIC_MASK_AGNOSTIC = 3;
- // FIXME: how about value 2
- // int PolicyAttrs = TAIL_UNDISTURBED;
+ // CGBuiltin.cpp
+ // The 0th bit simulates the `vta` of RVV
+ // The 1st bit simulates the `vma` of RVV
+ // int PolicyAttrs = 0;
+
assert(PolicyAttrs.IsUnspecified == false);
if (PolicyAttrs.isTUMAPolicy())
@@ -442,10 +441,6 @@ class RVVIntrinsic {
return 0;
if (PolicyAttrs.isTAMUPolicy())
return 1;
- if (PolicyAttrs.isTUPolicy())
- return 0;
- if (PolicyAttrs.isTAPolicy())
- return 1;
llvm_unreachable("unsupport policy");
return 0;
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 192a9181989b..f72e04a425d9 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -19480,10 +19480,11 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
unsigned NF = 1;
- constexpr unsigned TAIL_UNDISTURBED = 0;
- constexpr unsigned TAIL_AGNOSTIC = 1;
- constexpr unsigned TAIL_AGNOSTIC_MASK_AGNOSTIC = 3;
- int PolicyAttrs = TAIL_UNDISTURBED;
+ // The 0th bit simulates the `vta` of RVV
+ // The 1st bit simulates the `vma` of RVV
+ constexpr unsigned RVV_VTA = 0x1;
+ constexpr unsigned RVV_VMA = 0x2;
+ int PolicyAttrs = 0;
bool IsMasked = false;
// Required for overloaded intrinsics.
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