[PATCH] D141762: [8/15][Clang][RISCV][NFC] Always emit PolicyAttr in riscv_vector_builtin_cg.inc
Yueh-Ting (eop) Chen via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Tue Jan 24 02:25:30 PST 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5a1c6ec1041f: [8/15][Clang][RISCV][NFC] Always emit PolicyAttr in riscv_vector_builtin_cg.inc (authored by eopXD).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D141762/new/
https://reviews.llvm.org/D141762
Files:
clang/utils/TableGen/RISCVVEmitter.cpp
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===================================================================
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -163,18 +163,11 @@
OS << " ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
if (RVVI->getNF() >= 2)
OS << " NF = " + utostr(RVVI->getNF()) + ";\n";
- // We had initialized PolicyAttrs as TU/TUMU in CodeGen function.
- if (!RVVI->getPolicyAttrs().isTUPolicy() &&
- !RVVI->getPolicyAttrs().isTUMUPolicy() && !RVVI->hasPassthruOperand() &&
- !RVVI->hasManualCodegen() && RVVI->hasVL())
- OS << " PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
+
+ OS << " PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
if (RVVI->hasManualCodegen()) {
- OS << " PolicyAttrs = " << RVVI->getPolicyAttrsBits() << ";\n";
- if (RVVI->isMasked())
- OS << "IsMasked = true;\n";
- else
- OS << "IsMasked = false;\n";
+ OS << "IsMasked = " << (RVVI->isMasked() ? "true" : "false") << ";\n";
OS << RVVI->getManualCodegen();
OS << "break;\n";
return;
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