[PATCH] D142065: [SVE] Fix incorrect lowering of predicate permute builtins.

[Paul Walker via Phabricator via cfe-commits]

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When lowering predicate permute builtins we incorrectly assume only
the typically "active" bits for the specified element type play a
role with all other bits zero'd.  This is not the case because all
bits are significant, with the element type specifying how they
are grouped:

  b8  - permute using a block size of 1 bit
  b16 - permute using a block size of 2 bits
  b32 - permute using a block size of 4 bits
  b64 - permute using a block size of 8 bits

The affected builtins are svrev, svtrn1, svtrn2, svuzp1, svuzp2,
svzip1 and svzip2.

This patch adds new intrinsics to support these operations and
changes the builtin lowering code to emit them.  The b8 case remains
unchanged because for that operation the existing intrinsics work
as required and their support for other predicate types has been
maintained as useful if only as a way to test the correctness of
their matching ISD nodes that code generation relies on.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D142065

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll

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