[clang] f601039 - [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march
Kito Cheng via cfe-commits
cfe-commits at lists.llvm.org
Fri Jan 13 07:58:38 PST 2023
Author: Kito Cheng
Date: 2023-01-13T23:58:31+08:00
New Revision: f601039e8165cb2a49c783ccf4aafd1f7b326a63
URL: https://github.com/llvm/llvm-project/commit/f601039e8165cb2a49c783ccf4aafd1f7b326a63
DIFF: https://github.com/llvm/llvm-project/commit/f601039e8165cb2a49c783ccf4aafd1f7b326a63.diff
LOG: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march
RISC-V supports `-march`, `-mtune`, and `-mcpu`: `-march` provides the
architecture extension information, `-mtune` provide the pipeline model, and
`-mcpu` provides both.
What's the priority among those options for now(w/o this patch)?
Pipeline model:
- Take from `-mtune` if present.
- Take from `-mcpu` if present
- Use the default pipeline model: `generic-rv32` or `generic-rv64`
Architecture extension has quite complicated behavior now:
- Take union from `-march` and `-mcpu` if both are present.
- Take from `-march` if present.
- Take from `-mcpu` if present.
- Implied from `-mabi` if present.
- Use the default architecture depending on the target triple
We treat `-mcpu`/`-mtune` and `-mcpu`/`-march` differently, and it's
kind of counterintuitive: -march is explicitly specified but ignored.
This patch adjusts the priority between `-mcpu`/`-march`, letting it use
architecture extension information from `-march` if it's present.
So the priority of architecture extension information becomes:
- Take from `-march` if present.
- Take from `-mcpu` if present.
- Implied from `-mabi` if present.
- Use the default architecture depending on the target triple
And this also match what we implement in RISC-V GCC too.
Reviewed By: craig.topper, MaskRay
Differential Revision: https://reviews.llvm.org/D140693
Added:
clang/test/Driver/riscv-march-mcpu-mtune.c
Modified:
clang/docs/ReleaseNotes.rst
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Driver/riscv-cpus.c
clang/test/Driver/riscv-default-features.c
llvm/include/llvm/Support/RISCVISAInfo.h
llvm/lib/Support/RISCVISAInfo.cpp
Removed:
################################################################################
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 632862aaa0237..92de83bae01cd 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -803,6 +803,9 @@ RISC-V Support in Clang
- ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for ``-mcpu``.
Use ``sifive-e76``, ``sifive-s76``, or ``sifive-u74`` instead.
- Native detections via ``-mcpu=native`` and ``-mtune=native`` are supported.
+- Fix interaction of ``-mcpu`` and ``-march``, RISC-V backend will take the
+ architecture extension union of ``-mcpu`` and ``-march`` before, and now will
+ take architecture extensions from ``-march`` if both are given.
X86 Support in Clang
--------------------
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 5c11064d81d59..4c34c09d55895 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -43,7 +43,8 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
}
(*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); });
+ Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
+ /*AddAllExtensions=*/true);
return true;
}
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index eb05569f8bc1d..1753251341b61 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -9,12 +9,14 @@
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-base | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-BASE %s
// MCPU-SYNTACORE-SCR1-BASE: "-target-cpu" "syntacore-scr1-base"
-// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c" "-target-feature" "-64bit"
+// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "-64bit"
// MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32"
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-max | FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-MAX %s
// MCPU-SYNTACORE-SCR1-MAX: "-target-cpu" "syntacore-scr1-max"
-// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c" "-target-feature" "-64bit"
+// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "-64bit"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
// We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
@@ -80,42 +82,48 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s
// MCPU-ABI-SIFIVE-S21: "-nostdsysteminc" "-target-cpu" "sifive-s21"
// MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a"
-// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c"
+// MCPU-ABI-SIFIVE-S21: "-target-feature" "+64bit"
// MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64"
// mcpu with mabi option
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
-// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+64bit"
// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
// mcpu with default march
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s54 | FileCheck -check-prefix=MCPU-SIFIVE-S54 %s
// MCPU-SIFIVE-S54: "-nostdsysteminc" "-target-cpu" "sifive-s54"
// MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
-// MCPU-SIFIVE-S54: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-SIFIVE-S54: "-target-feature" "+c"
+// MCPU-SIFIVE-S54: "-target-feature" "+64bit"
// MCPU-SIFIVE-S54: "-target-abi" "lp64d"
// mcpu with mabi option
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s76 | FileCheck -check-prefix=MCPU-SIFIVE-S76 %s
// MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76"
// MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
-// MCPU-SIFIVE-S76: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-SIFIVE-S76: "-target-feature" "+c"
+// MCPU-SIFIVE-S76: "-target-feature" "+64bit"
// MCPU-SIFIVE-S76: "-target-abi" "lp64d"
// mcpu with default march
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s
// MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
// MCPU-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
-// MCPU-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-SIFIVE-U54: "-target-feature" "+c"
+// MCPU-SIFIVE-U54: "-target-feature" "+64bit"
// MCPU-SIFIVE-U54: "-target-abi" "lp64d"
// mcpu with mabi option
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U54 %s
// MCPU-ABI-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
// MCPU-ABI-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
-// MCPU-ABI-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-U54: "-target-feature" "+c"
+// MCPU-ABI-SIFIVE-U54: "-target-feature" "+64bit"
// MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64"
// mcpu with default march
@@ -129,7 +137,8 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s
// MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74"
// MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
-// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c"
+// MCPU-ABI-SIFIVE-U74: "-target-feature" "+64bit"
// MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64"
// march overwrite mcpu's default march
diff --git a/clang/test/Driver/riscv-default-features.c b/clang/test/Driver/riscv-default-features.c
index c154b7879b047..6e48f7cc37dcb 100644
--- a/clang/test/Driver/riscv-default-features.c
+++ b/clang/test/Driver/riscv-default-features.c
@@ -1,8 +1,10 @@
// RUN: %clang --target=riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
// RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
-// RV32: "target-features"="+32bit,+a,+c,+m,+relax,-save-restore"
-// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+// RV32: "target-features"="+32bit,+a,+c,+m,+relax,
+// RV32-SAME: -save-restore
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,
+// RV64-SAME: -save-restore
// Dummy function
int foo(void){
diff --git a/clang/test/Driver/riscv-march-mcpu-mtune.c b/clang/test/Driver/riscv-march-mcpu-mtune.c
new file mode 100644
index 0000000000000..90b7173974a29
--- /dev/null
+++ b/clang/test/Driver/riscv-march-mcpu-mtune.c
@@ -0,0 +1,74 @@
+// Check the priority between -mcpu, -mtune and -march
+
+// sifive-e76 is rv32imafc and sifive-e31 is rv32imac
+
+// -mcpu, -mtune and -march are not given, pipeline model and arch ext. use
+// default setting.
+// RUN: %clang --target=riscv32-elf -### -c %s 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-DEFAULT %s
+// CHECK-DEFAULT: "-target-cpu" "generic-rv32"
+// CHECK-DEFAULT: "-target-feature" "+m" "-target-feature" "+a"
+// CHECK-DEFAULT: "-target-feature" "+c"
+
+// -mtune is given, pipeline model take from -mtune, arch ext. use
+// default setting.
+// RUN: %clang --target=riscv32 -mtune=sifive-e76 -### -c %s 2>&1 \
+// RUN: | FileCheck -check-prefix=MTUNE-E76 %s
+// MTUNE-E76: "-target-feature" "+m" "-target-feature" "+a"
+// MTUNE-E76: "-target-feature" "+c"
+// MTUNE-E76: "-target-feature" "-f"
+// MTUNE-E76: "-tune-cpu" "sifive-e76"
+
+// -march is given, arch ext. take from -march, pipeline model use
+// default setting.
+// RUN: %clang --target=riscv32 -### -c %s -march=rv32imafdc 2>&1 \
+// RUN: | FileCheck -check-prefix=MARCH-RV32IMAFDC %s
+// MARCH-RV32IMAFDC: "-target-cpu" "generic-rv32"
+// MARCH-RV32IMAFDC: "-target-feature" "+m" "-target-feature" "+a"
+// MARCH-RV32IMAFDC: "-target-feature" "+f" "-target-feature" "+d"
+// MARCH-RV32IMAFDC: "-target-feature" "+c"
+
+// -mcpu is given, pipeline model and arch ext. from -mcpu.
+// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e76 2>&1 \
+// RUN: | FileCheck -check-prefix=MCPU-E76 %s
+// MCPU-E76: "-target-cpu" "sifive-e76"
+// MCPU-E76: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-E76: "-target-feature" "+f" "-target-feature" "+c"
+
+// -mcpu and -mtune are given, so pipeline model take from -mtune, and arch ext.
+// take from -mcpu since -march is not given.
+// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e76 -mtune=sifive-e31 2>&1 \
+// RUN: | FileCheck -check-prefix=MCPU-E76-MTUNE-E31 %s
+// MCPU-E76-MTUNE-E31: "-target-cpu" "sifive-e76"
+// MCPU-E76-MTUNE-E31: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-E76-MTUNE-E31: "-target-feature" "+f" "-target-feature" "+c"
+// MCPU-E76-MTUNE-E31: "-tune-cpu" "sifive-e31"
+
+// RUN: %clang --target=riscv32 -### -c %s -mtune=sifive-e76 -mcpu=sifive-e31 2>&1 \
+// RUN: | FileCheck -check-prefix=MTUNE-E76-MCPU-E31 %s
+// MTUNE-E76-MCPU-E31: "-target-cpu" "sifive-e31"
+// MTUNE-E76-MCPU-E31: "-target-feature" "+m" "-target-feature" "+a"
+// MTUNE-E76-MCPU-E31: "-target-feature" "+c"
+// MTUNE-E76-MCPU-E31: "-target-feature" "-f"
+// MTUNE-E76-MCPU-E31: "-tune-cpu" "sifive-e76"
+
+// -mcpu and -march are given, so pipeline model take from -mcpu since -mtune is
+// not given, and arch ext. take from -march.
+// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e31 -march=rv32ic 2>&1 \
+// RUN: | FileCheck -check-prefix=MCPU-E31-MARCH-RV32I %s
+// MCPU-E31-MARCH-RV32I: "-target-cpu" "sifive-e31"
+// MCPU-E31-MARCH-RV32I: "-target-feature" "+c"
+// MCPU-E31-MARCH-RV32I: "-target-feature" "-m"
+// MCPU-E31-MARCH-RV32I: "-target-feature" "-a"
+// MCPU-E31-MARCH-RV32I: "-target-feature" "-f"
+
+// -mcpu, -march and -mtune are given, so pipeline model take from -mtune
+// and arch ext. take from -march, -mcpu is unused.
+// RUN: %clang --target=riscv32 -### -c %s -mcpu=sifive-e31 -mtune=sifive-e76 -march=rv32ic 2>&1 \
+// RUN: | FileCheck -check-prefix=MCPU-E31-MTUNE-E76-MARCH-RV32I %s
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-cpu" "sifive-e31"
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "+c"
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-m"
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-a"
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-f"
+// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-tune-cpu" "sifive-e76"
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/Support/RISCVISAInfo.h
index 746ef5f947b06..50eca534bddc2 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -56,7 +56,8 @@ class RISCVISAInfo {
/// Convert RISCV ISA info to a feature vector.
void toFeatures(std::vector<StringRef> &Features,
- std::function<StringRef(const Twine &)> StrAlloc) const;
+ llvm::function_ref<StringRef(const Twine &)> StrAlloc,
+ bool AddAllExtensions) const;
const OrderedExtensionMap &getExtensions() const { return Exts; };
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index d82f337feb534..a4e6a8976efe9 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -331,7 +331,8 @@ bool RISCVISAInfo::compareExtension(const std::string &LHS,
void RISCVISAInfo::toFeatures(
std::vector<StringRef> &Features,
- std::function<StringRef(const Twine &)> StrAlloc) const {
+ llvm::function_ref<StringRef(const Twine &)> StrAlloc,
+ bool AddAllExtensions) const {
for (auto const &Ext : Exts) {
StringRef ExtName = Ext.first;
@@ -344,6 +345,19 @@ void RISCVISAInfo::toFeatures(
Features.push_back(StrAlloc("+" + ExtName));
}
}
+ if (AddAllExtensions) {
+ for (const RISCVSupportedExtension &Ext : SupportedExtensions) {
+ if (Exts.count(Ext.Name))
+ continue;
+ Features.push_back(StrAlloc(Twine("-") + Ext.Name));
+ }
+
+ for (const RISCVSupportedExtension &Ext : SupportedExperimentalExtensions) {
+ if (Exts.count(Ext.Name))
+ continue;
+ Features.push_back(StrAlloc(Twine("-experimental-") + Ext.Name));
+ }
+ }
}
// Extensions may have a version number, and may be separated by
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