[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

[Brandon Wu via Phabricator via cfe-commits]

4vtomat created this revision.
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LLVM implements the 0.1 draft specification:
https://github.com/riscv/riscv-crypto/releases/download/v20221220/riscv-crypto-spec-vector.pdf
, and current vector crypto extension version can be found in:
https://github.com/riscv/riscv-crypto.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141672

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s
  llvm/test/MC/RISCV/rvv/zvknh.s
  llvm/test/MC/RISCV/rvv/zvkns-invalid.s
  llvm/test/MC/RISCV/rvv/zvkns.s
  llvm/test/MC/RISCV/rvv/zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/zvksed.s
  llvm/test/MC/RISCV/rvv/zvksh.s

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