[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

[Francesco Petrogalli via Phabricator via cfe-commits]

fpetrogalli updated this revision to Diff 486222.
fpetrogalli added a comment.

I have addressed last round of review from @craig.topper and @pcwang-thead:

1. Renamed the RISCV-specific classes for the ProcessorModel.
2. Swapped `tunef` with `f` in `RISCVTuneProcessorModel`.
3. Fixed comment.
4. Aimed for consistency in formatting of TD files.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137517/new/

https://reviews.llvm.org/D137517

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  llvm/include/llvm/CMakeLists.txt
  llvm/include/llvm/TargetParser/CMakeLists.txt
  llvm/include/llvm/TargetParser/RISCVTargetParser.def
  llvm/include/llvm/TargetParser/RISCVTargetParser.h
  llvm/include/llvm/TargetParser/TargetParser.h
  llvm/include/llvm/module.extern.modulemap
  llvm/include/llvm/module.install.modulemap
  llvm/include/llvm/module.modulemap
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/TargetParser/CMakeLists.txt
  llvm/lib/TargetParser/RISCVTargetParser.cpp
  llvm/lib/TargetParser/TargetParser.cpp
  llvm/utils/TableGen/CMakeLists.txt
  llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
  llvm/utils/TableGen/TableGen.cpp
  llvm/utils/TableGen/TableGenBackends.h

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