[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCV.td:572
+                              string default_march = "",
+                              list<SubtargetFeature> tunef = []> :  ProcessorModel<n, m, f, tunef> {
+  string DefaultMarch = default_march;
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80 columns


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Comment at: llvm/lib/Target/RISCV/RISCV.td:623
+                                                                      FeatureStdExtC],
+                                         "rv32imafc", [TuneSiFive7]>;
+
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The formatting is inconsisent. Sometimes the "rv32imafc" is on the end of the previous line. Can we be consistent?


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Comment at: llvm/lib/TargetParser/RISCVTargetParser.cpp:1
+//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
+//
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This comment should match the name of the file.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137517/new/

https://reviews.llvm.org/D137517