[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD added inline comments.


================
Comment at: llvm/lib/Support/RISCVISAInfo.cpp:772
+
+  if ((Exts.count("zvkb") || Exts.count("zvknhb")) && !Exts.count("zve64x"))
+    return createStringError(
----------------
With this check, the check for these extensions on top are redundant.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1675
 
+include "RISCVInstrInfoZvk.td" //SIFIVE
 include "RISCVInstrInfoVPseudos.td"
----------------
Got to remove the company name here ;)


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td:8
+//===----------------------------------------------------------------------===//
+///
+// This file describes the RISC-V instructions from the standard 'Zvk',
----------------
`///` -> `//`, and same below.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807