[PATCH] D139507: [Intrinsic] Add get.rounding as alias to flt.rounds and rename related DAG nodes

[Qiu Chaofan via Phabricator via cfe-commits]

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This is to address the inconsistency between `FLT_ROUNDS_` and `SET_ROUNDING` SDAG node. Rename `FLT_ROUNDS_` to `GET_ROUNDING` and add new `llvm.get.rounding` intrinsic. For compatibility, `@llvm.flt.rounds` is kept.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139507

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-msp430.c
  clang/test/CodeGen/builtins.c
  libcxxabi/test/test_demangle.pass.cpp
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/AArch64/arm64-fpcr.ll
  llvm/test/CodeGen/AArch64/strict-fp-opt.ll
  llvm/test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll
  llvm/test/CodeGen/ARM/fpscr-intrinsics.ll
  llvm/test/CodeGen/ARM/no-fpscr-liveness.ll
  llvm/test/CodeGen/MSP430/flt_rounds.ll
  llvm/test/CodeGen/PowerPC/frounds.ll
  llvm/test/CodeGen/RISCV/flt-rounds.ll
  llvm/test/CodeGen/RISCV/fpenv.ll
  llvm/test/CodeGen/X86/flt-rounds.ll

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