[PATCH] D139398: [AMDGPU] Add bf16 storage support

[Pierre van Houtryve via Phabricator via cfe-commits]

Pierre-vh added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:4819-4831
+    // When we don't have 16 bit instructions, bf16 is illegal and gets
+    // softened to i16 for storage, with float being used for arithmetic.
+    //
+    // After softening, some i16 -> fp32 bf16_to_fp operations can be left over.
+    // Lower those to (f32 (fp_extend (f16 (bitconvert x))))
+    if (!Op->getValueType(0).isFloatingPoint() ||
+        Op->getOperand(0).getValueType() != MVT::i16)
----------------
arsenm wrote:
> Pierre-vh wrote:
> > arsenm wrote:
> > > The generic legalizer should have handled this?
> > It looks like those operations are not implemented in the generic legalizer, e.g. I get 
> > ``` 
> > Do not know how to promote this operator's operand!
> > ```
> Right, this is the code that would go there
Do I just copy/paste this code in that PromoteInt function, and keep a copy here too in LowerOperation? (not really a fan of copy-pasting code in different files, I'd rather keep it all here)
We need to have the lowering too AFAIK, it didn't go well when I tried to remove it


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D139398/new/

https://reviews.llvm.org/D139398